| /u-boot-v2022.01-rc1/board/freescale/corenet_ds/ |
| A D | p4080ds_ddr.c | 89 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
121 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
153 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
185 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
217 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
249 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
281 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
313 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
|
| /u-boot-v2022.01-rc1/drivers/ddr/fsl/ |
| A D | mpc85xx_ddr_gen1.c | 47 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
|
| A D | mpc85xx_ddr_gen2.c | 69 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
|
| A D | arm_ddr_gen3.c | 95 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
|
| A D | util.c | 239 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); in print_ddr_info()
|
| A D | mpc85xx_ddr_gen3.c | 127 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
|
| A D | fsl_ddr_gen4.c | 169 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
|
| A D | ctrl_regs.c | 621 ddr->timing_cfg_1 = (0 in set_timing_cfg_1()
631 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); in set_timing_cfg_1()
|
| /u-boot-v2022.01-rc1/board/freescale/p1010rdb/ |
| A D | ddr.c | 28 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
55 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
|
| /u-boot-v2022.01-rc1/board/kontron/sl28/ |
| A D | ddr.c | 29 .timing_cfg_1 = 0xbcb48c66,
|
| /u-boot-v2022.01-rc1/board/socrates/ |
| A D | sdram.c | 40 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
|
| /u-boot-v2022.01-rc1/board/freescale/ls1043ardb/ |
| A D | ddr.h | 61 .timing_cfg_1 = 0xBBB48C42,
|
| /u-boot-v2022.01-rc1/board/gdsys/mpc8308/ |
| A D | sdram.c | 53 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
|
| /u-boot-v2022.01-rc1/drivers/ram/ |
| A D | mpc83xx_sdram.c | 337 u32 timing_cfg_1; in mpc83xx_sdram_probe() local
683 timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT | in mpc83xx_sdram_probe()
695 out_be32(&im->ddr.timing_cfg_1, timing_cfg_1); in mpc83xx_sdram_probe()
|
| /u-boot-v2022.01-rc1/board/freescale/ls1021aiot/ |
| A D | ls1021aiot.c | 62 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); in ddrmc_init()
|
| /u-boot-v2022.01-rc1/board/freescale/ls1021atsn/ |
| A D | ls1021atsn.c | 40 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); in ddrmc_init()
|
| /u-boot-v2022.01-rc1/board/freescale/mpc837xerdb/ |
| A D | mpc837xerdb.c | 117 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
|
| /u-boot-v2022.01-rc1/board/ids/ids8313/ |
| A D | ids8313.c | 85 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
|
| /u-boot-v2022.01-rc1/board/keymile/km83xx/ |
| A D | km83xx.c | 130 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
|
| /u-boot-v2022.01-rc1/include/ |
| A D | fsl_immap.h | 35 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ member
|
| A D | fsl_ddr_sdram.h | 250 unsigned int timing_cfg_1; member
|
| /u-boot-v2022.01-rc1/board/freescale/p1_p2_rdb_pc/ |
| A D | ddr.c | 222 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, in fixed_sdram()
|
| /u-boot-v2022.01-rc1/arch/powerpc/cpu/mpc83xx/ |
| A D | spd_sdram.c | 538 ddr->timing_cfg_1 = in spd_sdram()
640 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); in spd_sdram()
|
| /u-boot-v2022.01-rc1/board/freescale/ls1021atwr/ |
| A D | ls1021atwr.c | 156 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); in ddrmc_init()
|
| /u-boot-v2022.01-rc1/arch/powerpc/include/asm/ |
| A D | immap_83xx.h | 296 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ member
|