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Searched refs:r3 (Results 1 – 25 of 48) sorted by relevance

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/lk-master/external/platform/pico/rp2_common/pico_bit_ops/
A Dbit_ops_aeabi.S39 bx r3
51 ldr r3, [r3, #CLZ32]
52 bx r3
57 ldr r3, [r3, #CTZ32]
63 ldr r3, [r3, #POPCOUNT32]
70 ldr r3, [r3, #CLZ32]
84 ldr r3, [r3, #CTZ32]
98 ldr r3, [r3, #POPCOUNT32]
111 ldr r3, [r3, #REVERSE32]
118 ldr r3, [r3, #REVERSE32]
[all …]
/lk-master/arch/or1k/
A Dstart.S170 l.add r3, r3, r9
207 l.or r3,r3,r4
217 l.sll r3, r4, r3
218 l.addi r3, r3, -1
221 l.and r3, r4, r3
252 l.add r3, r3, r9
290 l.sll r3, r4, r3
291 l.addi r3, r3, -1
294 l.and r3, r4, r3
364 l.addi r3, r3, 1
[all …]
A Dasm.S15 l.sw 0(r3), r1
16 l.sw 4(r3), r2
17 l.sw 8(r3), r9
18 l.sw 12(r3), r10
19 l.sw 16(r3), r14
20 l.sw 20(r3), r16
21 l.sw 24(r3), r18
22 l.sw 28(r3), r20
23 l.sw 32(r3), r22
24 l.sw 36(r3), r24
[all …]
/lk-master/app/mdebug/
A Dfw-m0sub.S156 lsrs r3, r3, #1 // make room
157 orrs r3, r3, r0 // add bit
288 lsrs r3, r3, #1 // make room
289 orrs r3, r3, r0 // add bit
330 ldr r3, [r3, #COMM_ARG0]
337 lsrs r3, r3, #29
382 ldr r3, [r3, #COMM_ARG0]
390 lsrs r3, r3, #29
416 ldr r3, [r3, #COMM_ARG1]
435 ldr r3, [r3, #COMM_ARG0]
[all …]
/lk-master/external/platform/pico/rp2_common/boot_stage2/
A Dboot2_w25q080.S110 ldr r3, =PADS_QSPI_BASE
121 ldr r3, =XIP_SSI_BASE
139 str r1, [r3, r2]
166 str r1, [r3, #SSI_DR0_OFFSET]
170 ldr r1, [r3, #SSI_DR0_OFFSET]
174 str r1, [r3, #SSI_DR0_OFFSET]
176 str r0, [r3, #SSI_DR0_OFFSET]
177 str r2, [r3, #SSI_DR0_OFFSET]
180 ldr r1, [r3, #SSI_DR0_OFFSET]
181 ldr r1, [r3, #SSI_DR0_OFFSET]
[all …]
A Dboot2_is25lp080.S98 str r1, [r3, #SSI_SSIENR_OFFSET]
102 str r1, [r3, #SSI_BAUDR_OFFSET]
113 str r1, [r3, #SSI_CTRLR0_OFFSET]
117 str r1, [r3, #SSI_SSIENR_OFFSET]
128 str r1, [r3, #SSI_DR0_OFFSET]
132 ldr r1, [r3, #SSI_DR0_OFFSET]
136 str r1, [r3, #SSI_DR0_OFFSET]
138 str r2, [r3, #SSI_DR0_OFFSET]
141 ldr r1, [r3, #SSI_DR0_OFFSET]
142 ldr r1, [r3, #SSI_DR0_OFFSET]
[all …]
A Dboot2_w25x10cl.S86 ldr r3, =XIP_SSI_BASE // Use as base address where possible
91 str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI to allow further config
97 str r1, [r3, #SSI_BAUDR_OFFSET] // Set SSI Clock
117 str r1, [r3, #SSI_CTRLR0_OFFSET]
120 str r1, [r3, #SSI_CTRLR1_OFFSET]
135 str r1, [r3, #SSI_SSIENR_OFFSET]
138 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
140 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
147 ldr r0, [r3, #SSI_SR_OFFSET] // Read status register
162 str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
[all …]
A Dboot2_generic_03h.S67 ldr r3, =XIP_SSI_BASE // Use as base address where possible
71 str r1, [r3, #SSI_SSIENR_OFFSET]
75 str r1, [r3, #SSI_BAUDR_OFFSET]
78 str r1, [r3, #SSI_CTRLR0_OFFSET]
86 str r1, [r3, #SSI_CTRLR1_OFFSET]
90 str r1, [r3, #SSI_SSIENR_OFFSET]
/lk-master/lib/libc/string/arch/arm/arm-m/
A Dmemcpy.S37 eors r3, r0, r1
38 ands r3, #7
42 and r3, r0, #3
44 rsb r3, #4
45 subs r2, r3
51 subs r3, r3, #1
63 subs r3, r3, #1
87 rsb r3, #8
88 subs r2, r3
94 subs r3, r3, #1
[all …]
A Dmemset.S35 and r3, r0, #7
36 cbz r3, .L_prepare_dwordwise
37 rsb r3, #8
38 subs r2, r3
42 subs r3, r3, #1
54 lsrs r3, r2, #3
58 subs r3, r3, #1
/lk-master/external/platform/pico/rp2_common/pico_mem_ops/
A Dmem_ops_aeabi.S48 bx r3
66 ldr r3, [r3, #MEMSET]
67 bx r3
76 ldr r3, [r3, #MEMSET4]
77 bx r3
82 ldr r3, [r3, #MEMCPY4]
83 bx r3
89 ldr r3, [r3, #MEMSET]
90 bx r3
96 ldr r3, [r3, #MEMCPY]
[all …]
/lk-master/external/platform/pico/rp2_common/pico_double/
A Ddouble_aeabi.S76 mov r1, r3
92 ldr r3, [r3, #\SF_TABLE_OFFSET]
100 ldr r3, [r3, #\SF_TABLE_OFFSET]
198 asrs r3, r3, #24
220 asrs r3, r3, #21
292 eors r3,r1 @ restore r3
294 cmp r3,r1
301 cmp r1,r3
308 adds r3,r3
417 ldr r3, [r3]
[all …]
A Ddouble_v1_rom_shim.S90 pop {r0-r3}
99 pop {r0-r3}
260 add r1,r3
311 lsls r3,r3,r7
985 muls r3,r3
1004 muls r3,r3
1029 mul32_32_64 r2,r1, r3,r4, r5,r6,r7,r3,r4
1030 adds r3,r3,r3
1032 adds r3,r3,r3
1169 adcs r3,r5 @ r2:r3 x+(y>>i)
[all …]
/lk-master/external/platform/pico/rp2_common/pico_divider/
A Ddivider.S272 cmp r3,#0
284 dneg r2,r3
308 movs r3,#0
376 cmp r3,#0
471 lsls r3,#17 @ r3:r7 is (x0l*q)<<17
477 adds r3,r3
488 lsls r3,#4 @ r3:r7 is (x0l*q)<<4
495 lsls r3,#20 @ r3:r7 is (x0h*q)<<4
585 movs r3,r1 @ y now in r2:r3
681 @ r2:r3 x0
[all …]
/lk-master/external/platform/pico/rp2_common/hardware_divider/
A Ddivider.S23 ldr r3, =(SIO_BASE)
24 str r0, [r3, #SIO_DIV_SDIVIDEND_OFFSET]
25 str r1, [r3, #SIO_DIV_SDIVISOR_OFFSET]
28 ldr r1, [r3, #SIO_DIV_REMAINDER_OFFSET]
29 ldr r0, [r3, #SIO_DIV_QUOTIENT_OFFSET]
37 ldr r3, =(SIO_BASE)
38 str r0, [r3, #SIO_DIV_UDIVIDEND_OFFSET]
39 str r1, [r3, #SIO_DIV_UDIVISOR_OFFSET]
42 ldr r1, [r3, #SIO_DIV_REMAINDER_OFFSET]
43 ldr r0, [r3, #SIO_DIV_QUOTIENT_OFFSET]
/lk-master/external/platform/pico/rp2_common/pico_float/
A Dfloat_aeabi.S55 movs r3, #1
58 adds r2, r3
66 movs r3, #1
89 ldr r3, [r3, #\SF_TABLE_OFFSET]
90 bx r3
95 ldr r3, [r3, #\SF_TABLE_OFFSET]
99 bx r3
158 asrs r3, r3, #24
188 asrs r3, r3, #24
366 ldr r3, [r3]
[all …]
A Dfloat_v1_rom_shim.S124 mov r2,r3
125 mov r3,r4
184 bx r3
236 eors r0,r3
281 mvns r0,r3
308 movs r1,r3
312 cmp r2,r3
316 mvns r0,r3
325 lsls r3,#31
334 orrs r1,r3
[all …]
/lk-master/external/platform/pico/rp2_common/pico_int64_ops/
A Dpico_int64_ops_aeabi.S16 muls r3, r0
17 adds r1, r3
20 uxth r3, r0
21 muls r3, r1
29 lsls r4, r3, #16
30 lsrs r3, #16
33 adcs r1, r3
34 lsls r3, r2, #16
36 adds r0, r3
/lk-master/lib/libc/string/arch/arm/arm/
A Dmemcpy.S33 subs r3, r0, r1
34 cmphi r2, r3
44 eor r3, r0, r1
45 tst r3, #3
92 ldr r3, [r1], #4
94 str r3, [r0], #4
103 ldrb r3, [r1], #1
105 strb r3, [r0], #1
131 strvsb r3, [r0], #1
136 stmmiia r0!, {r3-r4}
[all …]
A Dmemset.S46 mov r3, r1
55 stmia r0!, { r1, r3, r4, r5 }
57 stmia r0!, { r1, r3, r4, r5 }
82 lsl r3, r0, #28
83 rsb r3, r3, #0
84 msr CPSR_f, r3 // move into NZCV fields in CPSR
94 sub r2, r2, r3, lsr #28
/lk-master/external/platform/nrfx/soc/
A Dnrfx_atomic_internal.h62 strex r3, r5, [r4] in nrfx_atomic_internal_mov()
63 cmp r3, #0 in nrfx_atomic_internal_mov()
82 strex r3, r5, [r4] in nrfx_atomic_internal_orr()
83 cmp r3, #0 in nrfx_atomic_internal_orr()
101 strex r3, r5, [r4] in nrfx_atomic_internal_and()
102 cmp r3, #0 in nrfx_atomic_internal_and()
121 cmp r3, #0 in nrfx_atomic_internal_eor()
140 cmp r3, #0 in nrfx_atomic_internal_add()
159 cmp r3, #0 in nrfx_atomic_internal_sub()
174 #define STR_RES r3 in nrfx_atomic_internal_cmp_exch()
[all …]
/lk-master/external/platform/pico/rp2_common/boot_stage2/asminclude/boot2_helpers/
A Dread_flash_sreg.S19 str r0, [r3, #SSI_DR0_OFFSET]
21 str r0, [r3, #SSI_DR0_OFFSET]
25 ldr r0, [r3, #SSI_DR0_OFFSET]
26 ldr r0, [r3, #SSI_DR0_OFFSET]
/lk-master/app/lpcboot/
A Dminiloader.S26 ldr r3, [r0], #4
27 str r3, [r2], #4
39 ldr r3, [r0]
44 cmp r1, r3
/lk-master/external/platform/nrfx/mdk/
A Dgcc_startup_nrf5340_network.S249 ldr r3, =__bss_start__
251 subs r3, r3, r2
255 subs r3, r3, #4
256 ldr r0, [r1,r3]
257 str r0, [r2,r3]
A Dgcc_startup_nrf51.S166 ldr r3, =__bss_start__
168 subs r3, r3, r2
172 subs r3, r3, #4
173 ldr r0, [r1,r3]
174 str r0, [r2,r3]

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