1 /*
2 * Copyright (C) 2017-2019 Alibaba Group Holding Limited
3 */
4
5
6 /******************************************************************************
7 * @file core_804.h
8 * @brief CSI 804 Core Peripheral Access Layer Header File
9 * @version V1.0
10 * @date 02. June 2017
11 ******************************************************************************/
12
13 #ifndef __CORE_804_H_GENERIC
14 #define __CORE_804_H_GENERIC
15
16 #include <stdint.h>
17
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21
22 /*******************************************************************************
23 * CSI definitions
24 ******************************************************************************/
25 /**
26 \ingroup Ck804
27 @{
28 */
29
30 /* CSI CK804 definitions */
31 #define __CK804_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
32 #define __CK804_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
33 #define __CK804_CSI_VERSION ((__CK804_CSI_VERSION_MAIN << 16U) | \
34 __CK804_CSI_VERSION_SUB ) /*!< CSI HAL version number */
35
36 #ifndef __CK80X
37 #define __CK80X (0x03U) /*!< CK80X Core */
38 #endif
39
40 /* __FPU_USED indicates whether an FPU is used or not. */
41 #define __FPU_USED 1U
42
43 #if defined ( __GNUC__ )
44 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
45 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
46 #endif
47 #endif
48
49 #ifdef __cplusplus
50 }
51 #endif
52
53 #endif /* __CORE_CK804_H_GENERIC */
54
55 #ifndef __CSI_GENERIC
56
57 #ifndef __CORE_CK804_H_DEPENDANT
58 #define __CORE_CK804_H_DEPENDANT
59
60 #ifdef __cplusplus
61 extern "C" {
62 #endif
63
64 /* check device defines and use defaults */
65 #ifndef __CK804_REV
66 #define __CK804_REV 0x0000U
67 #endif
68
69 #ifndef __VIC_PRIO_BITS
70 #define __VIC_PRIO_BITS 2U
71 #endif
72
73 #ifndef __Vendor_SysTickConfig
74 #define __Vendor_SysTickConfig 1U
75 #endif
76
77 #ifndef __GSR_GCR_PRESENT
78 #define __GSR_GCR_PRESENT 0U
79 #endif
80
81 #ifndef __MPU_PRESENT
82 #define __MPU_PRESENT 1U
83 #endif
84
85 #ifndef __ICACHE_PRESENT
86 #define __ICACHE_PRESENT 1U
87 #endif
88
89 #ifndef __DCACHE_PRESENT
90 #define __DCACHE_PRESENT 1U
91 #endif
92
93 #include <core/csi_gcc.h>
94
95 /* IO definitions (access restrictions to peripheral registers) */
96 /**
97 \defgroup CSI_glob_defs CSI Global Defines
98
99 <strong>IO Type Qualifiers</strong> are used
100 \li to specify the access to peripheral variables.
101 \li for automatic generation of peripheral register debug information.
102 */
103 #ifdef __cplusplus
104 #define __I volatile /*!< Defines 'read only' permissions */
105 #else
106 #define __I volatile const /*!< Defines 'read only' permissions */
107 #endif
108 #define __O volatile /*!< Defines 'write only' permissions */
109 #define __IO volatile /*!< Defines 'read / write' permissions */
110
111 /* following defines should be used for structure members */
112 #define __IM volatile const /*! Defines 'read only' structure member permissions */
113 #define __OM volatile /*! Defines 'write only' structure member permissions */
114 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
115
116 /*@} end of group CK804 */
117
118 /*******************************************************************************
119 * Register Abstraction
120 Core Register contain:
121 - Core Register
122 - Core VIC Register
123 - Core Cache Register
124 - Core CoreTIM Register
125 ******************************************************************************/
126 /**
127 \defgroup CSI_core_register Defines and Type Definitions
128 \brief Type definitions and defines for CK80X processor based devices.
129 */
130
131 /**
132 \ingroup CSI_core_register
133 \defgroup CSI_CORE Status and Control Registers
134 \brief Core Register type definitions.
135 @{
136 */
137
138 /**
139 \brief Access Processor Status Register(PSR)struct definition.
140 */
141 typedef union {
142 struct {
143 uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
144 uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
145 uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
146 uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
147 uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
148 uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
149 uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
150 uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
151 uint32_t _reserved2: 1; /*!< bit: 24 Reserved */
152 uint32_t SV: 1; /*!< bit: 25 Stacked valid */
153 uint32_t SD: 1; /*!< bit: 26 Stacked dirty */
154 uint32_t SC: 1; /*!< bit: 27 Secure call bit */
155 uint32_t HS: 1; /*!< bit: 28 Hardware stacked bit */
156 uint32_t SP: 1; /*!< bit: 29 Secure pending bit */
157 uint32_t T: 1; /*!< bit: 30 TEE mode bit */
158 uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
159 } b; /*!< Structure Access by bit */
160 uint32_t w; /*!< Type Access by whole register */
161 } PSR_Type;
162
163 /* PSR Register Definitions */
164 #define PSR_S_Pos 31U /*!< PSR: S Position */
165 #define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
166
167 #define PSR_T_Pos 30U /*!< PSR: T Position */
168 #define PSR_T_Msk (1UL << PSR_T_Pos) /*!< PSR: T Mask */
169
170 #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
171 #define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
172
173 #define PSR_MM_Pos 9U /*!< PSR: MM Position */
174 #define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
175
176 #define PSR_EE_Pos 8U /*!< PSR: EE Position */
177 #define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
178
179 #define PSR_IC_Pos 7U /*!< PSR: IC Position */
180 #define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
181
182 #define PSR_IE_Pos 6U /*!< PSR: IE Position */
183 #define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
184
185 #define PSR_C_Pos 0U /*!< PSR: C Position */
186 #define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
187
188 /**
189 \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
190 */
191 typedef union {
192 struct {
193 uint32_t MP: 1; /*!< bit: 0.. 1 memory protection settings */
194 uint32_t _reserved0: 6; /*!< bit: 2.. 6 Reserved */
195 uint32_t BE: 1; /*!< bit: 7 Endian mode */
196 uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
197 uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
198 uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
199 uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
200 } b; /*!< Structure Access by bit */
201 uint32_t w; /*!< Type Access by whole register */
202 } CCR_Type;
203
204 /* CCR Register Definitions */
205 #define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
206 #define CCR_BE_V2_Msk (0x1UL << CCR_BE_V2_Pos) /*!< CCR: BE_V2 Mask */
207
208 #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
209 #define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
210
211 #define CCR_BE_Pos 7U /*!< CCR: BE Position */
212 #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
213
214 #define CCR_MP_Pos 0U /*!< CCR: MP Position */
215 #define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
216
217 /**
218 \brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
219 */
220 typedef union {
221 struct {
222 uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
223 uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
224 uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
225 uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
226 uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
227 uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
228 uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
229 uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
230 uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
231 uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
232 uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
233 uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
234 uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
235 uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
236 uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
237 uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
238 uint32_t S0: 1; /*!< bit: 24 Security property settings */
239 uint32_t S1: 1; /*!< bit: 25 Security property settings */
240 uint32_t S2: 1; /*!< bit: 26 Security property settings */
241 uint32_t S3: 1; /*!< bit: 27 Security property settings */
242 uint32_t S4: 1; /*!< bit: 28 Security property settings */
243 uint32_t S5: 1; /*!< bit: 29 Security property settings */
244 uint32_t S6: 1; /*!< bit: 30 Security property settings */
245 uint32_t S7: 1; /*!< bit: 31 Security property settings */
246 } b; /*!< Structure Access by bit */
247 uint32_t w; /*!< Type Access by whole register */
248 } CAPR_Type;
249
250 /* CAPR Register Definitions */
251 #define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
252 #define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
253
254 #define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
255 #define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
256
257 #define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
258 #define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
259
260 #define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
261 #define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
262
263 #define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
264 #define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
265
266 #define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
267 #define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
268
269 #define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
270 #define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
271
272 #define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
273 #define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
274
275 #define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
276 #define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
277
278 #define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
279 #define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
280
281 #define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
282 #define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
283
284 #define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
285 #define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
286
287 #define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
288 #define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
289
290 #define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
291 #define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
292
293 #define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
294 #define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
295
296 #define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
297 #define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
298
299 #define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
300 #define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
301
302 #define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
303 #define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
304
305 #define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
306 #define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
307
308 #define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
309 #define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
310
311 #define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
312 #define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
313
314 #define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
315 #define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
316
317 #define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
318 #define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
319
320 #define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
321 #define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
322
323 /**
324 \brief Consortium definition for accessing control register(PACR, CR<20,0>).
325 */
326 typedef union {
327 struct {
328 uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
329 uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
330 uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
331 uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
332 } b; /*!< Structure Access by bit */
333 uint32_t w; /*!< Type Access by whole register */
334 } PACR_Type;
335
336 /* PACR Register Definitions */
337 #define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
338 #define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
339
340 #define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
341 #define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
342
343 #define PACR_E_Pos 0U /*!< PACR: E Position */
344 #define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
345
346 /**
347 \brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
348 */
349 typedef union {
350 struct {
351 uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
352 uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
353 } b; /*!< Structure Access by bit */
354 uint32_t w; /*!< Type Access by whole register */
355 } PRSR_Type;
356
357 /* PRSR Register Definitions */
358 #define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
359 #define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
360
361 /**
362 \brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
363 */
364 typedef union {
365 struct {
366 uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
367 uint32_t BE: 1; /*!< bit: 1 System bus support burst transer */
368 uint32_t IPE: 1; /*!< bit: 2 Instruction prefetch function enable */
369 uint32_t RPE: 1; /*!< bit: 3 Function return instruction RTS will speculate execution */
370 uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
371 uint32_t _reserved1: 9; /*!< bit: 5..13 Reserved */
372 uint32_t ISE: 1; /*!< bit: 14 Interrupt SP enable */
373 uint32_t HS_EXP: 1; /*!< bit: 15 Exception bit for TEE world switch */
374 uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
375 } b;
376 uint32_t w;
377 } CHR_Type;
378
379 /* CHR Register Definitions */
380 #define CHR_BE_Pos 1U /*!< CHR: BE Position */
381 #define CHR_BE_Msk (1UL << CHR_BE_Pos) /*!< CHR: BE Mask */
382 #define CHR_IPE_Pos 1U /*!< CHR: IPE Position */
383 #define CHR_IPE_Msk (1UL << CHR_IPE_Pos) /*!< CHR: IPE Mask */
384 #define CHR_RPE_Pos 1U /*!< CHR: RPE Position */
385 #define CHR_RPE_Msk (1UL << CHR_RPE_Pos) /*!< CHR: RPE Mask */
386 #define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
387 #define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
388 #define CHR_ISE_Pos 14U /*!< CHR: ISE Position */
389 #define CHR_ISE_Msk (0x1UL << CHR_ISE_Pos) /*!< CHR: ISE Mask */
390 #define CHR_HS_EXP_Pos 15U /*!< CHR: HS_EXP Position */
391 #define CHR_HS_EXP_Msk (0x1UL << CHR_HS_EXP_Pos) /*!< CHR: HS_EXP Mask */
392 #define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
393 #define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
394
395 /*@} end of group CSI_CORE */
396
397
398 /**
399 \ingroup CSI_core_register
400 \defgroup CSI_VIC Vectored Interrupt Controller (VIC)
401 \brief Type definitions for the VIC Registers
402 @{
403 */
404
405 /**
406 \brief Access to the structure of a vector interrupt controller.
407 */
408 typedef struct {
409 __IOM uint32_t ISER[4U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
410 uint32_t RESERVED0[12U];
411 __IOM uint32_t IWER[4U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
412 uint32_t RESERVED1[12U];
413 __IOM uint32_t ICER[4U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
414 uint32_t RESERVED2[12U];
415 __IOM uint32_t IWDR[4U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
416 uint32_t RESERVED3[12U];
417 __IOM uint32_t ISPR[4U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
418 uint32_t RESERVED4[12U];
419 __IOM uint32_t ISSR[4U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
420 uint32_t RESERVED5[12U];
421 __IOM uint32_t ICPR[4U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
422 uint32_t RESERVED6[12U];
423 __IOM uint32_t ICSR[4U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
424 uint32_t RESERVED7[12U];
425 __IOM uint32_t IABR[4U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
426 uint32_t RESERVED8[60U];
427 __IOM uint32_t IPR[32U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
428 uint32_t RESERVED9[480U];
429 __IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
430 __IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
431 __IOM uint32_t TSPEND; /*!< Offset: 0xB08 (R/W) Task pending register */
432 __IOM uint32_t TSABR; /*!< Offset: 0xB0c (R/W) Tspend acknowledge register */
433 __IOM uint32_t TSPR; /*!< Offset: 0xB10 (R/W) Tspend priority register */
434 } VIC_Type;
435
436 /*@} end of group CSI_VIC */
437
438 /**
439 \ingroup CSI_core_register
440 \defgroup CSI_CACHE
441 \brief Type definitions for the cache Registers
442 @{
443 */
444
445 /**
446 \brief On chip cache structure.
447 */
448 typedef struct
449 {
450 __IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
451 __IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
452 __IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
453 uint32_t RSERVED0[1015U];
454 __IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
455 __IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
456 __IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
457 } CACHE_Type;
458
459 /* CACHE Register Definitions */
460 #define CACHE_CER_EN_Pos 0U /*!< CACHE CER: EN Position */
461 #define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /*!< CACHE CER: EN Mask */
462
463 #define CACHE_CER_CFIG_Pos 1U /*!< CACHE CER: CFIG Position */
464 #define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /*!< CACHE CER: CFIG Mask */
465
466 #define CACHE_CER_WB_Pos 2U /*!< CACHE CER: WB Position */
467 #define CACHE_CER_WB_Msk (0x1UL << CACHE_CER_WB_Pos) /*!< CACHE CER: WB Mask */
468
469 #define CACHE_CER_DCW_Pos 4U /*!< CACHE CER: DCW Position */
470 #define CACHE_CER_DCW_Msk (0x1UL << CACHE_CER_DCW_Pos) /*!< CACHE CER: DCW Mask */
471
472 #define CACHE_CER_WA_Pos 5U /*!< CACHE CER: WA Position */
473 #define CACHE_CER_WA_Msk (0x1UL << CACHE_CER_WA_Pos) /*!< CACHE CER: WA Mask */
474
475 #define CACHE_CIR_INV_ALL_Pos 0U /*!< CACHE CIR: INV_ALL Position */
476 #define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /*!< CACHE CIR: INV_ALL Mask */
477
478 #define CACHE_CIR_INV_ONE_Pos 1U /*!< CACHE CIR: INV_ONE Position */
479 #define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /*!< CACHE CIR: INV_ONE Mask */
480
481 #define CACHE_CIR_CLR_ALL_Pos 2U /*!< CACHE CIR: CLR_ALL Position */
482 #define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /*!< CACHE CIR: CLR_ALL Mask */
483
484 #define CACHE_CIR_CLR_ONE_Pos 3U /*!< CACHE CIR: CLR_ONE Position */
485 #define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /*!< CACHE CIR: CLR_ONE Mask */
486
487 #define CACHE_CIR_INV_ADDR_Pos 4U /*!< CACHE CIR: INV_ADDR Position */
488 #define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos) /*!< CACHE CIR: INV_ADDR Mask */
489
490 #define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
491 #define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
492
493 #define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
494 #define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
495
496 #define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
497 #define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
498
499 #define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
500 #define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
501
502 #define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
503 #define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
504
505 #define CACHE_CRCR_4K 0xB /* 01011 */
506 #define CACHE_CRCR_8K 0xC /* 01100 */
507 #define CACHE_CRCR_16K 0xD /* 01101 */
508 #define CACHE_CRCR_32K 0xE /* 01110 */
509 #define CACHE_CRCR_64K 0xF /* 01111 */
510 #define CACHE_CRCR_128K 0x10 /* 10000 */
511 #define CACHE_CRCR_256K 0x11 /* 10001 */
512 #define CACHE_CRCR_512K 0x12 /* 10010 */
513 #define CACHE_CRCR_1M 0x13 /* 10011 */
514 #define CACHE_CRCR_2M 0x14 /* 10100 */
515 #define CACHE_CRCR_4M 0x15 /* 10101 */
516 #define CACHE_CRCR_8M 0x16 /* 10110 */
517 #define CACHE_CRCR_16M 0x17 /* 10111 */
518 #define CACHE_CRCR_32M 0x18 /* 11000 */
519 #define CACHE_CRCR_64M 0x19 /* 11001 */
520 #define CACHE_CRCR_128M 0x1A /* 11010 */
521 #define CACHE_CRCR_256M 0x1B /* 11011 */
522 #define CACHE_CRCR_512M 0x1C /* 11100 */
523 #define CACHE_CRCR_1G 0x1D /* 11101 */
524 #define CACHE_CRCR_2G 0x1E /* 11110 */
525 #define CACHE_CRCR_4G 0x1F /* 11111 */
526
527 /*@} end of group CSI_CACHE */
528
529
530 /**
531 \ingroup CSI_core_register
532 \defgroup CSI_SysTick System Tick Timer (CORET)
533 \brief Type definitions for the System Timer Registers.
534 @{
535 */
536
537 /**
538 \brief The data structure of the access system timer.
539 */
540 typedef struct {
541 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
542 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
543 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
544 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
545 } CORET_Type;
546
547 /* CORET Control / Status Register Definitions */
548 #define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
549 #define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
550
551 #define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
552 #define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
553
554 #define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
555 #define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
556
557 #define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
558 #define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
559
560 /* CORET Reload Register Definitions */
561 #define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
562 #define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
563
564 /* CORET Current Register Definitions */
565 #define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
566 #define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
567
568 /* CORET Calibration Register Definitions */
569 #define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
570 #define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
571
572 #define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
573 #define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
574
575 #define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
576 #define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
577
578 /*@} end of group CSI_SysTick */
579
580 /**
581 \ingroup CSI_core_register
582 \defgroup CSI_DCC
583 \brief Type definitions for the DCC.
584 @{
585 */
586
587 /**
588 \brief Access to the data structure of DCC.
589 */
590 typedef struct {
591 uint32_t RESERVED0[13U];
592 __IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
593 uint32_t RESERVED1;
594 __IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
595 uint32_t RESERVED2[6U];
596 union {
597 __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
598 __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
599 };
600
601 } DCC_Type;
602
603 #define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
604 #define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
605
606 #define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
607 #define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
608
609 #define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
610 #define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
611
612 #define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
613 #define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
614
615 /*@} end of group CSI_DCC */
616
617 /**
618 \ingroup CSI_core_register
619 \defgroup CSI_core_bitfield Core register bit field macros
620 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
621 @{
622 */
623
624 /**
625 \brief Mask and shift a bit field value for use in a register bit range.
626 \param[in] field Name of the register bit field.
627 \param[in] value Value of the bit field.
628 \return Masked and shifted value.
629 */
630 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
631
632 /**
633 \brief Mask and shift a register value to extract a bit filed value.
634 \param[in] field Name of the register bit field.
635 \param[in] value Value of register.
636 \return Masked and shifted bit field value.
637 */
638 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
639
640 /*@} end of group CSI_core_bitfield */
641
642 /**
643 \ingroup CSI_core_register
644 \defgroup CSI_core_base Core Definitions
645 \brief Definitions for base addresses, unions, and structures.
646 @{
647 */
648
649 /* Memory mapping of CK804 Hardware */
650 #define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
651 #define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
652 #define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
653 #define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
654 #define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
655
656 #define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
657 #define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
658 #define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
659 #define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
660
661 /*@} */
662
663
664 /*******************************************************************************
665 * Hardware Abstraction Layer
666 Core Function Interface contains:
667 - Core VIC Functions
668 - Core CORET Functions
669 - Core Register Access Functions
670 ******************************************************************************/
671 /**
672 \defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
673 */
674
675 /* ########################## VIC functions #################################### */
676 /**
677 \ingroup CSI_Core_FunctionInterface
678 \defgroup CSI_Core_VICFunctions VIC Functions
679 \brief Functions that manage interrupts and exceptions via the VIC.
680 @{
681 */
682
683 /* The following MACROS handle generation of the register offset and byte masks */
684 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
685 #define _IR_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
686 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
687
688 /**
689 \brief Enable External Interrupt
690 \details Enable a device-specific interrupt in the VIC interrupt controller.
691 \param [in] IRQn External interrupt number. Value cannot be negative.
692 */
csi_vic_enable_irq(int32_t IRQn)693 __STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
694 {
695 IRQn &= 0x7FUL;
696
697 VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
698 }
699
700 /**
701 \brief Disable External Interrupt
702 \details Disable a device-specific interrupt in the VIC interrupt controller.
703 \param [in] IRQn External interrupt number. Value cannot be negative.
704 */
csi_vic_disable_irq(int32_t IRQn)705 __STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
706 {
707 IRQn &= 0x7FUL;
708
709 VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
710 }
711
712 /**
713 \brief Enable External Secure Interrupt
714 \details Enable a secure device-specific interrupt in the VIC interrupt controller.
715 \param [in] IRQn External interrupt number. Value cannot be negative.
716 */
csi_vic_enable_sirq(int32_t IRQn)717 __STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
718 {
719 IRQn &= 0x7FUL;
720
721 VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
722 VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
723 }
724
725 /**
726 \brief Disable External Secure Interrupt
727 \details Disable a secure device-specific interrupt in the VIC interrupt controller.
728 \param [in] IRQn External interrupt number. Value cannot be negative.
729 */
csi_vic_disable_sirq(int32_t IRQn)730 __STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
731 {
732 IRQn &= 0x7FUL;
733
734 VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
735 VIC->ICSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
736 }
737
738 /**
739 \brief Check Interrupt is Enabled or not
740 \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
741 \param [in] IRQn Interrupt number.
742 \return 0 Interrupt status is not enabled.
743 \return 1 Interrupt status is enabled.
744 */
csi_vic_get_enabled_irq(int32_t IRQn)745 __STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
746 {
747 IRQn &= 0x7FUL;
748
749 return ((uint32_t)(((VIC->ISER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
750 }
751
752 /**
753 \brief Check Interrupt is Pending or not
754 \details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
755 \param [in] IRQn Interrupt number.
756 \return 0 Interrupt status is not pending.
757 \return 1 Interrupt status is pending.
758 */
csi_vic_get_pending_irq(int32_t IRQn)759 __STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
760 {
761 IRQn &= 0x7FUL;
762
763 return ((uint32_t)(((VIC->ISPR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
764 }
765
766 /**
767 \brief Set Pending Interrupt
768 \details Set the pending bit of an external interrupt.
769 \param [in] IRQn Interrupt number. Value cannot be negative.
770 */
csi_vic_set_pending_irq(int32_t IRQn)771 __STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
772 {
773 IRQn &= 0x7FUL;
774
775 VIC->ISPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
776 }
777
778 /**
779 \brief Clear Pending Interrupt
780 \details Clear the pending bit of an external interrupt.
781 \param [in] IRQn External interrupt number. Value cannot be negative.
782 */
csi_vic_clear_pending_irq(int32_t IRQn)783 __STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
784 {
785 IRQn &= 0x7FUL;
786
787 VIC->ICPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
788 }
789
790 /**
791 \brief Check Interrupt is Wakeup or not
792 \details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
793 \param [in] IRQn Interrupt number.
794 \return 0 Interrupt is not set as wake up interrupt.
795 \return 1 Interrupt is set as wake up interrupt.
796 */
csi_vic_get_wakeup_irq(int32_t IRQn)797 __STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
798 {
799 IRQn &= 0x7FUL;
800
801 return ((uint32_t)(((VIC->IWER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
802 }
803
804 /**
805 \brief Set Wake up Interrupt
806 \details Set the wake up bit of an external interrupt.
807 \param [in] IRQn Interrupt number. Value cannot be negative.
808 */
csi_vic_set_wakeup_irq(int32_t IRQn)809 __STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
810 {
811 IRQn &= 0x7FUL;
812
813 VIC->IWER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
814 }
815
816 /**
817 \brief Clear Wake up Interrupt
818 \details Clear the wake up bit of an external interrupt.
819 \param [in] IRQn External interrupt number. Value cannot be negative.
820 */
csi_vic_clear_wakeup_irq(int32_t IRQn)821 __STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
822 {
823 IRQn &= 0x7FUL;
824
825 VIC->IWDR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
826 }
827
828 /**
829 \brief Get Interrupt is Active or not
830 \details Read the active register in the VIC and returns the active bit for the device specific interrupt.
831 \param [in] IRQn Device specific interrupt number.
832 \return 0 Interrupt status is not active.
833 \return 1 Interrupt status is active.
834 \note IRQn must not be negative.
835 */
csi_vic_get_active(int32_t IRQn)836 __STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
837 {
838 IRQn &= 0x7FUL;
839
840 return ((uint32_t)(((VIC->IABR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
841 }
842
843 /**
844 \brief Set Threshold register
845 \details set the threshold register in the VIC.
846 \param [in] VectThreshold specific vector threshold.
847 \param [in] PrioThreshold specific priority threshold.
848 */
csi_vic_set_threshold(uint32_t VectThreshold,uint32_t PrioThreshold)849 __STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
850 {
851 PrioThreshold &= 0xFFU;
852
853 VIC->IPTR = 0x80000000U | ((VectThreshold & 0xFFU) << 8U) | ((PrioThreshold << (8U - __VIC_PRIO_BITS)) & 0xFFU);
854 }
855
856 /**
857 \brief Set Interrupt Priority
858 \details Set the priority of an interrupt.
859 \note The priority cannot be set for every core interrupt.
860 \param [in] IRQn Interrupt number.
861 \param [in] priority Priority to set.
862 */
csi_vic_set_prio(int32_t IRQn,uint32_t priority)863 __STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
864 {
865 VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
866 (((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
867 }
868
869 /**
870 \brief Get Interrupt Priority
871 \details Read the priority of an interrupt.
872 The interrupt number can be positive to specify an external (device specific) interrupt,
873 or negative to specify an internal (core) interrupt.
874 \param [in] IRQn Interrupt number.
875 \return Interrupt Priority.
876 Value is aligned automatically to the implemented priority bits of the microcontroller.
877 */
csi_vic_get_prio(int32_t IRQn)878 __STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
879 {
880 return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
881 }
882
883 /**
884 \brief Set interrupt handler
885 \details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
886 \param [in] IRQn Interrupt number.
887 \param [in] handler Interrupt handler.
888 */
csi_vic_set_vector(int32_t IRQn,uint32_t handler)889 __STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
890 {
891 if (IRQn >= 0 && IRQn < 128) {
892 uint32_t *vectors = (uint32_t *)__get_VBR();
893 vectors[32 + IRQn] = handler;
894 }
895 }
896
897 /**
898 \brief Get interrupt handler
899 \details Get the address of interrupt handler function.
900 \param [in] IRQn Interrupt number.
901 */
csi_vic_get_vector(int32_t IRQn)902 __STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
903 {
904 if (IRQn >= 0 && IRQn < 128) {
905 uint32_t *vectors = (uint32_t *)__get_VBR();
906 return (uint32_t)vectors[32 + IRQn];
907 }
908
909 return 0;
910 }
911
912 /*@} end of CSI_Core_VICFunctions */
913
914 /* ################################## SysTick function ############################################ */
915 /**
916 \ingroup CSI_Core_FunctionInterface
917 \defgroup CSI_Core_SysTickFunctions SysTick Functions
918 \brief Functions that configure the System.
919 @{
920 */
921
922
923 /**
924 \brief CORE timer Configuration
925 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
926 Counter is in free running mode to generate periodic interrupts.
927 \param [in] ticks Number of ticks between two interrupts.
928 \param [in] IRQn core timer Interrupt number.
929 \return 0 Function succeeded.
930 \return 1 Function failed.
931 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
932 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
933 must contain a vendor-specific implementation of this function.
934 */
csi_coret_config(uint32_t ticks,int32_t IRQn)935 __STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
936 {
937 if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
938 return (1UL); /* Reload value impossible */
939 }
940
941 CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
942 CORET->VAL = 0UL; /* Load the CORET Counter Value */
943 CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
944 CORET_CTRL_TICKINT_Msk |
945 CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
946 return (0UL); /* Function successful */
947 }
948
949 /**
950 \brief get CORE timer reload value
951 \return CORE timer counter value.
952 */
csi_coret_get_load(void)953 __STATIC_INLINE uint32_t csi_coret_get_load(void)
954 {
955 return CORET->LOAD;
956 }
957
958 /**
959 \brief get CORE timer counter value
960 \return CORE timer counter value.
961 */
csi_coret_get_value(void)962 __STATIC_INLINE uint32_t csi_coret_get_value(void)
963 {
964 return CORET->VAL;
965 }
966
967 /*@} end of CSI_Core_SysTickFunctions */
968
969 /* ##################################### DCC function ########################################### */
970 /**
971 \ingroup CSI_Core_FunctionInterface
972 \defgroup CSI_core_DebugFunctions HAD Functions
973 \brief Functions that access the HAD debug interface.
974 @{
975 */
976
977 /**
978 \brief HAD Send Character
979 \details Transmits a character via the HAD channel 0, and
980 \li Just returns when no debugger is connected that has booked the output.
981 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
982 \param [in] ch Character to transmit.
983 \returns Character to transmit.
984 */
csi_had_send_char(uint32_t ch)985 __STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
986 {
987 DCC->DERJR = (uint8_t)ch;
988
989 return (ch);
990 }
991
992
993 /**
994 \brief HAD Receive Character
995 \details Inputs a character via the external variable \ref HAD_RxBuffer.
996 \return Received character.
997 \return -1 No character pending.
998 */
csi_had_receive_char(void)999 __STATIC_INLINE int32_t csi_had_receive_char(void)
1000 {
1001 int32_t ch = -1; /* no character available */
1002
1003 if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
1004 ch = DCC->DERJW;
1005 }
1006
1007 return (ch);
1008 }
1009
1010
1011 /**
1012 \brief HAD Check Character
1013 \details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
1014 \return 0 No character available.
1015 \return 1 Character available.
1016 */
csi_had_check_char(void)1017 __STATIC_INLINE int32_t csi_had_check_char(void)
1018 {
1019 return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
1020 }
1021
1022 /*@} end of CSI_core_DebugFunctions */
1023
1024 /* ########################## Cache functions #################################### */
1025 /**
1026 \ingroup CSI_Core_FunctionInterface
1027 \defgroup CSI_Core_CacheFunctions Cache Functions
1028 \brief Functions that configure Instruction and Data cache.
1029 @{
1030 */
1031
1032 /**
1033 \brief Enable I-Cache
1034 \details Turns on I-Cache
1035 */
csi_icache_enable(void)1036 __STATIC_INLINE void csi_icache_enable (void)
1037 {
1038 #if (__ICACHE_PRESENT == 1U)
1039 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1040 CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
1041 #endif
1042 }
1043
1044
1045 /**
1046 \brief Disable I-Cache
1047 \details Turns off I-Cache
1048 */
csi_icache_disable(void)1049 __STATIC_INLINE void csi_icache_disable (void)
1050 {
1051 #if (__ICACHE_PRESENT == 1U)
1052 CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
1053 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1054 #endif
1055 }
1056
1057
1058 /**
1059 \brief Invalidate I-Cache
1060 \details Invalidates I-Cache
1061 */
csi_icache_invalid(void)1062 __STATIC_INLINE void csi_icache_invalid (void)
1063 {
1064 #if (__ICACHE_PRESENT == 1U)
1065 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1066 #endif
1067 }
1068
1069
1070 /**
1071 \brief Enable D-Cache
1072 \details Turns on D-Cache
1073 \note I-Cache also turns on.
1074 */
csi_dcache_enable(void)1075 __STATIC_INLINE void csi_dcache_enable (void)
1076 {
1077 #if (__DCACHE_PRESENT == 1U)
1078 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1079 CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_WB_Msk | CACHE_CER_DCW_Msk) & (~CACHE_CER_CFIG_Msk); /* enable all Cache */
1080 #endif
1081 }
1082
1083
1084 /**
1085 \brief Disable D-Cache
1086 \details Turns off D-Cache
1087 \note I-Cache also turns off.
1088 */
csi_dcache_disable(void)1089 __STATIC_INLINE void csi_dcache_disable (void)
1090 {
1091 #if (__DCACHE_PRESENT == 1U)
1092 CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
1093 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1094 #endif
1095 }
1096
1097
1098 /**
1099 \brief Invalidate D-Cache
1100 \details Invalidates D-Cache
1101 \note I-Cache also invalid
1102 */
csi_dcache_invalid(void)1103 __STATIC_INLINE void csi_dcache_invalid (void)
1104 {
1105 #if (__DCACHE_PRESENT == 1U)
1106 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1107 #endif
1108 }
1109
1110
1111 /**
1112 \brief Clean D-Cache
1113 \details Cleans D-Cache
1114 \note I-Cache also cleans
1115 */
csi_dcache_clean(void)1116 __STATIC_INLINE void csi_dcache_clean (void)
1117 {
1118 #if (__DCACHE_PRESENT == 1U)
1119 CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
1120 #endif
1121 }
1122
1123
1124 /**
1125 \brief Clean & Invalidate D-Cache
1126 \details Cleans and Invalidates D-Cache
1127 \note I-Cache also flush.
1128 */
csi_dcache_clean_invalid(void)1129 __STATIC_INLINE void csi_dcache_clean_invalid (void)
1130 {
1131 #if (__DCACHE_PRESENT == 1U)
1132 CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
1133 #endif
1134 }
1135
1136
1137 /**
1138 \brief D-Cache Invalidate by address
1139 \details Invalidates D-Cache for the given address
1140 \param[in] addr address (aligned to 16-byte boundary)
1141 \param[in] dsize size of memory block (aligned to 16-byte boundary)
1142 */
1143
csi_dcache_invalid_range(uint32_t * addr,int32_t dsize)1144 __STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
1145 {
1146 #if (__DCACHE_PRESENT == 1U)
1147 int32_t op_size = dsize + (uint32_t)addr % 16;
1148 uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
1149 int32_t linesize = 16;
1150
1151 op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
1152
1153 while (op_size >= 128) {
1154 CACHE->CIR = op_addr;
1155 op_addr += linesize;
1156 CACHE->CIR = op_addr;
1157 op_addr += linesize;
1158 CACHE->CIR = op_addr;
1159 op_addr += linesize;
1160 CACHE->CIR = op_addr;
1161 op_addr += linesize;
1162 CACHE->CIR = op_addr;
1163 op_addr += linesize;
1164 CACHE->CIR = op_addr;
1165 op_addr += linesize;
1166 CACHE->CIR = op_addr;
1167 op_addr += linesize;
1168 CACHE->CIR = op_addr;
1169 op_addr += linesize;
1170
1171 op_size -= 128;
1172 }
1173
1174 while (op_size > 0) {
1175 CACHE->CIR = op_addr;
1176 op_addr += linesize;
1177 op_size -= linesize;
1178 }
1179 #endif
1180 }
1181
1182
1183 /**
1184 \brief D-Cache Clean by address
1185 \details Cleans D-Cache for the given address
1186 \param[in] addr address (aligned to 16-byte boundary)
1187 \param[in] dsize size of memory block (aligned to 16-byte boundary)
1188 */
csi_dcache_clean_range(uint32_t * addr,int32_t dsize)1189 __STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
1190 {
1191 #if (__DCACHE_PRESENT == 1)
1192 int32_t op_size = dsize + (uint32_t)addr % 16;
1193 uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
1194 int32_t linesize = 16;
1195
1196 op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
1197
1198 while (op_size >= 128) {
1199 CACHE->CIR = op_addr;
1200 op_addr += linesize;
1201 CACHE->CIR = op_addr;
1202 op_addr += linesize;
1203 CACHE->CIR = op_addr;
1204 op_addr += linesize;
1205 CACHE->CIR = op_addr;
1206 op_addr += linesize;
1207 CACHE->CIR = op_addr;
1208 op_addr += linesize;
1209 CACHE->CIR = op_addr;
1210 op_addr += linesize;
1211 CACHE->CIR = op_addr;
1212 op_addr += linesize;
1213 CACHE->CIR = op_addr;
1214 op_addr += linesize;
1215
1216 op_size -= 128;
1217 }
1218
1219 while (op_size > 0) {
1220 CACHE->CIR = op_addr;
1221 op_addr += linesize;
1222 op_size -= linesize;
1223 }
1224 #endif
1225 }
1226
1227
1228 /**
1229 \brief D-Cache Clean and Invalidate by address
1230 \details Cleans and invalidates D_Cache for the given address
1231 \param[in] addr address (aligned to 16-byte boundary)
1232 \param[in] dsize size of memory block (aligned to 16-byte boundary)
1233 */
csi_dcache_clean_invalid_range(uint32_t * addr,int32_t dsize)1234 __STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
1235 {
1236 #if (__DCACHE_PRESENT == 1U)
1237 int32_t op_size = dsize + (uint32_t)addr % 16;
1238 uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
1239 int32_t linesize = 16;
1240
1241 op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
1242
1243 while (op_size >= 128) {
1244 CACHE->CIR = op_addr;
1245 op_addr += linesize;
1246 CACHE->CIR = op_addr;
1247 op_addr += linesize;
1248 CACHE->CIR = op_addr;
1249 op_addr += linesize;
1250 CACHE->CIR = op_addr;
1251 op_addr += linesize;
1252 CACHE->CIR = op_addr;
1253 op_addr += linesize;
1254 CACHE->CIR = op_addr;
1255 op_addr += linesize;
1256 CACHE->CIR = op_addr;
1257 op_addr += linesize;
1258 CACHE->CIR = op_addr;
1259 op_addr += linesize;
1260
1261 op_size -= 128;
1262 }
1263
1264 while (op_size > 0) {
1265 CACHE->CIR = op_addr;
1266 op_addr += linesize;
1267 op_size -= linesize;
1268 }
1269 #endif
1270 }
1271
1272 /**
1273 \brief setup cacheable range Cache
1274 \details setup Cache range
1275 \param [in] index cache scope index (0, 1, 2, 3).
1276 \param [in] baseAddr base address must be aligned with size.
1277 \param [in] size \ref CACHE Register Definitions. cache scope size.
1278 \param [in] enable enable or disable cache scope.
1279 */
csi_cache_set_range(uint32_t index,uint32_t baseAddr,uint32_t size,uint32_t enable)1280 __STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
1281 {
1282 CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
1283 (_VAL2FLD(CACHE_CRCR_SIZE, size)) |
1284 (_VAL2FLD(CACHE_CRCR_EN, enable)));
1285 }
1286
1287 /**
1288 \brief Enable cache profile
1289 \details Turns on Cache profile
1290 */
csi_cache_enable_profile(void)1291 __STATIC_INLINE void csi_cache_enable_profile (void)
1292 {
1293 CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
1294 }
1295
1296 /**
1297 \brief Disable cache profile
1298 \details Turns off Cache profile
1299 */
csi_cache_disable_profile(void)1300 __STATIC_INLINE void csi_cache_disable_profile (void)
1301 {
1302 CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
1303 }
1304
1305 /**
1306 \brief Reset cache profile
1307 \details Reset Cache profile
1308 */
csi_cache_reset_profile(void)1309 __STATIC_INLINE void csi_cache_reset_profile (void)
1310 {
1311 CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
1312 }
1313
1314 /**
1315 \brief cache access times
1316 \details Cache access times
1317 \note every 256 access add 1.
1318 \return cache access times, actual times should be multiplied by 256
1319 */
csi_cache_get_access_time(void)1320 __STATIC_INLINE uint32_t csi_cache_get_access_time (void)
1321 {
1322 return CACHE->CPFATR;
1323 }
1324
1325 /**
1326 \brief cache miss times
1327 \details Cache miss times
1328 \note every 256 miss add 1.
1329 \return cache miss times, actual times should be multiplied by 256
1330 */
csi_cache_get_miss_time(void)1331 __STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
1332 {
1333 return CACHE->CPFMTR;
1334 }
1335
1336 /*@} end of CSI_Core_CacheFunctions */
1337
1338 /* ########################## MPU functions #################################### */
1339 /**
1340 \ingroup CSI_Core_FunctionInterface
1341 \defgroup CSI_Core_MPUFunctions MPU Functions
1342 \brief Functions that configure MPU.
1343 @{
1344 */
1345
1346 typedef enum {
1347 REGION_SIZE_4KB = 0xB,
1348 REGION_SIZE_8KB = 0xC,
1349 REGION_SIZE_16KB = 0xD,
1350 REGION_SIZE_32KB = 0xE,
1351 REGION_SIZE_64KB = 0xF,
1352 REGION_SIZE_128KB = 0x10,
1353 REGION_SIZE_256KB = 0x11,
1354 REGION_SIZE_512KB = 0x12,
1355 REGION_SIZE_1MB = 0x13,
1356 REGION_SIZE_2MB = 0x14,
1357 REGION_SIZE_4MB = 0x15,
1358 REGION_SIZE_8MB = 0x16,
1359 REGION_SIZE_16MB = 0x17,
1360 REGION_SIZE_32MB = 0x18,
1361 REGION_SIZE_64MB = 0x19,
1362 REGION_SIZE_128MB = 0x1A,
1363 REGION_SIZE_256MB = 0x1B,
1364 REGION_SIZE_512MB = 0x1C,
1365 REGION_SIZE_1GB = 0x1D,
1366 REGION_SIZE_2GB = 0x1E,
1367 REGION_SIZE_4GB = 0x1F
1368 } region_size_e;
1369
1370 typedef enum {
1371 AP_BOTH_INACCESSIBLE = 0,
1372 AP_SUPER_RW_USER_INACCESSIBLE,
1373 AP_SUPER_RW_USER_RDONLY,
1374 AP_BOTH_RW
1375 } access_permission_e;
1376
1377 typedef struct {
1378 uint32_t nx: 1; /* instruction fetched excution */
1379 access_permission_e ap: 2; /* super user and normal user access.*/
1380 uint32_t s: 1; /* security */
1381 } mpu_region_attr_t;
1382
1383 /**
1384 \brief enable mpu.
1385 \details
1386 */
csi_mpu_enable(void)1387 __STATIC_INLINE void csi_mpu_enable(void)
1388 {
1389 __set_CCR(__get_CCR() | CCR_MP_Msk);
1390 }
1391
1392 /**
1393 \brief disable mpu.
1394 \details
1395 */
csi_mpu_disable(void)1396 __STATIC_INLINE void csi_mpu_disable(void)
1397 {
1398 __set_CCR(__get_CCR() & (~CCR_MP_Msk));
1399 }
1400
1401 /**
1402 \brief configure memory protected region.
1403 \details
1404 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1405 \param [in] base_addr base address must be aligned with page size.
1406 \param [in] size \ref region_size_e. memory protected region size.
1407 \param [in] attr \ref region_size_t. memory protected region attribute.
1408 \param [in] enable enable or disable memory protected region.
1409 */
csi_mpu_config_region(uint32_t idx,uint32_t base_addr,region_size_e size,mpu_region_attr_t attr,uint32_t enable)1410 __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
1411 mpu_region_attr_t attr, uint32_t enable)
1412 {
1413 if (idx > 7) {
1414 return;
1415 }
1416
1417 CAPR_Type capr;
1418 PACR_Type pacr;
1419 PRSR_Type prsr;
1420
1421 capr.w = __get_CAPR();
1422 pacr.w = __get_PACR();
1423 prsr.w = __get_PRSR();
1424
1425 pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
1426
1427 prsr.b.RID = idx;
1428 __set_PRSR(prsr.w);
1429
1430 if (size != REGION_SIZE_4KB) {
1431 pacr.w &= ~(((1u << (size -11)) - 1) << 12);
1432 }
1433
1434 pacr.b.size = size;
1435
1436 capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
1437 capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
1438 __set_CAPR(capr.w);
1439
1440 pacr.b.E = enable;
1441 __set_PACR(pacr.w);
1442 }
1443
1444 /**
1445 \brief enable mpu region by idx.
1446 \details
1447 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1448 */
csi_mpu_enable_region(uint32_t idx)1449 __STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
1450 {
1451 if (idx > 7) {
1452 return;
1453 }
1454
1455 __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
1456 __set_PACR(__get_PACR() | PACR_E_Msk);
1457 }
1458
1459 /**
1460 \brief disable mpu region by idx.
1461 \details
1462 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1463 */
csi_mpu_disable_region(uint32_t idx)1464 __STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
1465 {
1466 if (idx > 7) {
1467 return;
1468 }
1469
1470 __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
1471 __set_PACR(__get_PACR() & (~PACR_E_Msk));
1472 }
1473
1474 /*@} end of CSI_Core_MMUFunctions */
1475
1476
1477 /* ################################## IRQ Functions ############################################ */
1478
1479 /**
1480 \brief Save the Irq context
1481 \details save the psr result before disable irq.
1482 \param [in] irq_num External interrupt number. Value cannot be negative.
1483 */
csi_irq_save(void)1484 __STATIC_INLINE uint32_t csi_irq_save(void)
1485 {
1486 uint32_t result;
1487 result = __get_PSR();
1488 __disable_irq();
1489 return(result);
1490 }
1491
1492 /**
1493 \brief Restore the Irq context
1494 \details restore saved primask state.
1495 \param [in] irq_state psr irq state.
1496 */
csi_irq_restore(uint32_t irq_state)1497 __STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
1498 {
1499 __set_PSR(irq_state);
1500 }
1501
1502 /*@} end of IRQ Functions */
1503
1504 /**
1505 \brief System Reset
1506 \details Initiates a system reset request to reset the MCU.
1507 */
csi_system_reset(void)1508 __STATIC_INLINE void csi_system_reset(void)
1509 {
1510 CHR_Type chr;
1511
1512 chr.w = __get_CHR();
1513 #ifdef __RESET_CONST
1514 chr.b.SRST_VAL = __RESET_CONST;
1515 #else
1516 chr.b.SRST_VAL = 0xABCD;
1517 #endif
1518
1519 __DSB(); /* Ensure all outstanding memory accesses included
1520 buffered write are completed before reset */
1521 __set_CHR(chr.w);
1522
1523 __DSB(); /* Ensure completion of memory access */
1524
1525 for(;;) /* wait until reset */
1526 {
1527 __NOP();
1528 }
1529 }
1530
1531 /* ################################## Old Interfaces ############################################ */
1532
1533 /* These interfaces are deprecated */
1534 #define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
1535 #define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
1536 #define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
1537 #define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
1538 #define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
1539 #define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
1540 #define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
1541 #define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
1542 #define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
1543 #define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
1544 #define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
1545 #define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
1546 #define NVIC_SystemReset() csi_system_reset()
1547
1548 #define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
1549 #define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
1550
1551 #define SCB_EnableICache() csi_icache_enable()
1552 #define SCB_DisableICache() csi_icache_disable()
1553 #define SCB_InvalidateICache() csi_icache_invalid()
1554 #define SCB_EnableDCache() csi_dcache_enable()
1555 #define SCB_DisableDCache() csi_dcache_disable()
1556 #define SCB_InvalidateDCache() csi_dcache_invalid()
1557 #define SCB_CleanDCache() csi_dcache_clean()
1558 #define SCB_CleanInvalidateDCache() csi_dcache_clean_invalid()
1559 #define SCB_InvalidateDCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize)
1560 #define SCB_CleanDCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
1561 #define SCB_CleanInvalidateDCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
1562 #define SCB_Cacheable_Range(index, baseAddr, size, enable) csi_cache_set_range(index, baseAddr, size, enable)
1563 #define SCB_EnableCacheProfile() csi_cache_enable_profile()
1564 #define SCB_DisableCacheProfile() csi_cache_disable_profile()
1565 #define SCB_ResetCacheProfile() csi_cache_reset_profile()
1566 #define SCB_CacheAccessTime() csi_cache_get_access_time()
1567 #define SCB_CacheMissTime() csi_cache_get_miss_time()
1568 #define SCB_EnableCache() csi_icache_enable();csi_dcache_enable()
1569 #define SCB_DisableCache() csi_icache_disable();csi_dcache_disable()
1570 #define SCB_InvalidateCache() csi_icache_invalid();csi_dcache_invalid()
1571 #define SCB_CleanCache() csi_dcache_clean()
1572 #define SCB_CleanInvalidateCache() csi_icache_invalid();csi_dcache_clean();csi_dcache_invalid()
1573 #define SCB_InvalidateCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize);csi_icache_invalid()
1574 #define SCB_CleanCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
1575 #define SCB_CleanInvalidateCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
1576
1577 #ifdef __cplusplus
1578 }
1579 #endif
1580
1581 #endif /* __CORE_804_H_DEPENDANT */
1582
1583 #endif /* __CSI_GENERIC */
1584