1 /*
2 * Copyright (C) 2017-2019 Alibaba Group Holding Limited
3 */
4
5
6 /******************************************************************************
7 * @file core_ck610.h
8 * @brief CSI CK610 Core Peripheral Access Layer Header File
9 * @version V1.0
10 * @date 02. June 2017
11 ******************************************************************************/
12
13 #ifndef __CORE_CK610_H_GENERIC
14 #define __CORE_CK610_H_GENERIC
15
16 #include <stdint.h>
17 #include <stdio.h>
18
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22
23 /*******************************************************************************
24 * CSI definitions
25 ******************************************************************************/
26 /**
27 \ingroup Ck610
28 @{
29 */
30
31 /* CSI CK610 definitions */
32 #define __CK610_CSI_VERSION_MAIN (0x01U) /*!< [31:16] CSI HAL main version */
33 #define __CK610_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
34 #define __CK610_CSI_VERSION ((__CK610_CSI_VERSION_MAIN << 16U) | \
35 __CK610_CSI_VERSION_SUB ) /*!< CSI HAL version number */
36
37 #define __CK610 (0x01U) /*!< CK610 Core */
38
39 /** __FPU_USED indicates whether an FPU is used or not.
40 This core does not support an FPU at all
41 */
42 #define __FPU_USED 1U
43
44 #if defined ( __GNUC__ )
45 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
46 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
47 #endif
48 #endif
49
50 #ifdef __cplusplus
51 }
52 #endif
53
54 #endif /* __CORE_CK610_H_GENERIC */
55
56 #ifndef __CSI_GENERIC
57
58 #ifndef __CORE_CK610_H_DEPENDANT
59 #define __CORE_CK610_H_DEPENDANT
60
61 #ifdef __cplusplus
62 extern "C" {
63 #endif
64
65 /* check device defines and use defaults */
66 #ifndef __CK610_REV
67 #define __CK610_REV 0x0000U
68 #endif
69
70 #ifndef __GSR_GCR_PRESENT
71 #define __GSR_GCR_PRESENT 0U
72 #endif
73
74 #ifndef __MPU_PRESENT
75 #define __MPU_PRESENT 0U
76 #endif
77
78 #ifndef __ICACHE_PRESENT
79 #define __ICACHE_PRESENT 1U
80 #endif
81
82 #ifndef __DCACHE_PRESENT
83 #define __DCACHE_PRESENT 1U
84 #endif
85
86 #include <core/csi_gcc.h>
87
88 /* IO definitions (access restrictions to peripheral registers) */
89 /**
90 \defgroup CSI_glob_defs CSI Global Defines
91
92 <strong>IO Type Qualifiers</strong> are used
93 \li to specify the access to peripheral variables.
94 \li for automatic generation of peripheral register debug information.
95 */
96 #ifdef __cplusplus
97 #define __I volatile /*!< Defines 'read only' permissions */
98 #else
99 #define __I volatile const /*!< Defines 'read only' permissions */
100 #endif
101 #define __O volatile /*!< Defines 'write only' permissions */
102 #define __IO volatile /*!< Defines 'read / write' permissions */
103
104 /* following defines should be used for structure members */
105 #define __IM volatile const /*! Defines 'read only' structure member permissions */
106 #define __OM volatile /*! Defines 'write only' structure member permissions */
107 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
108
109 /*@} end of group CK610 */
110
111 /*******************************************************************************
112 * Register Abstraction
113 Core Register contain:
114 - Core Register
115 - Core MGU Register
116 - Core MMU Register
117 ******************************************************************************/
118 /**
119 \defgroup CSI_core_register Defines and Type Definitions
120 \brief Type definitions and defines for CK610 processor based devices.
121 */
122
123 /**
124 \brief Access Processor Status Register(PSR)struct definition.
125 */
126 typedef union {
127 struct {
128 uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
129 uint32_t AF: 1; /*!< bit: 1 Alternate register valid control bit */
130 uint32_t _reserved0: 2; /*!< bit: 2.. 3 Reserved */
131 uint32_t FE: 1; /*!< bit: 4 Fast interrupt enable control bit */
132 uint32_t _reserved1: 1; /*!< bit: 5 Reserved */
133 uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
134 uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
135 uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
136 uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
137 uint32_t _reserved2: 2; /*!< bit: 10..11 Reserved */
138 uint32_t TE: 1; /*!< bit: 12 Trace transmission control bit */
139 uint32_t TP: 1; /*!< bit: 13 Pending trace exception set bit */
140 uint32_t TM: 2; /*!< bit: 14..15 Tracing mode bit */
141 uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
142 uint32_t CPID: 4; /*!< bit: 24..27 Number of processor currently running */
143 uint32_t _reserved3: 3; /*!< bit: 28..30 Reserved */
144 uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
145 } b; /*!< Structure Access by bit */
146 uint32_t w; /*!< Type Access by whole register */
147 } PSR_Type;
148
149 /* PSR Register Definitions */
150 #define PSR_S_Pos 31U /*!< PSR: S Position */
151 #define PSR_S_Msk (0x1UL << PSR_S_Pos) /*!< PSR: S Mask */
152
153 #define PSR_CPID_Pos 24U /*!< PSR: CPID Position */
154 #define PSR_CPID_Msk (0xFUL << PSR_CPID_Pos) /*!< PSR: CPID Mask */
155
156 #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
157 #define PSR_VEC_Msk (0xFFUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
158
159 #define PSR_TM_Pos 14U /*!< PSR: TM Position */
160 #define PSR_TM_Msk (0x3UL << PSR_TM_Pos) /*!< PSR: TM Mask */
161
162 #define PSR_TP_Pos 13U /*!< PSR: TP Position */
163 #define PSR_TP_Msk (0x1UL << PSR_TM_Pos) /*!< PSR: TP Mask */
164
165 #define PSR_TE_Pos 12U /*!< PSR: TE Position */
166 #define PSR_TE_Msk (0x1UL << PSR_TE_Pos) /*!< PSR: TE Mask */
167
168 #define PSR_MM_Pos 9U /*!< PSR: MM Position */
169 #define PSR_MM_Msk (0x1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
170
171 #define PSR_EE_Pos 8U /*!< PSR: EE Position */
172 #define PSR_EE_Msk (0x1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
173
174 #define PSR_IC_Pos 7U /*!< PSR: IC Position */
175 #define PSR_IC_Msk (0x1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
176
177 #define PSR_IE_Pos 6U /*!< PSR: IE Position */
178 #define PSR_IE_Msk (0x1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
179
180 #define PSR_FE_Pos 4U /*!< PSR: FE Position */
181 #define PSR_FE_Msk (0x1UL << PSR_FE_Pos) /*!< PSR: FE Mask */
182
183 #define PSR_AF_Pos 1U /*!< PSR: AF Position */
184 #define PSR_AF_Msk (0x1UL << PSR_AF_Pos) /*!< PSR: AF Mask */
185
186 #define PSR_C_Pos 0U /*!< PSR: C Position */
187 #define PSR_C_Msk (0x1UL << PSR_C_Pos) /*!< PSR: C Mask */
188
189 /**
190 \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
191 */
192 typedef union {
193 struct {
194 uint32_t MP: 2; /*!< bit: 0..1 Memory protection settings */
195 uint32_t IE: 1; /*!< bit: 2 Endian mode */
196 uint32_t DE: 1; /*!< bit: 3 Endian mode */
197 uint32_t WB: 1; /*!< bit: 4 Endian mode */
198 uint32_t RS: 1; /*!< bit: 5 Endian mode */
199 uint32_t Z: 1; /*!< bit: 6 Endian mode */
200 uint32_t BE: 1; /*!< bit: 7 Endian mode */
201 uint32_t SCK: 3; /*!< bit: 8..10 The clock ratio of the system and the processor */
202 uint32_t _reserved0: 21; /*!< bit: 11..31 Reserved */
203 } b; /*!< Structure Access by bit */
204 uint32_t w; /*!< Type Access by whole register */
205 } CCR_Type;
206
207 /* CCR Register Definitions */
208 #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
209 #define CCR_SCK_Msk (0x7UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
210
211 #define CCR_BE_Pos 7U /*!< CCR: BE Position */
212 #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
213
214 #define CCR_Z_Pos 6U /*!< CCR: Z Position */
215 #define CCR_Z_Msk (0x1UL << CCR_Z_Pos) /*!< CCR: Z Mask */
216
217 #define CCR_RS_Pos 5U /*!< CCR: RS Position */
218 #define CCR_RS_Msk (0x1UL << CCR_RS_Pos) /*!< CCR: RS Mask */
219
220 #define CCR_WB_Pos 4U /*!< CCR: WB Position */
221 #define CCR_WB_Msk (0x1UL << CCR_WB_Pos) /*!< CCR: WB Mask */
222
223 #define CCR_DE_Pos 3U /*!< CCR: DE Position */
224 #define CCR_DE_Msk (0x1UL << CCR_DE_Pos) /*!< CCR: DE Mask */
225
226 #define CCR_IE_Pos 2U /*!< CCR: IE Position */
227 #define CCR_IE_Msk (0x1UL << CCR_IE_Pos) /*!< CCR: IE Mask */
228
229 #define CCR_MP_Pos 0U /*!< CCR: MP Position */
230 #define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
231
232
233 /**
234 \brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
235 */
236 typedef union {
237 struct {
238 uint32_t C0: 1; /*!< bit: 0 Cacheable setting */
239 uint32_t C1: 1; /*!< bit: 1 Cacheable setting */
240 uint32_t C2: 1; /*!< bit: 2 Cacheable setting */
241 uint32_t C3: 1; /*!< bit: 3 Cacheable setting */
242 uint32_t _reserved0: 4; /*!< bit: 4.. 7 Reserved */
243 uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
244 uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
245 uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
246 uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
247 uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
248 } b; /*!< Structure Access by bit */
249 uint32_t w; /*!< Type Access by whole register */
250 } CAPR_Type;
251
252 /* CAPR Register Definitions */
253 #define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
254 #define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
255
256 #define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
257 #define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
258
259 #define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
260 #define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
261
262 #define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
263 #define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
264
265 #define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
266 #define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
267
268 #define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
269 #define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
270
271 #define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
272 #define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
273
274 #define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
275 #define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
276
277
278 /**
279 \brief Consortium definition for accessing control register(PACR, CR<20,0>).
280 */
281 typedef union {
282 struct {
283 uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
284 uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
285 uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
286 uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
287 } b; /*!< Structure Access by bit */
288 uint32_t w; /*!< Type Access by whole register */
289 } PACR_Type;
290
291 /* PACR Register Definitions */
292 #define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
293 #define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
294
295 #define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
296 #define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
297
298 #define PACR_E_Pos 0U /*!< PACR: E Position */
299 #define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
300
301 /**
302 \brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
303 */
304 typedef union {
305 struct {
306 uint32_t RID: 2; /*!< bit: 0.. 1 Protected area index value */
307 uint32_t _reserved0: 30; /*!< bit: 2..31 Reserved */
308 } b; /*!< Structure Access by bit */
309 uint32_t w; /*!< Type Access by whole register */
310 } PRSR_Type;
311
312 /* PRSR Register Definitions */
313 #define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
314 #define PRSR_RID_Msk (0x3UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
315
316 /**
317 \brief Consortium definition for accessing mmu index register(MIR,CP15_CR0).
318 */
319 typedef union {
320 struct {
321 uint32_t Index: 10;
322 uint32_t _reserved: 20;
323 uint32_t TF: 1;
324 uint32_t P: 1;
325 } b;
326 uint32_t w;
327 } MIR_Type;
328
329 /* MIR Register Definitions */
330 #define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
331 #define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
332
333 #define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
334 #define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
335
336 #define MIR_Index_Pos 0 /*!< PRSR: Index Position */
337 #define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
338
339
340 /**
341 \brief Consortium definition for accessing mmu entry of high physical address register(MEL, CP15_CR2 and CP15_CR3).
342 */
343 typedef union {
344 struct {
345 uint32_t G: 1;
346 uint32_t V: 1;
347 uint32_t D: 1;
348 uint32_t C: 3;
349 uint32_t PFN: 20;
350 uint32_t _reserved: 6;
351 } b;
352 uint32_t w;
353 } MEL_Type;
354
355 /* MEL Register Definitions */
356 #define MEL_PFN_Pos 6 /*!< MEL: PFN Position */
357 #define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
358
359 #define MEL_C_Pos 3 /*!< MEL: C Position */
360 #define MEL_C_Msk (0x7UL << MEL_C_Pos) /*!< MEL: C Mask */
361
362 #define MEL_D_Pos 2 /*!< MEL: D Position */
363 #define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
364
365 #define MEL_V_Pos 1 /*!< MEL: V Position */
366 #define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
367
368 #define MEL_G_Pos 0 /*!< MEL: G Position */
369 #define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
370
371
372 /**
373 \brief Consortium definition for accessing mmu entry of high physical address register(MEH, CP15_CR4).
374 */
375 typedef union {
376 struct {
377 uint32_t ASID :8;
378 uint32_t _reserved :4;
379 uint32_t VPN :20;
380 } b;
381 uint32_t w;
382 } MEH_Type;
383
384 /* MEH Register Definitions */
385 #define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
386 #define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
387
388 #define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
389 #define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
390
391
392 /**
393 \brief Consortium definition for accessing mmu entry of high physical address register(MPR, CP15_CR6).
394 */
395 typedef union {
396 struct {
397 uint32_t _reserved0: 13;
398 uint32_t page_mask: 12;
399 uint32_t _reserved1: 7;
400 } b;
401 uint32_t w;
402 } MPR_Type;
403
404 /* MPR Register Definitions */
405 #define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
406 #define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
407
408
409 /**
410 \brief Consortium definition for accessing mmu entry of high physical address register(MCIR, CP15_CR8).
411 */
412 typedef union {
413 struct {
414 uint32_t ASID: 8;
415 uint32_t _reserved: 17;
416 uint32_t TLBINV_INDEX: 1;
417 uint32_t TLBINV_ALL: 1;
418 uint32_t TLBINV: 1;
419 uint32_t TLBWR: 1;
420 uint32_t TLBWI: 1;
421 uint32_t TLBR: 1;
422 uint32_t TLBP: 1;
423 } b;
424 uint32_t w;
425 } MCIR_Type;
426
427 /* MCIR Register Definitions */
428 #define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
429 #define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
430
431 #define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
432 #define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
433
434 #define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
435 #define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
436
437 #define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
438 #define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
439
440 #define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
441 #define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
442
443 #define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
444 #define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
445
446 #define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
447 #define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
448
449 #define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
450 #define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
451
452
453 /*@} end of group CSI_CORE */
454
455
456 /**
457 \ingroup CSI_core_register
458 \defgroup CSI_CACHE
459 \brief Type definitions for the cache Registers
460 @{
461 */
462
463 #define SSEG0_BASE_ADDR 0x80000000
464 #define CACHE_RANGE_MAX_SIZE 0x80000
465
466 #define INS_CACHE (1 << 0)
467 #define DATA_CACHE (1 << 1)
468 #define CACHE_INV (1 << 4)
469 #define CACHE_CLR (1 << 5)
470 #define CACHE_OMS (1 << 6)
471 #define CACHE_ITS (1 << 7)
472 #define CACHE_LICF (1 << 31)
473
474 #define L1_CACHE_SHIFT 4 /* 16 Bytes */
475 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
476
477 /**
478 \brief Mask and shift a bit field value for use in a register bit range.
479 \param[in] field Name of the register bit field.
480 \param[in] value Value of the bit field.
481 \return Masked and shifted value.
482 */
483 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
484
485 /**
486 \brief Mask and shift a register value to extract a bit filed value.
487 \param[in] field Name of the register bit field.
488 \param[in] value Value of register.
489 \return Masked and shifted bit field value.
490 */
491 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
492
493 /*@} end of group CSI_core_bitfield */
494
495
496 /*******************************************************************************
497 * Hardware Abstraction Layer
498 Core Function Interface contains:
499 - Core VIC Functions
500 - Core CORET Functions
501 - Core Register Access Functions
502 ******************************************************************************/
503 /* ########################## Cache functions #################################### */
504 /**
505 \ingroup CSI_Core_FunctionInterface
506 \defgroup CSI_Core_CacheFunctions Cache Functions
507 \brief Functions that configure Instruction and Data cache.
508 @{
509 */
510
511 /**
512 \brief Enable I-Cache
513 \details Turns on I-Cache
514 */
csi_icache_enable(void)515 __STATIC_INLINE void csi_icache_enable (void)
516 {
517 __set_CCR(__get_CCR() | 0x00000004);
518 }
519
520
521 /**
522 \brief Disable I-Cache
523 \details Turns off I-Cache
524 */
csi_icache_disable(void)525 __STATIC_INLINE void csi_icache_disable (void)
526 {
527 __set_CCR(__get_CCR() & 0xFFFFFFFB);
528 }
529
530
531 /**
532 \brief Invalidate I-Cache
533 \details Invalidates I-Cache
534 */
csi_icache_invalid(void)535 __STATIC_INLINE void csi_icache_invalid (void)
536 {
537 __set_CFR(0x11);
538 __set_CFR(INS_CACHE | CACHE_INV);
539 }
540
541
542 /**
543 \brief Enable D-Cache
544 \details Turns on D-Cache
545 \note I-Cache also turns on.
546 */
csi_dcache_enable(void)547 __STATIC_INLINE void csi_dcache_enable (void)
548 {
549 __set_CCR(__get_CCR() | 0x00000008);
550 }
551
552
553 /**
554 \brief Disable D-Cache
555 \details Turns off D-Cache
556 \note I-Cache also turns off.
557 */
csi_dcache_disable(void)558 __STATIC_INLINE void csi_dcache_disable (void)
559 {
560 __set_CCR(__get_CCR() & 0xFFFFFFF7);
561 }
562
563
564 /**
565 \brief Invalidate D-Cache
566 \details Invalidates D-Cache
567 \note I-Cache also invalid
568 */
csi_dcache_invalid(void)569 __STATIC_INLINE void csi_dcache_invalid (void)
570 {
571 __set_CFR(DATA_CACHE | CACHE_INV);
572 }
573
574
575 /**
576 \brief Clean D-Cache
577 \details Cleans D-Cache
578 \note I-Cache also cleans
579 */
csi_dcache_clean(void)580 __STATIC_INLINE void csi_dcache_clean (void)
581 {
582 __set_CFR(DATA_CACHE | CACHE_CLR);
583 }
584
585
586 /**
587 \brief Clean & Invalidate D-Cache
588 \details Cleans and Invalidates D-Cache
589 \note I-Cache also flush.
590 */
csi_dcache_clean_invalid(void)591 __STATIC_INLINE void csi_dcache_clean_invalid (void)
592 {
593 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
594 }
595
set_cache_range(uint32_t start,uint32_t end,uint32_t value)596 __STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
597 {
598 if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
599 __set_CFR(value);
600 }
601
602 if (value & INS_CACHE) {
603 csi_icache_disable();
604 }
605 uint32_t i;
606 for (i = start; i < end; i += L1_CACHE_BYTES) {
607 __set_CIR(i);
608 __set_CFR(CACHE_OMS | value);
609 }
610
611 if (end & (L1_CACHE_BYTES-1)) {
612 __set_CIR(end);
613 __set_CFR(CACHE_OMS | value);
614 }
615
616 if (value & INS_CACHE) {
617 csi_icache_enable();
618 }
619
620 }
621
622 /**
623 \brief D-Cache Invalidate by address
624 \details Invalidates D-Cache for the given address
625 \param[in] addr address (aligned to 16-byte boundary)
626 \param[in] dsize size of memory block (in number of bytes)
627 */
csi_dcache_invalid_range(uint32_t * addr,int32_t dsize)628 __STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
629 {
630 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
631 }
632
633
634 /**
635 \brief D-Cache Clean by address
636 \details Cleans D-Cache for the given address
637 \param[in] addr address (aligned to 16-byte boundary)
638 \param[in] dsize size of memory block (in number of bytes)
639 */
csi_dcache_clean_range(uint32_t * addr,int32_t dsize)640 __STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
641 {
642 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
643 }
644
645
646 /**
647 \brief D-Cache Clean and Invalidate by address
648 \details Cleans and invalidates D_Cache for the given address
649 \param[in] addr address (aligned to 16-byte boundary)
650 \param[in] dsize size of memory block (in number of bytes)
651 */
csi_dcache_clean_invalid_range(uint32_t * addr,int32_t dsize)652 __STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
653 {
654 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
655 }
656
657 /*@} end of CSI_Core_CacheFunctions */
658
659
660 /* ########################## MMU functions #################################### */
661 /**
662 \ingroup CSI_Core_FunctionInterface
663 \defgroup CSI_Core_MMUFunctions MMU Functions
664 \brief Functions that configure MMU.
665 @{
666 */
667
668 typedef struct {
669 uint32_t global: 1; /* tlb page global access. */
670 uint32_t valid: 1; /* tlb page valid */
671 uint32_t writeable: 1; /* tlb page writeable */
672 uint32_t cacheable: 1; /* tlb page cacheable*/
673 } page_attr_t;
674
675 typedef enum {
676 PAGE_SIZE_4KB = 0x000,
677 PAGE_SIZE_16KB = 0x003,
678 PAGE_SIZE_64KB = 0x00F,
679 PAGE_SIZE_256KB = 0x03F,
680 PAGE_SIZE_1MB = 0x0FF,
681 PAGE_SIZE_4MB = 0x3FF,
682 PAGE_SIZE_16MB = 0xFFF
683 } page_size_e;
684
685 /**
686 \brief enable mmu
687 \details
688 */
csi_mmu_enable(void)689 __STATIC_INLINE void csi_mmu_enable(void)
690 {
691 __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
692 }
693
694 /**
695 \brief disable mmu
696 \details
697 */
csi_mmu_disable(void)698 __STATIC_INLINE void csi_mmu_disable(void)
699 {
700 __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
701 }
702
703 /**
704 \brief create page with feature.
705 \details
706 \param [in] vaddr virtual address.
707 \param [in] paddr physical address.
708 \param [in] asid address sapce id (default: 0).
709 \param [in] attr \ref page_attr_t. tlb page attribute.
710 */
csi_mmu_set_tlb(uint32_t vaddr,uint32_t paddr,uint32_t asid,page_attr_t attr)711 __STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
712 {
713 MPR_Type pgmask;
714 MEL_Type mel;
715 MEH_Type meh;
716 uint32_t vaddr_bit = 0;
717 uint32_t page_feature = 0;
718
719 page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
720 attr.writeable << MEL_D_Pos | (attr.cacheable | 0x2) << MEL_C_Pos;
721
722 pgmask.w = __FF1(__get_MPR());
723 vaddr_bit = (pgmask.w == 32 ? 12 : (31 - pgmask.w));
724
725 meh.b.ASID = asid;
726 meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
727 __set_MEH(meh.w);
728
729 __set_MCIR(1u << MCIR_TLBP_Pos);
730
731 mel.w = (((paddr >> 6) & ~(pgmask.b.page_mask << 6)) | page_feature);
732
733 if (vaddr & (1 << vaddr_bit)) {
734 __set_MEL1(mel.w);
735 } else {
736 __set_MEL0(mel.w);
737 }
738
739 if (__get_MIR() & (1 << MIR_P_Pos)) {
740 __set_MCIR(1u << MCIR_TLBWR_Pos);
741 } else {
742 __set_MCIR(1u << MCIR_TLBWI_Pos);
743 }
744 }
745
746
747 /**
748 \brief enble mmu
749 \details
750 \param [in] size tlb page size.
751 */
csi_mmu_set_pagesize(page_size_e size)752 __STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
753 {
754 MPR_Type mpr;
755 mpr.w = __get_MPR();
756 mpr.b.page_mask = size;
757 __set_MPR(mpr.w);
758 }
759
760
761 /**
762 \brief read MEH, MEL0, MEL1 by tlb index.
763 \details
764 \param [in] index tlb index(0, 1, 2, ...)
765 \param [out] meh pointer to variable for retrieving MEH.
766 \param [out] mel0 pointer to variable for retrieving MEL0.
767 \param [out] mel1 pointer to variable for retrieving MEL1.
768 */
csi_mmu_read_by_index(uint32_t index,uint32_t * meh,uint32_t * mel0,uint32_t * mel1)769 __STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
770 {
771 MIR_Type mir;
772
773 if (meh == NULL || mel0 == NULL || mel1 == NULL) {
774 return;
775 }
776
777 mir.b.Index = index;
778 __set_MIR(mir.w);
779 __set_MCIR(1u << MCIR_TLBR_Pos);
780
781 *meh = __get_MEH();
782 *mel0 = __get_MEL0();
783 *mel1 = __get_MEL1();
784 }
785
786
787 /**
788 \brief flush all mmu tlb.
789 \details
790 */
csi_mmu_invalid_tlb_all(void)791 __STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
792 {
793 __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
794 }
795
796
797 /**
798 \brief flush mmu tlb by index.
799 \details
800 */
csi_mmu_invalid_tlb_by_index(uint32_t index)801 __STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
802 {
803 MIR_Type mir;
804
805 mir.b.Index = index;
806 __set_MIR(mir.w);
807 __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
808 }
809
810
811 /**
812 \brief flush mmu tlb by virtual address.
813 \details
814 */
csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr,uint32_t asid)815 __STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
816 {
817 __set_MEH(vaddr | (asid & MEH_ASID_Msk));
818 __set_MCIR(__get_MCIR() | (1 << MCIR_TLBP_Pos));
819
820 if (__get_MIR() & (1 << MIR_P_Pos)) {
821 return;
822 } else {
823 __set_MCIR(__get_MCIR() | (1 << MCIR_TLBINV_INDEX_Pos));
824 }
825 }
826
827 /*@} end of CSI_Core_MMUFunctions */
828
829 /* ########################## MPU functions #################################### */
830 /**
831 \ingroup CSI_Core_FunctionInterface
832 \defgroup CSI_Core_MPUFunctions MPU Functions
833 \brief Functions that configure MPU.
834 @{
835 */
836
837 typedef enum {
838 REGION_SIZE_4KB = 0xB,
839 REGION_SIZE_8KB = 0xC,
840 REGION_SIZE_16KB = 0xD,
841 REGION_SIZE_32KB = 0xE,
842 REGION_SIZE_64KB = 0xF,
843 REGION_SIZE_128KB = 0x10,
844 REGION_SIZE_256KB = 0x11,
845 REGION_SIZE_512KB = 0x12,
846 REGION_SIZE_1MB = 0x13,
847 REGION_SIZE_2MB = 0x14,
848 REGION_SIZE_4MB = 0x15,
849 REGION_SIZE_8MB = 0x16,
850 REGION_SIZE_16MB = 0x17,
851 REGION_SIZE_32MB = 0x18,
852 REGION_SIZE_64MB = 0x19,
853 REGION_SIZE_128MB = 0x1A,
854 REGION_SIZE_256MB = 0x1B,
855 REGION_SIZE_512MB = 0x1C,
856 REGION_SIZE_1GB = 0x1D,
857 REGION_SIZE_2GB = 0x1E,
858 REGION_SIZE_4GB = 0x1F
859 } region_size_e;
860
861 typedef enum {
862 AP_BOTH_INACCESSIBLE = 0,
863 AP_SUPER_RW_USER_INACCESSIBLE,
864 AP_SUPER_RW_USER_RDONLY,
865 AP_BOTH_RW
866 } access_permission_e;
867
868 typedef struct {
869 access_permission_e ap: 2; /* super user and normal user access.*/
870 uint32_t c: 1; /* cacheable */
871 } mpu_region_attr_t;
872 /**
873 \brief enable mpu
874 \details
875 */
csi_mpu_enable(void)876 __STATIC_INLINE void csi_mpu_enable(void)
877 {
878 __set_CCR(__get_CCR() | CCR_MP_Msk);
879 }
880
881 /**
882 \brief disable mpu
883 \details
884 */
csi_mpu_disable(void)885 __STATIC_INLINE void csi_mpu_disable(void)
886 {
887 __set_CCR(__get_CCR() & (~CCR_MP_Msk));
888 }
889
890 /**
891 \brief configure memory protected region.
892 \details
893 \param [in] idx memory protected region (0, 1, 2, 3.).
894 \param [in] base_addr base address must be aligned with page size.
895 \param [in] size \ref region_size_e. memory protected region size.
896 \param [in] attr \ref region_size_t. memory protected region attribute.
897 \param [in] enable enable or disable memory protected region.
898 */
csi_mpu_config_region(uint32_t idx,uint32_t base_addr,region_size_e size,mpu_region_attr_t attr,uint32_t enable)899 __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
900 mpu_region_attr_t attr, uint32_t enable)
901 {
902 if (idx > 3) {
903 return;
904 }
905
906 CAPR_Type capr;
907 PACR_Type pacr;
908 PRSR_Type prsr;
909
910 capr.w = __get_CAPR();
911 pacr.w = __get_PACR();
912 prsr.w = __get_PRSR();
913
914 pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
915
916 prsr.b.RID = idx;
917 __set_PRSR(prsr.w);
918
919 if (size != REGION_SIZE_4KB) {
920 pacr.w &= ~(((1u << (size -11)) - 1) << 12);
921 }
922
923 pacr.b.size = size;
924
925 capr.w = (0xFFFFFFFE & capr.w) | (attr.c << idx);
926 capr.w = ((~((0x3) << (2*idx + 8))) & capr.w) | (attr.ap << (2*idx + 8));
927 __set_CAPR(capr.w);
928
929 pacr.b.E = enable;
930 __set_PACR(pacr.w);
931 }
932
933 /**
934 \brief enable mpu region by idx.
935 \details
936 \param [in] idx memory protected region (0, 1, 2, 3.).
937 */
csi_mpu_enable_region(uint32_t idx)938 __STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
939 {
940 if (idx > 3) {
941 return;
942 }
943
944 __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
945 __set_PACR(__get_PACR() | PACR_E_Msk);
946 }
947
948 /**
949 \brief disable mpu region by idx.
950 \details
951 \param [in] idx memory protected region (0, 1, 2, 3.).
952 */
csi_mpu_disable_region(uint32_t idx)953 __STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
954 {
955 if (idx > 3) {
956 return;
957 }
958
959 __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
960 __set_PACR(__get_PACR() & (~PACR_E_Msk));
961 }
962
963 /*@} end of CSI_Core_MMUFunctions */
964
965 /*@} */
966
967 #ifdef __cplusplus
968 }
969 #endif
970
971 #endif /* __CORE_CK610_H_DEPENDANT */
972
973 #endif /* __CSI_GENERIC */
974