1 /*
2 * Copyright (C) 2017-2019 Alibaba Group Holding Limited
3 */
4
5
6 /******************************************************************************
7 * @file core_ck807.h
8 * @brief CSI CK807 Core Peripheral Access Layer Header File
9 * @version V1.0
10 * @date 26. Jan 2018
11 ******************************************************************************/
12
13 #ifndef __CORE_CK807_H_GENERIC
14 #define __CORE_CK807_H_GENERIC
15
16 #include <stdint.h>
17
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21
22 /*******************************************************************************
23 * CSI definitions
24 ******************************************************************************/
25 /**
26 \ingroup CK807
27 @{
28 */
29
30 /* CSI CK807 definitions */
31 #define __CK807_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
32 #define __CK807_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
33 #define __CK807_CSI_VERSION ((__CK807_CSI_VERSION_MAIN << 16U) | \
34 __CK807_CSI_VERSION_SUB ) /*!< CSI HAL version number */
35
36 #ifndef __CK807
37 #define __CK807 (0x07U) /*!< CK807 Core */
38 #endif
39
40 /** __FPU_USED indicates whether an FPU is used or not.
41 */
42 #define __FPU_USED 1U
43
44 #if defined ( __GNUC__ )
45 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
46 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
47 #endif
48 #endif
49
50 #ifdef __cplusplus
51 }
52 #endif
53
54 #endif /* __CORE_CK807_H_GENERIC */
55
56 #ifndef __CSI_GENERIC
57
58 #ifndef __CORE_CK807_H_DEPENDANT
59 #define __CORE_CK807_H_DEPENDANT
60
61 #ifdef __cplusplus
62 extern "C" {
63 #endif
64
65 /* check device defines and use defaults */
66 #ifndef __CK807_REV
67 #define __CK807_REV 0x0000U
68 #endif
69
70 #ifndef __GSR_GCR_PRESENT
71 #define __GSR_GCR_PRESENT 0U
72 #endif
73
74 #ifndef __ICACHE_PRESENT
75 #define __ICACHE_PRESENT 1U
76 #endif
77
78 #ifndef __DCACHE_PRESENT
79 #define __DCACHE_PRESENT 1U
80 #endif
81
82 #include <csi_gcc.h>
83
84 /* IO definitions (access restrictions to peripheral registers) */
85 /**
86 \defgroup CSI_glob_defs CSI Global Defines
87
88 <strong>IO Type Qualifiers</strong> are used
89 \li to specify the access to peripheral variables.
90 \li for automatic generation of peripheral register debug information.
91 */
92 #ifdef __cplusplus
93 #define __I volatile /*!< Defines 'read only' permissions */
94 #else
95 #define __I volatile const /*!< Defines 'read only' permissions */
96 #endif
97 #define __O volatile /*!< Defines 'write only' permissions */
98 #define __IO volatile /*!< Defines 'read / write' permissions */
99
100 /* following defines should be used for structure members */
101 #define __IM volatile const /*! Defines 'read only' structure member permissions */
102 #define __OM volatile /*! Defines 'write only' structure member permissions */
103 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
104
105 /*@} end of group CK807 */
106
107 /*******************************************************************************
108 * Register Abstraction
109 Core Register contain:
110 - Core Register
111 ******************************************************************************/
112 /**
113 \defgroup CSI_core_register Defines and Type Definitions
114 \brief Type definitions and defines for CK807 processor based devices.
115 */
116
117 /**
118 \ingroup CSI_core_register
119 \defgroup CSI_CORE Status and Control Registers
120 \brief Core Register type definitions.
121 @{
122 */
123
124 /**
125 \brief Access Processor Status Register(PSR)struct definition.
126 */
127 typedef union {
128 struct {
129 uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
130 uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
131 uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
132 uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
133 uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
134 uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
135 uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
136 uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
137 uint32_t _reserved2: 5; /*!< bit: 24..28 Reserved */
138 uint32_t SP: 1; /*!< bit: 29 Secure pedning bit */
139 uint32_t T: 1; /*!< bit: 30 TEE mode bit */
140 uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
141 } b; /*!< Structure Access by bit */
142 uint32_t w; /*!< Type Access by whole register */
143 } PSR_Type;
144
145 /* PSR Register Definitions */
146 #define PSR_S_Pos 31U /*!< PSR: S Position */
147 #define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
148
149 #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
150 #define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
151
152 #define PSR_MM_Pos 9U /*!< PSR: MM Position */
153 #define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
154
155 #define PSR_EE_Pos 8U /*!< PSR: EE Position */
156 #define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
157
158 #define PSR_IC_Pos 7U /*!< PSR: IC Position */
159 #define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
160
161 #define PSR_IE_Pos 6U /*!< PSR: IE Position */
162 #define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
163
164 #define PSR_C_Pos 0U /*!< PSR: C Position */
165 #define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
166
167 /**
168 \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
169 */
170 typedef union {
171 struct {
172 uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
173 uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
174 uint32_t DE: 1; /*!< bit: 3 Data cache enable */
175 uint32_t WB: 1; /*!< bit: 4 Cache write back */
176 uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
177 uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
178 uint32_t BE: 1; /*!< bit: 7 Endian mode */
179 uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
180 uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
181 uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
182 uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
183 uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
184 uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
185 uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
186 } b; /*!< Structure Access by bit */
187 uint32_t w; /*!< Type Access by whole register */
188 } CCR_Type;
189
190 /* CCR Register Definitions */
191 #define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
192 #define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
193
194 #define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
195 #define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
196
197 #define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
198 #define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
199
200 #define CCR_WA_Pos 12u /*!< CCR: WA Position */
201 #define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
202
203 #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
204 #define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
205
206 #define CCR_BE_Pos 7U /*!< CCR: BE Position */
207 #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
208
209 #define CCR_Z_Pos 6U /*!< CCR: Z Position */
210 #define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
211
212 #define CCR_RS_Pos 5U /*!< CCR: RS Position */
213 #define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
214
215 #define CCR_WB_Pos 4U /*!< CCR: WB Position */
216 #define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
217
218 #define CCR_DE_Pos 3U /*!< CCR: DE Position */
219 #define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
220
221 #define CCR_IE_Pos 2U /*!< CCR: IE Position */
222 #define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
223
224 #define CCR_MP_Pos 0U /*!< CCR: MP Position */
225 #define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
226
227 /**
228 \brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
229 */
230 typedef union {
231 struct {
232 uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
233 uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
234 uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
235 uint32_t P: 1; /*!< bit: 31 TLBP instruction */
236 } b;
237 uint32_t w;
238 } MIR_Type;
239
240 /* MIR Register Definitions */
241 #define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
242 #define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
243
244 #define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
245 #define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
246
247 #define MIR_Index_Pos 0 /*!< PRSR: Index Position */
248 #define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
249
250
251 /**
252 \brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
253 */
254 typedef union {
255 struct {
256 uint32_t G: 1; /*!< bit: 0 Global enbale bit */
257 uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
258 uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
259 uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
260 uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
261 uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
262 uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
263 uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
264 uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
265 } b;
266 uint32_t w;
267 } MEL_Type;
268
269 /* MEL Register Definitions */
270 #define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
271 #define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
272
273 #define MEL_B_Pos 6 /*!< MEL: B Position */
274 #define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
275
276 #define MEL_SO_Pos 5 /*!< MEL: SO Position */
277 #define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
278
279 #define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
280 #define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
281
282 #define MEL_C_Pos 3 /*!< MEL: C Position */
283 #define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
284
285 #define MEL_D_Pos 2 /*!< MEL: D Position */
286 #define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
287
288 #define MEL_V_Pos 1 /*!< MEL: V Position */
289 #define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
290
291 #define MEL_G_Pos 0 /*!< MEL: G Position */
292 #define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
293
294
295 /**
296 \brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
297 */
298 typedef union {
299 struct {
300 uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
301 uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
302 uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
303 } b;
304 uint32_t w;
305 } MEH_Type;
306
307 /* MEH Register Definitions */
308 #define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
309 #define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
310
311 #define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
312 #define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
313
314
315 /**
316 \brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
317 */
318
319 typedef union {
320 struct {
321 uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
322 uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
323 uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
324 } b;
325 uint32_t w;
326 } MPR_Type;
327
328 /* MPR Register Definitions */
329 #define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
330 #define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
331
332
333 /**
334 \brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
335 */
336 typedef union {
337 struct {
338 uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
339 uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
340 uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
341 uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
342 uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
343 uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
344 uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
345 uint32_t TLBR: 1; /*!< bit: 30 TLBR */
346 uint32_t TLBP: 1; /*!< bit: 31 TLBP */
347 } b;
348 uint32_t w;
349 } MCIR_Type;
350
351 /* MCIR Register Definitions */
352 #define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
353 #define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
354
355 #define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
356 #define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
357
358 #define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
359 #define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
360
361 #define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
362 #define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
363
364 #define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
365 #define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
366
367 #define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
368 #define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
369
370 #define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
371 #define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
372
373 #define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
374 #define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
375
376
377 /*@} end of group CSI_CORE */
378
379
380 /**
381 \ingroup CSI_core_register
382 \defgroup CSI_CACHE
383 \brief Type definitions for the cache Registers
384 @{
385 */
386
387 /**
388 \brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
389 */
390 typedef union {
391 struct {
392 uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
393 uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
394 uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
395 uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
396 uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
397 uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
398 uint32_t _reserved1: 8; /*!< bit: 8..15 Reserved */
399 uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
400 uint32_t _reserved2: 14; /*!< bit: 17..30 Reserved */
401 uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
402 } b; /*!< Structure Access by bit */
403 uint32_t w; /*!< Type Access by whole register */
404 } CFR_Type;
405
406 #define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
407 #define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
408
409 #define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
410 #define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
411
412 #define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
413 #define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
414
415 #define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
416 #define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
417
418 #define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
419 #define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
420
421 #define CFR_INV_Pos 4U /*!< CFR: INV Position */
422 #define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
423
424 #define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
425 #define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
426
427 /* CFR Register Definitions */
428 /*@} end of group CSI_CACHE */
429
430
431 /**
432 \ingroup CSI_core_register
433 \defgroup CSI_CACHE
434 \brief Type definitions for the cache Registers
435 @{
436 */
437 #define SSEG0_BASE_ADDR 0x80000000
438 #define CACHE_RANGE_MAX_SIZE 0x80000
439
440 #define INS_CACHE (1 << 0)
441 #define DATA_CACHE (1 << 1)
442 #define CACHE_INV (1 << 4)
443 #define CACHE_CLR (1 << 5)
444 #define CACHE_OMS (1 << 6)
445 #define CACHE_ITS (1 << 7)
446 #define CACHE_LICF (1 << 31)
447
448 #define L1_CACHE_SHIFT 4 /* 16 Bytes */
449 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
450
451 /**
452 \brief Mask and shift a bit field value for use in a register bit range.
453 \param[in] field Name of the register bit field.
454 \param[in] value Value of the bit field.
455 \return Masked and shifted value.
456 */
457 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
458
459 /**
460 \brief Mask and shift a register value to extract a bit filed value.
461 \param[in] field Name of the register bit field.
462 \param[in] value Value of register.
463 \return Masked and shifted bit field value.
464 */
465 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
466
467 /*@} end of group CSI_core_bitfield */
468
469
470 /*******************************************************************************
471 * Hardware Abstraction Layer
472 Core Function Interface contains:
473 - Core VIC Functions
474 - Core CORET Functions
475 - Core Register Access Functions
476 ******************************************************************************/
477
478 /* The following MACROS handle generation of the register offset and byte masks */
479 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
480 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
481
482
483 /* ########################## Cache functions #################################### */
484 /**
485 \ingroup CSI_Core_FunctionInterface
486 \defgroup CSI_Core_CacheFunctions Cache Functions
487 \brief Functions that configure Instruction and Data cache.
488 @{
489 */
490
491 /**
492 \brief Enable I-Cache
493 \details Turns on I-Cache
494 */
csi_icache_enable(void)495 __STATIC_INLINE void csi_icache_enable (void)
496 {
497 __set_CCR(__get_CCR() | 0x00000004);
498 }
499
500
501 /**
502 \brief Disable I-Cache
503 \details Turns off I-Cache
504 */
csi_icache_disable(void)505 __STATIC_INLINE void csi_icache_disable (void)
506 {
507 __set_CCR(__get_CCR() & 0xFFFFFFFB);
508 }
509
510
511 /**
512 \brief Invalidate I-Cache
513 \details Invalidates I-Cache
514 */
csi_icache_invalid(void)515 __STATIC_INLINE void csi_icache_invalid (void)
516 {
517 __set_CFR(0x11);
518 __set_CFR(INS_CACHE | CACHE_INV);
519 }
520
521
522 /**
523 \brief Enable D-Cache
524 \details Turns on D-Cache
525 \note I-Cache also turns on.
526 */
csi_dcache_enable(void)527 __STATIC_INLINE void csi_dcache_enable (void)
528 {
529 __set_CCR(__get_CCR() | 0x00000008);
530 }
531
532
533 /**
534 \brief Disable D-Cache
535 \details Turns off D-Cache
536 \note I-Cache also turns off.
537 */
csi_dcache_disable(void)538 __STATIC_INLINE void csi_dcache_disable (void)
539 {
540 __set_CCR(__get_CCR() & 0xFFFFFFF7);
541 }
542
543
544 /**
545 \brief Invalidate D-Cache
546 \details Invalidates D-Cache
547 \note I-Cache also invalid
548 */
csi_dcache_invalid(void)549 __STATIC_INLINE void csi_dcache_invalid (void)
550 {
551 __set_CFR(DATA_CACHE | CACHE_INV);
552 }
553
554
555 /**
556 \brief Clean D-Cache
557 \details Cleans D-Cache
558 \note I-Cache also cleans
559 */
csi_dcache_clean(void)560 __STATIC_INLINE void csi_dcache_clean (void)
561 {
562 __set_CFR(DATA_CACHE | CACHE_CLR);
563 }
564
565 /**
566 \brief Clean & Invalidate D-Cache
567 \details Cleans and Invalidates D-Cache
568 \note I-Cache also flush.
569 */
csi_dcache_clean_invalid(void)570 __STATIC_INLINE void csi_dcache_clean_invalid (void)
571 {
572 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
573 }
574
set_cache_range(uint32_t start,uint32_t end,uint32_t value)575 __STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
576 {
577 if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
578 __set_CFR(value);
579 }
580
581 if (value & INS_CACHE) {
582 csi_icache_disable();
583 }
584 uint32_t i;
585 for (i = start; i < end; i += L1_CACHE_BYTES) {
586 __set_CIR(i);
587 __set_CFR(CACHE_OMS | value);
588 }
589
590 if (end & (L1_CACHE_BYTES-1)) {
591 __set_CIR(end);
592 __set_CFR(CACHE_OMS | value);
593 }
594
595 if (value & INS_CACHE) {
596 csi_icache_enable();
597 }
598
599 }
600
601 /**
602 \brief D-Cache Invalidate by address
603 \details Invalidates D-Cache for the given address
604 \param[in] addr address (aligned to 16-byte boundary)
605 \param[in] dsize size of memory block (in number of bytes)
606 */
csi_dcache_invalid_range(uint32_t * addr,int32_t dsize)607 __STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
608 {
609 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
610 }
611
612
613 /**
614 \brief D-Cache Clean by address
615 \details Cleans D-Cache for the given address
616 \param[in] addr address (aligned to 16-byte boundary)
617 \param[in] dsize size of memory block (in number of bytes)
618 */
csi_dcache_clean_range(uint32_t * addr,int32_t dsize)619 __STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
620 {
621 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
622 }
623
624
625 /**
626 \brief D-Cache Clean and Invalidate by address
627 \details Cleans and invalidates D_Cache for the given address
628 \param[in] addr address (aligned to 16-byte boundary)
629 \param[in] dsize size of memory block (in number of bytes)
630 */
csi_dcache_clean_invalid_range(uint32_t * addr,int32_t dsize)631 __STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
632 {
633 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
634 }
635
636
637 /*@} end of CSI_Core_CacheFunctions */
638
639
640 /* ########################## MMU functions #################################### */
641 /**
642 \ingroup CSI_Core_FunctionInterface
643 \defgroup CSI_Core_MMUFunctions MMU Functions
644 \brief Functions that configure MMU.
645 @{
646 */
647
648 typedef struct {
649 uint32_t global: 1; /* tlb page global access. */
650 uint32_t valid: 1; /* tlb page valid */
651 uint32_t writeable: 1; /* tlb page writeable */
652 uint32_t cacheable: 1; /* tlb page cacheable*/
653 uint32_t is_secure: 1; /* tlb page security access */
654 uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
655 uint32_t bufferable: 1; /* tlb page bufferable */
656 } page_attr_t;
657
658 typedef enum {
659 PAGE_SIZE_4KB = 0x000,
660 PAGE_SIZE_16KB = 0x003,
661 PAGE_SIZE_64KB = 0x00F,
662 PAGE_SIZE_256KB = 0x03F,
663 PAGE_SIZE_1MB = 0x0FF,
664 PAGE_SIZE_4MB = 0x3FF,
665 PAGE_SIZE_16MB = 0xFFF
666 } page_size_e;
667
668
669 /**
670 \brief enable mmu
671 \details
672 */
csi_mmu_enable(void)673 __STATIC_INLINE void csi_mmu_enable(void)
674 {
675 __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
676 }
677
678 /**
679 \brief disable mmu
680 \details
681 */
csi_mmu_disable(void)682 __STATIC_INLINE void csi_mmu_disable(void)
683 {
684 __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
685 }
686
687 /**
688 \brief create page with feature.
689 \details
690 \param [in] vaddr virtual address.
691 \param [in] paddr physical address.
692 \param [in] asid address sapce id (default: 0).
693 \param [in] attr \ref page_attr_t. tlb page attribute.
694 */
csi_mmu_set_tlb(uint32_t vaddr,uint32_t paddr,uint32_t asid,page_attr_t attr)695 __STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
696 {
697 MPR_Type pgmask;
698 MEH_Type meh;
699 MEL_Type mel;
700 uint32_t vaddr_bit;
701 uint32_t page_feature = 0;
702
703 page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
704 attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
705 attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
706 attr.bufferable << MEL_B_Pos;
707
708 pgmask.w = __get_MPR();
709 vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
710
711 meh.b.ASID = (uint8_t)asid;
712 meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
713 __set_MEH(meh.w);
714
715 __set_MCIR(1u << MCIR_TLBP_Pos);
716
717 mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
718 if (vaddr & (1 << vaddr_bit)) {
719 __set_MEL1(mel.w);
720 }
721 else {
722 __set_MEL0(mel.w);
723 }
724
725 if (__get_MIR() & (1 << MIR_P_Pos)) {
726 __set_MCIR(1u << MCIR_TLBWR_Pos);
727 } else {
728 __set_MCIR(1u << MCIR_TLBWI_Pos);
729 }
730 }
731
732
733 /**
734 \brief enble mmu
735 \details
736 \param [in] size tlb page size.
737 */
csi_mmu_set_pagesize(page_size_e size)738 __STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
739 {
740 MPR_Type pgmask;
741 pgmask.b.page_mask = size;
742 __set_MPR(pgmask.w);
743 }
744
745
746 /**
747 \brief read MEH, MEL0, MEL1 by tlb index.
748 \details
749 \param [in] index tlb index(0, 1, 2, ...)
750 \param [out] meh pointer to variable for retrieving MEH.
751 \param [out] mel0 pointer to variable for retrieving MEL0.
752 \param [out] mel1 pointer to variable for retrieving MEL1.
753 */
csi_mmu_read_by_index(uint32_t index,uint32_t * meh,uint32_t * mel0,uint32_t * mel1)754 __STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
755 {
756 MIR_Type mir;
757
758 if (meh == NULL || mel0 == NULL || mel1 == NULL) {
759 return;
760 }
761
762 mir.b.Index = index;
763 __set_MIR(mir.w);
764 __set_MCIR(1u << MCIR_TLBR_Pos);
765
766 *meh = __get_MEH();
767 *mel0 = __get_MEL0();
768 *mel1 = __get_MEL1();
769 }
770
771
772 /**
773 \brief flush all mmu tlb.
774 \details
775 */
csi_mmu_invalid_tlb_all(void)776 __STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
777 {
778 __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
779 }
780
781 /**
782 \brief flush mmu tlb by index.
783 \details
784 */
csi_mmu_invalid_tlb_by_index(uint32_t index)785 __STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
786 {
787 MIR_Type mir;
788
789 mir.b.Index = index;
790 __set_MIR(mir.w);
791 __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
792 }
793
794
795 /**
796 \brief flush mmu tlb by virtual address.
797 \details
798 */
csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr,uint32_t asid)799 __STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
800 {
801 __set_MEH(vaddr | (asid & MEH_ASID_Msk));
802 __set_MCIR(1u << MCIR_TLBP_Pos);
803
804 if (__get_MIR() & (1 << MIR_P_Pos)) {
805 return;
806 } else {
807 __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
808 }
809 }
810
811 /*@} end of CSI_Core_MMUFunctions */
812
813
814 /* ################################## IRQ Functions ############################################ */
815
816 /**
817 \brief Save the Irq context
818 \details save the psr result before disable irq.
819 \param [in] irq_num External interrupt number. Value cannot be negative.
820 */
csi_irq_save(void)821 __STATIC_INLINE uint32_t csi_irq_save(void)
822 {
823 uint32_t result;
824 result = __get_PSR();
825 __disable_irq();
826 return(result);
827 }
828
829 /**
830 \brief Restore the Irq context
831 \details restore saved primask state.
832 \param [in] irq_state psr irq state.
833 */
csi_irq_restore(uint32_t irq_state)834 __STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
835 {
836 __set_PSR(irq_state);
837 }
838
839 /*@} end of IRQ Functions */
840
841 #ifdef __cplusplus
842 }
843 #endif
844
845 #endif /* __CORE_CK807_H_DEPENDANT */
846
847 #endif /* __CSI_GENERIC */
848