1 /*
2 * Copyright (C) 2017-2019 Alibaba Group Holding Limited
3 */
4
5
6 /******************************************************************************
7 * @file core_801.h
8 * @brief CSI 801 Core Peripheral Access Layer Header File
9 * @version V1.0
10 * @date 02. June 2017
11 ******************************************************************************/
12
13 #ifndef __CORE_801_H_GENERIC
14 #define __CORE_801_H_GENERIC
15
16 #include <stdint.h>
17
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21
22 /*******************************************************************************
23 * CSI definitions
24 ******************************************************************************/
25 /**
26 \ingroup Ck801
27 @{
28 */
29
30 /* CSI CK801 definitions */
31 #define __CK801_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
32 #define __CK801_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
33 #define __CK801_CSI_VERSION ((__CK801_CSI_VERSION_MAIN << 16U) | \
34 __CK801_CSI_VERSION_SUB ) /*!< CSI HAL version number */
35
36 #ifndef __CK80X
37 #define __CK80X (0x01U) /*!< CK80X Core */
38 #endif
39
40 /** __FPU_USED indicates whether an FPU is used or not.
41 This core does not support an FPU at all
42 */
43 #define __FPU_USED 0U
44
45 #if defined ( __GNUC__ )
46 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
47 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
48 #endif
49 #endif
50
51 #ifdef __cplusplus
52 }
53 #endif
54
55 #endif /* __CORE_CK801_H_GENERIC */
56
57 #ifndef __CSI_GENERIC
58
59 #ifndef __CORE_CK801_H_DEPENDANT
60 #define __CORE_CK801_H_DEPENDANT
61
62 #ifdef __cplusplus
63 extern "C" {
64 #endif
65
66 /* check device defines and use defaults */
67 #ifndef __CK801_REV
68 #define __CK801_REV 0x0000U
69 #endif
70
71 #ifndef __VIC_PRIO_BITS
72 #define __VIC_PRIO_BITS 2U
73 #endif
74
75 #ifndef __Vendor_SysTickConfig
76 #define __Vendor_SysTickConfig 1U
77 #endif
78
79 #ifndef __GSR_GCR_PRESENT
80 #define __GSR_GCR_PRESENT 0U
81 #endif
82
83 #ifndef __MPU_PRESENT
84 #define __MPU_PRESENT 1U
85 #endif
86
87 #include <core/csi_gcc.h>
88
89 /* IO definitions (access restrictions to peripheral registers) */
90 /**
91 \defgroup CSI_glob_defs CSI Global Defines
92
93 <strong>IO Type Qualifiers</strong> are used
94 \li to specify the access to peripheral variables.
95 \li for automatic generation of peripheral register debug information.
96 */
97 #ifdef __cplusplus
98 #define __I volatile /*!< Defines 'read only' permissions */
99 #else
100 #define __I volatile const /*!< Defines 'read only' permissions */
101 #endif
102 #define __O volatile /*!< Defines 'write only' permissions */
103 #define __IO volatile /*!< Defines 'read / write' permissions */
104
105 /* following defines should be used for structure members */
106 #define __IM volatile const /*! Defines 'read only' structure member permissions */
107 #define __OM volatile /*! Defines 'write only' structure member permissions */
108 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
109
110 /*@} end of group CK801 */
111
112 /*******************************************************************************
113 * Register Abstraction
114 Core Register contain:
115 - Core Register
116 - Core VIC Register
117 - Core Cache Register
118 - Core CoreTIM Register
119 ******************************************************************************/
120 /**
121 \defgroup CSI_core_register Defines and Type Definitions
122 \brief Type definitions and defines for CK80X processor based devices.
123 */
124
125 /**
126 \ingroup CSI_core_register
127 \defgroup CSI_CORE Status and Control Registers
128 \brief Core Register type definitions.
129 @{
130 */
131
132 /**
133 \brief Access Processor Status Register(PSR)struct definition.
134 */
135 typedef union {
136 struct {
137 uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
138 uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
139 uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
140 uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
141 uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
142 uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
143 uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
144 uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
145 uint32_t _reserved2: 7; /*!< bit: 24..30 Reserved */
146 uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
147 } b; /*!< Structure Access by bit */
148 uint32_t w; /*!< Type Access by whole register */
149 } PSR_Type;
150
151 /* PSR Register Definitions */
152 #define PSR_S_Pos 31U /*!< PSR: S Position */
153 #define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
154
155 #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
156 #define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
157
158 #define PSR_MM_Pos 9U /*!< PSR: MM Position */
159 #define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
160
161 #define PSR_EE_Pos 8U /*!< PSR: EE Position */
162 #define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
163
164 #define PSR_IC_Pos 7U /*!< PSR: IC Position */
165 #define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
166
167 #define PSR_IE_Pos 6U /*!< PSR: IE Position */
168 #define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
169
170 #define PSR_C_Pos 0U /*!< PSR: C Position */
171 #define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
172
173 /**
174 \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
175 */
176 typedef union {
177 struct {
178 uint32_t MP: 1; /*!< bit: 0 memory protection settings */
179 uint32_t _reserved0: 6; /*!< bit: 1.. 6 Reserved */
180 uint32_t BE: 1; /*!< bit: 7 Endian mode */
181 uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
182 uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
183 uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
184 uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
185 } b; /*!< Structure Access by bit */
186 uint32_t w; /*!< Type Access by whole register */
187 } CCR_Type;
188
189 /* CCR Register Definitions */
190 #define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
191 #define CCR_BE_V2_Msk (0x1UL << CCR_ISR_Pos) /*!< CCR: BE_V2 Mask */
192
193 #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
194 #define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
195
196 #define CCR_BE_Pos 7U /*!< CCR: BE Position */
197 #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
198
199 #define CCR_MP_Pos 0U /*!< CCR: MP Position */
200 #define CCR_MP_Msk (0x1UL << CCR_MP_Pos) /*!< CCR: MP Mask */
201
202 /**
203 \brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
204 */
205 typedef union {
206 struct {
207 uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
208 uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
209 uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
210 uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
211 uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
212 uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
213 uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
214 uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
215 uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
216 uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
217 uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
218 uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
219 uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
220 uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
221 uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
222 uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
223 uint32_t S0: 1; /*!< bit: 24 Security property settings */
224 uint32_t S1: 1; /*!< bit: 25 Security property settings */
225 uint32_t S2: 1; /*!< bit: 26 Security property settings */
226 uint32_t S3: 1; /*!< bit: 27 Security property settings */
227 uint32_t S4: 1; /*!< bit: 28 Security property settings */
228 uint32_t S5: 1; /*!< bit: 29 Security property settings */
229 uint32_t S6: 1; /*!< bit: 30 Security property settings */
230 uint32_t S7: 1; /*!< bit: 31 Security property settings */
231 } b; /*!< Structure Access by bit */
232 uint32_t w; /*!< Type Access by whole register */
233 } CAPR_Type;
234
235 /* CAPR Register Definitions */
236 #define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
237 #define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
238
239 #define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
240 #define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
241
242 #define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
243 #define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
244
245 #define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
246 #define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
247
248 #define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
249 #define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
250
251 #define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
252 #define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
253
254 #define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
255 #define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
256
257 #define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
258 #define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
259
260 #define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
261 #define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
262
263 #define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
264 #define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
265
266 #define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
267 #define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
268
269 #define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
270 #define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
271
272 #define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
273 #define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
274
275 #define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
276 #define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
277
278 #define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
279 #define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
280
281 #define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
282 #define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
283
284 #define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
285 #define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
286
287 #define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
288 #define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
289
290 #define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
291 #define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
292
293 #define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
294 #define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
295
296 #define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
297 #define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
298
299 #define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
300 #define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
301
302 #define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
303 #define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
304
305 #define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
306 #define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
307
308 /**
309 \brief Consortium definition for accessing control register(PACR, CR<20,0>).
310 */
311 typedef union {
312 struct {
313 uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
314 uint32_t Size: 5; /*!< bit: 1.. 5 Size of protected area */
315 uint32_t _reserved0: 1; /*!< bit: 6 Reserved */
316 uint32_t base_addr: 25; /*!< bit: 7..31 The high position of the address of a protected area */
317 } b; /*!< Structure Access by bit */
318 uint32_t w; /*!< Type Access by whole register */
319 } PACR_Type;
320
321 /* PACR Register Definitions */
322 #define PACR_BASE_ADDR_Pos 7U /*!< PACR: base_addr Position */
323 #define PACR_BASE_ADDR_Msk (0x1FFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
324
325 #define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
326 #define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
327
328 #define PACR_E_Pos 0U /*!< PACR: E Position */
329 #define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
330
331 /**
332 \brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
333 */
334 typedef union {
335 struct {
336 uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
337 uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
338 } b; /*!< Structure Access by bit */
339 uint32_t w; /*!< Type Access by whole register */
340 } PRSR_Type;
341
342 /* PRSR Register Definitions */
343 #define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
344 #define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
345
346 /**
347 \brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
348 */
349 typedef union {
350 struct {
351 uint32_t _reserved0: 4; /*!< bit: 0.. 3 Reserved */
352 uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
353 uint32_t _reserved1: 11; /*!< bit: 5..15 Reserved */
354 uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
355 } b;
356 uint32_t w;
357 } CHR_Type;
358
359 /* CHR Register Definitions */
360 #define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
361 #define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
362 #define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
363 #define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
364
365 /*@} end of group CSI_CORE */
366
367
368 /**
369 \ingroup CSI_core_register
370 \defgroup CSI_VIC Vectored Interrupt Controller (VIC)
371 \brief Type definitions for the VIC Registers
372 @{
373 */
374
375 /**
376 \brief Access to the structure of a vector interrupt controller.
377 */
378 typedef struct {
379 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
380 uint32_t RESERVED0[15U];
381 __IOM uint32_t IWER[1U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
382 uint32_t RESERVED1[15U];
383 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
384 uint32_t RESERVED2[15U];
385 __IOM uint32_t IWDR[1U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
386 uint32_t RESERVED3[15U];
387 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
388 uint32_t RESERVED4[15U];
389 __IOM uint32_t ISSR[1U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
390 uint32_t RESERVED5[15U];
391 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
392 uint32_t RESERVED6[15U];
393 __IOM uint32_t ICSR[1U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
394 uint32_t RESERVED7[15U];
395 __IOM uint32_t IABR[1U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
396 uint32_t RESERVED8[63U];
397 __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
398 uint32_t RESERVED9[504U];
399 __IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
400 __IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
401 } VIC_Type;
402
403 /*@} end of group CSI_VIC */
404
405 /**
406 \ingroup CSI_core_register
407 \defgroup CSI_SysTick System Tick Timer (CORET)
408 \brief Type definitions for the System Timer Registers.
409 @{
410 */
411
412 /**
413 \brief The data structure of the access system timer.
414 */
415 typedef struct {
416 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
417 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
418 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
419 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
420 } CORET_Type;
421
422 /* CORET Control / Status Register Definitions */
423 #define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
424 #define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
425
426 #define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
427 #define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
428
429 #define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
430 #define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
431
432 #define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
433 #define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
434
435 /* CORET Reload Register Definitions */
436 #define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
437 #define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
438
439 /* CORET Current Register Definitions */
440 #define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
441 #define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
442
443 /* CORET Calibration Register Definitions */
444 #define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
445 #define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
446
447 #define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
448 #define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
449
450 #define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
451 #define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
452
453 /*@} end of group CSI_SysTick */
454
455 /**
456 \ingroup CSI_core_register
457 \defgroup CSI_DCC
458 \brief Type definitions for the DCC.
459 @{
460 */
461
462 /**
463 \brief Access to the data structure of DCC.
464 */
465 typedef struct {
466 uint32_t RESERVED0[13U];
467 __IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
468 __IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
469 uint32_t RESERVED1[6U];
470 union {
471 __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
472 __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
473 };
474
475 } DCC_Type;
476
477 #define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
478 #define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
479
480 #define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
481 #define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
482
483 #define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
484 #define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
485
486 #define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
487 #define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
488
489 /*@} end of group CSI_DCC */
490
491 /**
492 \ingroup CSI_core_register
493 \defgroup CSI_core_bitfield Core register bit field macros
494 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
495 @{
496 */
497
498 /**
499 \brief Mask and shift a bit field value for use in a register bit range.
500 \param[in] field Name of the register bit field.
501 \param[in] value Value of the bit field.
502 \return Masked and shifted value.
503 */
504 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
505
506 /**
507 \brief Mask and shift a register value to extract a bit filed value.
508 \param[in] field Name of the register bit field.
509 \param[in] value Value of register.
510 \return Masked and shifted bit field value.
511 */
512 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
513
514 /*@} end of group CSI_core_bitfield */
515
516 /**
517 \ingroup CSI_core_register
518 \defgroup CSI_core_base Core Definitions
519 \brief Definitions for base addresses, unions, and structures.
520 @{
521 */
522
523 /* Memory mapping of CK801 Hardware */
524 #define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
525 #define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
526 #define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
527 #define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
528
529 #define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
530 #define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
531 #define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
532
533 /*@} */
534
535 /*******************************************************************************
536 * Hardware Abstraction Layer
537 Core Function Interface contains:
538 - Core VIC Functions
539 - Core CORET Functions
540 - Core Register Access Functions
541 ******************************************************************************/
542 /**
543 \defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
544 */
545
546 /* ########################## VIC functions #################################### */
547 /**
548 \ingroup CSI_Core_FunctionInterface
549 \defgroup CSI_Core_VICFunctions VIC Functions
550 \brief Functions that manage interrupts and exceptions via the VIC.
551 @{
552 */
553
554 /* The following MACROS handle generation of the register offset and byte masks */
555 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
556 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
557
558 /**
559 \brief Enable External Interrupt
560 \details Enable a device-specific interrupt in the VIC interrupt controller.
561 \param [in] IRQn External interrupt number. Value cannot be negative.
562 */
csi_vic_enable_irq(int32_t IRQn)563 __STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
564 {
565 VIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
566 }
567
568 /**
569 \brief Disable External Interrupt
570 \details Disable a device-specific interrupt in the VIC interrupt controller.
571 \param [in] IRQn External interrupt number. Value cannot be negative.
572 */
csi_vic_disable_irq(int32_t IRQn)573 __STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
574 {
575 VIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
576 }
577
578 /**
579 \brief Enable External Secure Interrupt
580 \details Enable a secure device-specific interrupt in the VIC interrupt controller.
581 \param [in] IRQn External interrupt number. Value cannot be negative.
582 */
csi_vic_enable_sirq(int32_t IRQn)583 __STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
584 {
585 VIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
586 VIC->ISSR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
587 }
588
589 /**
590 \brief Disable External Secure Interrupt
591 \details Disable a secure device-specific interrupt in the VIC interrupt controller.
592 \param [in] IRQn External interrupt number. Value cannot be negative.
593 */
csi_vic_disable_sirq(int32_t IRQn)594 __STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
595 {
596 VIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
597 VIC->ICSR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
598 }
599
600 /**
601 \brief Check Interrupt is Enabled or not
602 \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
603 \param [in] IRQn Interrupt number.
604 \return Interrput status is enabled.
605 */
csi_vic_get_enabled_irq(int32_t IRQn)606 __STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
607 {
608 return ((uint32_t)(((VIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
609 }
610
611 /**
612 \brief Check Interrupt is Pending or not
613 \details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
614 \param [in] IRQn Interrupt number.
615 \return 0 Interrupt status is not pending.
616 \return 1 Interrupt status is pending.
617 */
csi_vic_get_pending_irq(int32_t IRQn)618 __STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
619 {
620 return ((uint32_t)(((VIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
621 }
622
623 /**
624 \brief Set Pending Interrupt
625 \details Set the pending bit of an external interrupt.
626 \param [in] IRQn Interrupt number. Value cannot be negative.
627 */
csi_vic_set_pending_irq(int32_t IRQn)628 __STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
629 {
630 VIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
631 }
632
633 /**
634 \brief Clear Pending Interrupt
635 \details Clear the pending bit of an external interrupt.
636 \param [in] IRQn External interrupt number. Value cannot be negative.
637 */
csi_vic_clear_pending_irq(int32_t IRQn)638 __STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
639 {
640 VIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
641 }
642
643 /**
644 \brief Check Interrupt is Wakeup or not
645 \details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
646 \param [in] IRQn Interrupt number.
647 \return 0 Interrupt is not set as wake up interrupt.
648 \return 1 Interrupt is set as wake up interrupt.
649 */
csi_vic_get_wakeup_irq(int32_t IRQn)650 __STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
651 {
652 return ((uint32_t)(((VIC->IWER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
653 }
654
655 /**
656 \brief Set Wakeup Interrupt
657 \details Set the wake up bit of an external interrupt.
658 \param [in] IRQn Interrupt number. Value cannot be negative.
659 */
csi_vic_set_wakeup_irq(int32_t IRQn)660 __STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
661 {
662 VIC->IWER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
663 }
664
665 /**
666 \brief Clear Wake up Interrupt
667 \details Clear the wake up bit of an external interrupt.
668 \param [in] IRQn External interrupt number. Value cannot be negative.
669 */
csi_vic_clear_wakeup_irq(int32_t IRQn)670 __STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
671 {
672 VIC->IWDR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
673 }
674
675 /**
676 \brief Get Interrupt is Active or not
677 \details Read the active register in the VIC and returns the active bit for the device specific interrupt.
678 \param [in] IRQn Device specific interrupt number.
679 \return 0 Interrupt status is not active.
680 \return 1 Interrupt status is active.
681 \note IRQn must not be negative.
682 */
csi_vic_get_active(int32_t IRQn)683 __STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
684 {
685 return ((uint32_t)(((VIC->IABR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
686 }
687
688 /**
689 \brief Set Threshold register
690 \details set the threshold register in the VIC.
691 \param [in] VectThreshold specific vecter threshold.
692 \param [in] PrioThreshold specific priority threshold.
693 */
csi_vic_set_threshold(uint32_t VectThreshold,uint32_t PrioThreshold)694 __STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
695 {
696 VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x3) << 6);
697 }
698
699 /**
700 \brief Set Interrupt Priority
701 \details Set the priority of an interrupt.
702 \note The priority cannot be set for every core interrupt.
703 \param [in] IRQn Interrupt number.
704 \param [in] priority Priority to set.
705 */
csi_vic_set_prio(int32_t IRQn,uint32_t priority)706 __STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
707 {
708 VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
709 (((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
710 }
711
712 /**
713 \brief Get Interrupt Priority
714 \details Read the priority of an interrupt.
715 The interrupt number can be positive to specify an external (device specific) interrupt,
716 or negative to specify an internal (core) interrupt.
717 \param [in] IRQn Interrupt number.
718 \return Interrupt Priority.
719 Value is aligned automatically to the implemented priority bits of the microcontroller.
720 */
csi_vic_get_prio(int32_t IRQn)721 __STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
722 {
723 return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
724 }
725
726 /**
727 \brief Set interrupt handler
728 \details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
729 \param [in] IRQn Interrupt number.
730 \param [in] handler Interrupt handler.
731 */
csi_vic_set_vector(int32_t IRQn,uint32_t handler)732 __STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
733 {
734 if (IRQn >= 0 && IRQn < 32) {
735 uint32_t *vectors = (uint32_t *)__get_VBR();
736 vectors[32 + IRQn] = handler;
737 }
738 }
739
740 /**
741 \brief Get interrupt handler
742 \details Get the address of interrupt handler function.
743 \param [in] IRQn Interrupt number.
744 */
csi_vic_get_vector(int32_t IRQn)745 __STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
746 {
747 if (IRQn >= 0 && IRQn < 32) {
748 uint32_t *vectors = (uint32_t *)__get_VBR();
749 return (uint32_t)vectors[32 + IRQn];
750 }
751
752 return 0;
753 }
754
755 /*@} end of CSI_Core_VICFunctions */
756
757 /* ################################## SysTick function ############################################ */
758 /**
759 \ingroup CSI_Core_FunctionInterface
760 \defgroup CSI_Core_SysTickFunctions SysTick Functions
761 \brief Functions that configure the System.
762 @{
763 */
764
765
766 /**
767 \brief CORE timer Configuration
768 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
769 Counter is in free running mode to generate periodic interrupts.
770 \param [in] ticks Number of ticks between two interrupts.
771 \param [in] IRQn core timer Interrupt number.
772 \return 0 Function succeeded.
773 \return 1 Function failed.
774 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
775 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
776 must contain a vendor-specific implementation of this function.
777 */
csi_coret_config(uint32_t ticks,int32_t IRQn)778 __STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
779 {
780 (void)IRQn;
781
782 if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
783 return (1UL); /* Reload value impossible */
784 }
785
786 CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
787 CORET->VAL = 0UL; /* Load the CORET Counter Value */
788 CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
789 CORET_CTRL_TICKINT_Msk |
790 CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
791 return (0UL); /* Function successful */
792 }
793
794 /**
795 \brief get CORE timer reload value
796 \return CORE timer counter value.
797 */
csi_coret_get_load(void)798 __STATIC_INLINE uint32_t csi_coret_get_load(void)
799 {
800 return CORET->LOAD;
801 }
802
803 /**
804 \brief get CORE timer counter value
805 \return CORE timer counter value.
806 */
csi_coret_get_value(void)807 __STATIC_INLINE uint32_t csi_coret_get_value(void)
808 {
809 return CORET->VAL;
810 }
811
812 /**
813 \brief clean CORE timer interrupt flag
814 */
csi_coret_clear_irq(void)815 __STATIC_INLINE void csi_coret_clear_irq(void)
816 {
817 CORET->CTRL;
818 }
819
820 /*@} end of CSI_Core_SysTickFunctions */
821
822
823 /* ##################################### DCC function ########################################### */
824 /**
825 \ingroup CSI_Core_FunctionInterface
826 \defgroup CSI_core_DebugFunctions HAD Functions
827 \brief Functions that access the HAD debug interface.
828 @{
829 */
830
831 /**
832 \brief HAD Send Character
833 \details Transmits a character via the HAD channel 0, and
834 \li Just returns when no debugger is connected that has booked the output.
835 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
836 \param [in] ch Character to transmit.
837 \returns Character to transmit.
838 */
csi_had_send_char(uint32_t ch)839 __STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
840 {
841 DCC->DERJR = (uint8_t)ch;
842
843 return (ch);
844 }
845
846
847 /**
848 \brief HAD Receive Character
849 \details Inputs a character via the external variable \ref HAD_RxBuffer.
850 \return Received character.
851 \return -1 No character pending.
852 */
csi_had_receive_char(void)853 __STATIC_INLINE int32_t csi_had_receive_char(void)
854 {
855 int32_t ch = -1; /* no character available */
856
857 if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
858 ch = DCC->DERJW;
859 }
860
861 return (ch);
862 }
863
864
865 /**
866 \brief HAD Check Character
867 \details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
868 \return 0 No character available.
869 \return 1 Character available.
870 */
csi_had_check_char(void)871 __STATIC_INLINE int32_t csi_had_check_char(void)
872 {
873 return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
874 }
875
876 /*@} end of CSI_core_DebugFunctions */
877
878 /* ########################## MPU functions #################################### */
879 /**
880 \ingroup CSI_Core_FunctionInterface
881 \defgroup CSI_Core_MPUFunctions MPU Functions
882 \brief Functions that configure MPU.
883 @{
884 */
885
886 typedef enum {
887 REGION_SIZE_128B = 0x6,
888 REGION_SIZE_256B = 0x7,
889 REGION_SIZE_512B = 0x8,
890 REGION_SIZE_1KB = 0x9,
891 REGION_SIZE_2KB = 0xA,
892 REGION_SIZE_4KB = 0xB,
893 REGION_SIZE_8KB = 0xC,
894 REGION_SIZE_16KB = 0xD,
895 REGION_SIZE_32KB = 0xE,
896 REGION_SIZE_64KB = 0xF,
897 REGION_SIZE_128KB = 0x10,
898 REGION_SIZE_256KB = 0x11,
899 REGION_SIZE_512KB = 0x12,
900 REGION_SIZE_1MB = 0x13,
901 REGION_SIZE_2MB = 0x14,
902 REGION_SIZE_4MB = 0x15,
903 REGION_SIZE_8MB = 0x16,
904 REGION_SIZE_16MB = 0x17,
905 REGION_SIZE_32MB = 0x18,
906 REGION_SIZE_64MB = 0x19,
907 REGION_SIZE_128MB = 0x1A,
908 REGION_SIZE_256MB = 0x1B,
909 REGION_SIZE_512MB = 0x1C,
910 REGION_SIZE_1GB = 0x1D,
911 REGION_SIZE_2GB = 0x1E,
912 REGION_SIZE_4GB = 0x1F
913 } region_size_e;
914
915 typedef enum {
916 AP_BOTH_INACCESSIBLE = 0,
917 AP_SUPER_RW_USER_INACCESSIBLE,
918 AP_SUPER_RW_USER_RDONLY,
919 AP_BOTH_RW
920 } access_permission_e;
921
922 typedef struct {
923 uint32_t nx: 1; /* instruction fetched excution */
924 access_permission_e ap: 2; /* super user and normal user access.*/
925 uint32_t s: 1; /* security */
926 } mpu_region_attr_t;
927
928 /**
929 \brief enable mpu
930 \details
931 */
csi_mpu_enable(void)932 __STATIC_INLINE void csi_mpu_enable(void)
933 {
934 __set_CCR(__get_CCR() | CCR_MP_Msk);
935 }
936
937 /**
938 \brief disable mpu
939 \details
940 */
csi_mpu_disable(void)941 __STATIC_INLINE void csi_mpu_disable(void)
942 {
943 __set_CCR(__get_CCR() & (~CCR_MP_Msk));
944 }
945
946 /**
947 \brief configure memory protected region.
948 \details
949 \param [in] idx memory protected region (0, 1, 2, ..., 7).
950 \param [in] base_addr base address must be aligned with page size.
951 \param [in] size \ref region_size_e. memory protected region size.
952 \param [in] attr \ref region_size_t. memory protected region attribute.
953 \param [in] enable enable or disable memory protected region.
954 */
csi_mpu_config_region(uint32_t idx,uint32_t base_addr,region_size_e size,mpu_region_attr_t attr,uint32_t enable)955 __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
956 mpu_region_attr_t attr, uint32_t enable)
957 {
958 if (idx > 7) {
959 return;
960 }
961
962 CAPR_Type capr;
963 PACR_Type pacr;
964 PRSR_Type prsr;
965
966 capr.w = __get_CAPR();
967 pacr.w = __get_PACR();
968 prsr.w = __get_PRSR();
969
970 pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0x3FFFFFF);
971
972 prsr.b.RID = idx;
973 __set_PRSR(prsr.w);
974
975 if (size != REGION_SIZE_128B) {
976 pacr.w &= ~(((1u << (size -6)) - 1) << 7);
977 }
978
979 pacr.b.Size = size;
980
981 capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
982 capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
983 __set_CAPR(capr.w);
984
985 pacr.b.E = enable;
986 __set_PACR(pacr.w);
987 }
988
989 /**
990 \brief enable mpu region by idx.
991 \details
992 \param [in] idx memory protected region (0, 1, 2, ..., 7).
993 */
csi_mpu_enable_region(uint32_t idx)994 __STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
995 {
996 if (idx > 7) {
997 return;
998 }
999
1000 __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
1001 __set_PACR(__get_PACR() | PACR_E_Msk);
1002 }
1003
1004 /**
1005 \brief disable mpu region by idx.
1006 \details
1007 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1008 */
csi_mpu_disable_region(uint32_t idx)1009 __STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
1010 {
1011 if (idx > 7) {
1012 return;
1013 }
1014
1015 __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
1016 __set_PACR(__get_PACR() & (~PACR_E_Msk));
1017 }
1018
1019 /*@} end of CSI_Core_MMUFunctions */
1020
1021 /* ################################## IRQ Functions ############################################ */
1022
1023 /**
1024 \brief Save the Irq context
1025 \details save the psr result before disable irq.
1026 \param [in] irq_num External interrupt number. Value cannot be negative.
1027 */
csi_irq_save(void)1028 __STATIC_INLINE uint32_t csi_irq_save(void)
1029 {
1030 uint32_t result;
1031 result = __get_PSR();
1032 __disable_irq();
1033 return(result);
1034 }
1035
1036 /**
1037 \brief Restore the Irq context
1038 \details restore saved primask state.
1039 \param [in] irq_state psr irq state.
1040 */
csi_irq_restore(uint32_t irq_state)1041 __STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
1042 {
1043 __set_PSR(irq_state);
1044 }
1045
1046 /*@} end of IRQ Functions */
1047
1048 /**
1049 \brief System Reset
1050 \details Initiates a system reset request to reset the MCU.
1051 */
csi_system_reset(void)1052 __STATIC_INLINE void csi_system_reset(void)
1053 {
1054 CHR_Type chr;
1055
1056 chr.w = __get_CHR();
1057 #ifdef __RESET_CONST
1058 chr.b.SRST_VAL = __RESET_CONST;
1059 #else
1060 chr.b.SRST_VAL = 0xABCD;
1061 #endif
1062
1063 __DSB(); /* Ensure all outstanding memory accesses included
1064 buffered write are completed before reset */
1065 __set_CHR(chr.w);
1066
1067 __DSB(); /* Ensure completion of memory access */
1068
1069 for(;;) /* wait until reset */
1070 {
1071 __NOP();
1072 }
1073 }
1074
1075 /* ################################## Old Interfaces ############################################ */
1076
1077 /* These interfaces are deprecated */
1078 #define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
1079 #define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
1080 #define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
1081 #define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
1082 #define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
1083 #define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
1084 #define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
1085 #define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
1086 #define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
1087 #define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
1088 #define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
1089 #define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
1090 #define NVIC_SystemReset() csi_system_reset()
1091
1092 #define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
1093 #define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
1094
1095 /*@} end of Old Interfaces */
1096
1097 #ifdef __cplusplus
1098 }
1099 #endif
1100
1101 #endif /* __CORE_801_H_DEPENDANT */
1102
1103 #endif /* __CSI_GENERIC */
1104