1 /*
2 * Copyright (C) 2017-2019 Alibaba Group Holding Limited
3 */
4
5
6 /******************************************************************************
7 * @file core_804.h
8 * @brief CSI 804 Core Peripheral Access Layer Header File
9 * @version V1.0
10 * @date 02. June 2017
11 ******************************************************************************/
12
13 #ifndef __CORE_804_H_GENERIC
14 #define __CORE_804_H_GENERIC
15
16 #include <stdint.h>
17
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21
22 /*******************************************************************************
23 * CSI definitions
24 ******************************************************************************/
25 /**
26 \ingroup Ck804
27 @{
28 */
29
30 /* CSI CK804 definitions */
31 #define __CK804_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
32 #define __CK804_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
33 #define __CK804_CSI_VERSION ((__CK804_CSI_VERSION_MAIN << 16U) | \
34 __CK804_CSI_VERSION_SUB ) /*!< CSI HAL version number */
35
36 #ifndef __CK80X
37 #define __CK80X (0x03U) /*!< CK80X Core */
38 #endif
39
40 /* __FPU_USED indicates whether an FPU is used or not. */
41 #define __FPU_USED 1U
42
43 #if defined ( __GNUC__ )
44 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
45 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
46 #endif
47 #endif
48
49 #ifdef __cplusplus
50 }
51 #endif
52
53 #endif /* __CORE_CK804_H_GENERIC */
54
55 #ifndef __CSI_GENERIC
56
57 #ifndef __CORE_CK804_H_DEPENDANT
58 #define __CORE_CK804_H_DEPENDANT
59
60 #ifdef __cplusplus
61 extern "C" {
62 #endif
63
64 /* check device defines and use defaults */
65 #ifndef __CK804_REV
66 #define __CK804_REV 0x0000U
67 #endif
68
69 #ifndef __VIC_PRIO_BITS
70 #define __VIC_PRIO_BITS 2U
71 #endif
72
73 #ifndef __Vendor_SysTickConfig
74 #define __Vendor_SysTickConfig 1U
75 #endif
76
77 #ifndef __GSR_GCR_PRESENT
78 #define __GSR_GCR_PRESENT 0U
79 #endif
80
81 #ifndef __MPU_PRESENT
82 #define __MPU_PRESENT 1U
83 #endif
84
85 #ifndef __ICACHE_PRESENT
86 #define __ICACHE_PRESENT 1U
87 #endif
88
89 #ifndef __DCACHE_PRESENT
90 #define __DCACHE_PRESENT 1U
91 #endif
92
93 #include <core/csi_gcc.h>
94
95 /* IO definitions (access restrictions to peripheral registers) */
96 /**
97 \defgroup CSI_glob_defs CSI Global Defines
98
99 <strong>IO Type Qualifiers</strong> are used
100 \li to specify the access to peripheral variables.
101 \li for automatic generation of peripheral register debug information.
102 */
103 #ifdef __cplusplus
104 #define __I volatile /*!< Defines 'read only' permissions */
105 #else
106 #define __I volatile const /*!< Defines 'read only' permissions */
107 #endif
108 #define __O volatile /*!< Defines 'write only' permissions */
109 #define __IO volatile /*!< Defines 'read / write' permissions */
110
111 /* following defines should be used for structure members */
112 #define __IM volatile const /*! Defines 'read only' structure member permissions */
113 #define __OM volatile /*! Defines 'write only' structure member permissions */
114 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
115
116 /*@} end of group CK804 */
117
118 /*******************************************************************************
119 * Register Abstraction
120 Core Register contain:
121 - Core Register
122 - Core VIC Register
123 - Core Cache Register
124 - Core CoreTIM Register
125 ******************************************************************************/
126 /**
127 \defgroup CSI_core_register Defines and Type Definitions
128 \brief Type definitions and defines for CK80X processor based devices.
129 */
130
131 /**
132 \ingroup CSI_core_register
133 \defgroup CSI_CORE Status and Control Registers
134 \brief Core Register type definitions.
135 @{
136 */
137
138 /**
139 \brief Access Processor Status Register(PSR)struct definition.
140 */
141 typedef union {
142 struct {
143 uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
144 uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
145 uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
146 uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
147 uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
148 uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
149 uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
150 uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
151 uint32_t _reserved2: 1; /*!< bit: 24 Reserved */
152 uint32_t SV: 1; /*!< bit: 25 Stacked valid */
153 uint32_t SD: 1; /*!< bit: 26 Stacked dirty */
154 uint32_t SC: 1; /*!< bit: 27 Secure call bit */
155 uint32_t HS: 1; /*!< bit: 28 Hardware stacked bit */
156 uint32_t SP: 1; /*!< bit: 29 Secure pending bit */
157 uint32_t T: 1; /*!< bit: 30 TEE mode bit */
158 uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
159 } b; /*!< Structure Access by bit */
160 uint32_t w; /*!< Type Access by whole register */
161 } PSR_Type;
162
163 /* PSR Register Definitions */
164 #define PSR_S_Pos 31U /*!< PSR: S Position */
165 #define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
166
167 #define PSR_T_Pos 30U /*!< PSR: T Position */
168 #define PSR_T_Msk (1UL << PSR_T_Pos) /*!< PSR: T Mask */
169
170 #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
171 #define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
172
173 #define PSR_T_Pos 30U /*!< PSR: T Position */
174 #define PSR_T_Msk (1UL << PSR_T_Pos) /*!< PSR: T Mask */
175
176 #define PSR_MM_Pos 9U /*!< PSR: MM Position */
177 #define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
178
179 #define PSR_EE_Pos 8U /*!< PSR: EE Position */
180 #define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
181
182 #define PSR_IC_Pos 7U /*!< PSR: IC Position */
183 #define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
184
185 #define PSR_IE_Pos 6U /*!< PSR: IE Position */
186 #define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
187
188 #define PSR_C_Pos 0U /*!< PSR: C Position */
189 #define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
190
191 /**
192 \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
193 */
194 typedef union {
195 struct {
196 uint32_t MP: 1; /*!< bit: 0.. 1 memory protection settings */
197 uint32_t _reserved0: 6; /*!< bit: 2.. 6 Reserved */
198 uint32_t BE: 1; /*!< bit: 7 Endian mode */
199 uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
200 uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
201 uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
202 uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
203 } b; /*!< Structure Access by bit */
204 uint32_t w; /*!< Type Access by whole register */
205 } CCR_Type;
206
207 /* CCR Register Definitions */
208 #define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
209 #define CCR_BE_V2_Msk (0x1UL << CCR_BE_V2_Pos) /*!< CCR: BE_V2 Mask */
210
211 #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
212 #define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
213
214 #define CCR_BE_Pos 7U /*!< CCR: BE Position */
215 #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
216
217 #define CCR_MP_Pos 0U /*!< CCR: MP Position */
218 #define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
219
220 /**
221 \brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
222 */
223 typedef union {
224 struct {
225 uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
226 uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
227 uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
228 uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
229 uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
230 uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
231 uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
232 uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
233 uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
234 uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
235 uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
236 uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
237 uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
238 uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
239 uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
240 uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
241 uint32_t S0: 1; /*!< bit: 24 Security property settings */
242 uint32_t S1: 1; /*!< bit: 25 Security property settings */
243 uint32_t S2: 1; /*!< bit: 26 Security property settings */
244 uint32_t S3: 1; /*!< bit: 27 Security property settings */
245 uint32_t S4: 1; /*!< bit: 28 Security property settings */
246 uint32_t S5: 1; /*!< bit: 29 Security property settings */
247 uint32_t S6: 1; /*!< bit: 30 Security property settings */
248 uint32_t S7: 1; /*!< bit: 31 Security property settings */
249 } b; /*!< Structure Access by bit */
250 uint32_t w; /*!< Type Access by whole register */
251 } CAPR_Type;
252
253 /* CAPR Register Definitions */
254 #define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
255 #define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
256
257 #define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
258 #define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
259
260 #define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
261 #define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
262
263 #define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
264 #define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
265
266 #define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
267 #define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
268
269 #define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
270 #define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
271
272 #define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
273 #define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
274
275 #define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
276 #define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
277
278 #define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
279 #define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
280
281 #define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
282 #define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
283
284 #define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
285 #define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
286
287 #define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
288 #define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
289
290 #define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
291 #define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
292
293 #define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
294 #define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
295
296 #define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
297 #define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
298
299 #define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
300 #define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
301
302 #define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
303 #define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
304
305 #define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
306 #define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
307
308 #define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
309 #define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
310
311 #define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
312 #define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
313
314 #define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
315 #define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
316
317 #define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
318 #define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
319
320 #define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
321 #define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
322
323 #define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
324 #define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
325
326 /**
327 \brief Consortium definition for accessing control register(PACR, CR<20,0>).
328 */
329 typedef union {
330 struct {
331 uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
332 uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
333 uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
334 uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
335 } b; /*!< Structure Access by bit */
336 uint32_t w; /*!< Type Access by whole register */
337 } PACR_Type;
338
339 /* PACR Register Definitions */
340 #define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
341 #define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
342
343 #define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
344 #define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
345
346 #define PACR_E_Pos 0U /*!< PACR: E Position */
347 #define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
348
349 /**
350 \brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
351 */
352 typedef union {
353 struct {
354 uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
355 uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
356 } b; /*!< Structure Access by bit */
357 uint32_t w; /*!< Type Access by whole register */
358 } PRSR_Type;
359
360 /* PRSR Register Definitions */
361 #define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
362 #define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
363
364 /**
365 \brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
366 */
367 typedef union {
368 struct {
369 uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
370 uint32_t BE: 1; /*!< bit: 1 System bus support burst transer */
371 uint32_t IPE: 1; /*!< bit: 2 Instruction prefetch function enable */
372 uint32_t RPE: 1; /*!< bit: 3 Function return instruction RTS will speculate execution */
373 uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
374 uint32_t _reserved1: 9; /*!< bit: 5..13 Reserved */
375 uint32_t ISE: 1; /*!< bit: 14 Interrupt SP enable */
376 uint32_t HS_EXP: 1; /*!< bit: 15 Exception bit for TEE world switch */
377 uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
378 } b;
379 uint32_t w;
380 } CHR_Type;
381
382 /* CHR Register Definitions */
383 #define CHR_BE_Pos 1U /*!< CHR: BE Position */
384 #define CHR_BE_Msk (1UL << CHR_BE_Pos) /*!< CHR: BE Mask */
385 #define CHR_IPE_Pos 1U /*!< CHR: IPE Position */
386 #define CHR_IPE_Msk (1UL << CHR_IPE_Pos) /*!< CHR: IPE Mask */
387 #define CHR_RPE_Pos 1U /*!< CHR: RPE Position */
388 #define CHR_RPE_Msk (1UL << CHR_RPE_Pos) /*!< CHR: RPE Mask */
389 #define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
390 #define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
391 #define CHR_ISE_Pos 14U /*!< CHR: ISE Position */
392 #define CHR_ISE_Msk (0x1UL << CHR_ISE_Pos) /*!< CHR: ISE Mask */
393 #define CHR_HS_EXP_Pos 15U /*!< CHR: HS_EXP Position */
394 #define CHR_HS_EXP_Msk (0x1UL << CHR_HS_EXP_Pos) /*!< CHR: HS_EXP Mask */
395 #define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
396 #define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
397
398 /*@} end of group CSI_CORE */
399
400
401 /**
402 \ingroup CSI_core_register
403 \defgroup CSI_VIC Vectored Interrupt Controller (VIC)
404 \brief Type definitions for the VIC Registers
405 @{
406 */
407
408 /**
409 \brief Access to the structure of a vector interrupt controller.
410 */
411 typedef struct {
412 __IOM uint32_t ISER[4U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
413 uint32_t RESERVED0[12U];
414 __IOM uint32_t IWER[4U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
415 uint32_t RESERVED1[12U];
416 __IOM uint32_t ICER[4U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
417 uint32_t RESERVED2[12U];
418 __IOM uint32_t IWDR[4U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
419 uint32_t RESERVED3[12U];
420 __IOM uint32_t ISPR[4U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
421 uint32_t RESERVED4[12U];
422 __IOM uint32_t ISSR[4U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
423 uint32_t RESERVED5[12U];
424 __IOM uint32_t ICPR[4U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
425 uint32_t RESERVED6[12U];
426 __IOM uint32_t ICSR[4U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
427 uint32_t RESERVED7[12U];
428 __IOM uint32_t IABR[4U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
429 uint32_t RESERVED8[60U];
430 __IOM uint32_t IPR[32U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
431 uint32_t RESERVED9[480U];
432 __IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
433 __IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
434 __IOM uint32_t TSPEND; /*!< Offset: 0xB08 (R/W) Task pending register */
435 __IOM uint32_t TSABR; /*!< Offset: 0xB0c (R/W) Tspend acknowledge register */
436 __IOM uint32_t TSPR; /*!< Offset: 0xB10 (R/W) Tspend priority register */
437 } VIC_Type;
438
439 /*@} end of group CSI_VIC */
440
441 /**
442 \ingroup CSI_core_register
443 \defgroup CSI_CACHE
444 \brief Type definitions for the cache Registers
445 @{
446 */
447
448 /**
449 \brief On chip cache structure.
450 */
451 typedef struct
452 {
453 __IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
454 __IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
455 __IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
456 uint32_t RSERVED0[1015U];
457 __IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
458 __IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
459 __IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
460 } CACHE_Type;
461
462 /* CACHE Register Definitions */
463 #define CACHE_CER_EN_Pos 0U /*!< CACHE CER: EN Position */
464 #define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /*!< CACHE CER: EN Mask */
465
466 #define CACHE_CER_CFIG_Pos 1U /*!< CACHE CER: CFIG Position */
467 #define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /*!< CACHE CER: CFIG Mask */
468
469 #define CACHE_CER_WB_Pos 2U /*!< CACHE CER: WB Position */
470 #define CACHE_CER_WB_Msk (0x1UL << CACHE_CER_WB_Pos) /*!< CACHE CER: WB Mask */
471
472 #define CACHE_CER_DCW_Pos 4U /*!< CACHE CER: DCW Position */
473 #define CACHE_CER_DCW_Msk (0x1UL << CACHE_CER_DCW_Pos) /*!< CACHE CER: DCW Mask */
474
475 #define CACHE_CER_WA_Pos 5U /*!< CACHE CER: WA Position */
476 #define CACHE_CER_WA_Msk (0x1UL << CACHE_CER_WA_Pos) /*!< CACHE CER: WA Mask */
477
478 #define CACHE_CIR_INV_ALL_Pos 0U /*!< CACHE CIR: INV_ALL Position */
479 #define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /*!< CACHE CIR: INV_ALL Mask */
480
481 #define CACHE_CIR_INV_ONE_Pos 1U /*!< CACHE CIR: INV_ONE Position */
482 #define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /*!< CACHE CIR: INV_ONE Mask */
483
484 #define CACHE_CIR_CLR_ALL_Pos 2U /*!< CACHE CIR: CLR_ALL Position */
485 #define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /*!< CACHE CIR: CLR_ALL Mask */
486
487 #define CACHE_CIR_CLR_ONE_Pos 3U /*!< CACHE CIR: CLR_ONE Position */
488 #define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /*!< CACHE CIR: CLR_ONE Mask */
489
490 #define CACHE_CIR_INV_ADDR_Pos 4U /*!< CACHE CIR: INV_ADDR Position */
491 #define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos) /*!< CACHE CIR: INV_ADDR Mask */
492
493 #define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
494 #define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
495
496 #define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
497 #define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
498
499 #define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
500 #define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
501
502 #define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
503 #define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
504
505 #define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
506 #define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
507
508 #define CACHE_CRCR_4K 0xB /* 01011 */
509 #define CACHE_CRCR_8K 0xC /* 01100 */
510 #define CACHE_CRCR_16K 0xD /* 01101 */
511 #define CACHE_CRCR_32K 0xE /* 01110 */
512 #define CACHE_CRCR_64K 0xF /* 01111 */
513 #define CACHE_CRCR_128K 0x10 /* 10000 */
514 #define CACHE_CRCR_256K 0x11 /* 10001 */
515 #define CACHE_CRCR_512K 0x12 /* 10010 */
516 #define CACHE_CRCR_1M 0x13 /* 10011 */
517 #define CACHE_CRCR_2M 0x14 /* 10100 */
518 #define CACHE_CRCR_4M 0x15 /* 10101 */
519 #define CACHE_CRCR_8M 0x16 /* 10110 */
520 #define CACHE_CRCR_16M 0x17 /* 10111 */
521 #define CACHE_CRCR_32M 0x18 /* 11000 */
522 #define CACHE_CRCR_64M 0x19 /* 11001 */
523 #define CACHE_CRCR_128M 0x1A /* 11010 */
524 #define CACHE_CRCR_256M 0x1B /* 11011 */
525 #define CACHE_CRCR_512M 0x1C /* 11100 */
526 #define CACHE_CRCR_1G 0x1D /* 11101 */
527 #define CACHE_CRCR_2G 0x1E /* 11110 */
528 #define CACHE_CRCR_4G 0x1F /* 11111 */
529
530 /*@} end of group CSI_CACHE */
531
532
533 /**
534 \ingroup CSI_core_register
535 \defgroup CSI_SysTick System Tick Timer (CORET)
536 \brief Type definitions for the System Timer Registers.
537 @{
538 */
539
540 /**
541 \brief The data structure of the access system timer.
542 */
543 typedef struct {
544 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
545 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
546 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
547 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
548 } CORET_Type;
549
550 /* CORET Control / Status Register Definitions */
551 #define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
552 #define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
553
554 #define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
555 #define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
556
557 #define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
558 #define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
559
560 #define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
561 #define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
562
563 /* CORET Reload Register Definitions */
564 #define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
565 #define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
566
567 /* CORET Current Register Definitions */
568 #define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
569 #define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
570
571 /* CORET Calibration Register Definitions */
572 #define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
573 #define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
574
575 #define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
576 #define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
577
578 #define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
579 #define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
580
581 /*@} end of group CSI_SysTick */
582
583 /**
584 \ingroup CSI_core_register
585 \defgroup CSI_DCC
586 \brief Type definitions for the DCC.
587 @{
588 */
589
590 /**
591 \brief Access to the data structure of DCC.
592 */
593 typedef struct {
594 uint32_t RESERVED0[13U];
595 __IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
596 __IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
597 uint32_t RESERVED1[6U];
598 union {
599 __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
600 __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
601 };
602
603 } DCC_Type;
604
605 #define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
606 #define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
607
608 #define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
609 #define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
610
611 #define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
612 #define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
613
614 #define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
615 #define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
616
617 /*@} end of group CSI_DCC */
618
619 /**
620 \ingroup CSI_core_register
621 \defgroup CSI_core_bitfield Core register bit field macros
622 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
623 @{
624 */
625
626 /**
627 \brief Mask and shift a bit field value for use in a register bit range.
628 \param[in] field Name of the register bit field.
629 \param[in] value Value of the bit field.
630 \return Masked and shifted value.
631 */
632 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
633
634 /**
635 \brief Mask and shift a register value to extract a bit filed value.
636 \param[in] field Name of the register bit field.
637 \param[in] value Value of register.
638 \return Masked and shifted bit field value.
639 */
640 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
641
642 /*@} end of group CSI_core_bitfield */
643
644 /**
645 \ingroup CSI_core_register
646 \defgroup CSI_core_base Core Definitions
647 \brief Definitions for base addresses, unions, and structures.
648 @{
649 */
650
651 /* Memory mapping of CK804 Hardware */
652 #define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
653 #define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
654 #define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
655 #define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
656 #define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
657
658 #define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
659 #define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
660 #define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
661 #define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
662
663 /*@} */
664
665
666 /*******************************************************************************
667 * Hardware Abstraction Layer
668 Core Function Interface contains:
669 - Core VIC Functions
670 - Core CORET Functions
671 - Core Register Access Functions
672 ******************************************************************************/
673 /**
674 \defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
675 */
676
677 /* ########################## VIC functions #################################### */
678 /**
679 \ingroup CSI_Core_FunctionInterface
680 \defgroup CSI_Core_VICFunctions VIC Functions
681 \brief Functions that manage interrupts and exceptions via the VIC.
682 @{
683 */
684
685 /* The following MACROS handle generation of the register offset and byte masks */
686 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
687 #define _IR_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
688 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
689
690 /**
691 \brief Enable External Interrupt
692 \details Enable a device-specific interrupt in the VIC interrupt controller.
693 \param [in] IRQn External interrupt number. Value cannot be negative.
694 */
csi_vic_enable_irq(int32_t IRQn)695 __STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
696 {
697 IRQn &= 0x7FUL;
698
699 VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
700 }
701
702 /**
703 \brief Disable External Interrupt
704 \details Disable a device-specific interrupt in the VIC interrupt controller.
705 \param [in] IRQn External interrupt number. Value cannot be negative.
706 */
csi_vic_disable_irq(int32_t IRQn)707 __STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
708 {
709 IRQn &= 0x7FUL;
710
711 VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
712 }
713
714 /**
715 \brief Enable External Secure Interrupt
716 \details Enable a secure device-specific interrupt in the VIC interrupt controller.
717 \param [in] IRQn External interrupt number. Value cannot be negative.
718 */
csi_vic_enable_sirq(int32_t IRQn)719 __STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
720 {
721 IRQn &= 0x7FUL;
722
723 VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
724 VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
725 }
726
727 /**
728 \brief Disable External Secure Interrupt
729 \details Disable a secure device-specific interrupt in the VIC interrupt controller.
730 \param [in] IRQn External interrupt number. Value cannot be negative.
731 */
csi_vic_disable_sirq(int32_t IRQn)732 __STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
733 {
734 IRQn &= 0x7FUL;
735
736 VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
737 VIC->ICSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
738 }
739
740 /**
741 \brief Check Interrupt is Enabled or not
742 \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
743 \param [in] IRQn Interrupt number.
744 \return 0 Interrupt status is not enabled.
745 \return 1 Interrupt status is enabled.
746 */
csi_vic_get_enabled_irq(int32_t IRQn)747 __STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
748 {
749 IRQn &= 0x7FUL;
750
751 return ((uint32_t)(((VIC->ISER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
752 }
753
754 /**
755 \brief Check Interrupt is Pending or not
756 \details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
757 \param [in] IRQn Interrupt number.
758 \return 0 Interrupt status is not pending.
759 \return 1 Interrupt status is pending.
760 */
csi_vic_get_pending_irq(int32_t IRQn)761 __STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
762 {
763 IRQn &= 0x7FUL;
764
765 return ((uint32_t)(((VIC->ISPR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
766 }
767
768 /**
769 \brief Set Pending Interrupt
770 \details Set the pending bit of an external interrupt.
771 \param [in] IRQn Interrupt number. Value cannot be negative.
772 */
csi_vic_set_pending_irq(int32_t IRQn)773 __STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
774 {
775 IRQn &= 0x7FUL;
776
777 VIC->ISPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
778 }
779
780 /**
781 \brief Clear Pending Interrupt
782 \details Clear the pending bit of an external interrupt.
783 \param [in] IRQn External interrupt number. Value cannot be negative.
784 */
csi_vic_clear_pending_irq(int32_t IRQn)785 __STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
786 {
787 IRQn &= 0x7FUL;
788
789 VIC->ICPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
790 }
791
792 /**
793 \brief Check Interrupt is Wakeup or not
794 \details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
795 \param [in] IRQn Interrupt number.
796 \return 0 Interrupt is not set as wake up interrupt.
797 \return 1 Interrupt is set as wake up interrupt.
798 */
csi_vic_get_wakeup_irq(int32_t IRQn)799 __STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
800 {
801 IRQn &= 0x7FUL;
802
803 return ((uint32_t)(((VIC->IWER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
804 }
805
806 /**
807 \brief Set Wake up Interrupt
808 \details Set the wake up bit of an external interrupt.
809 \param [in] IRQn Interrupt number. Value cannot be negative.
810 */
csi_vic_set_wakeup_irq(int32_t IRQn)811 __STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
812 {
813 IRQn &= 0x7FUL;
814
815 VIC->IWER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
816 }
817
818 /**
819 \brief Clear Wake up Interrupt
820 \details Clear the wake up bit of an external interrupt.
821 \param [in] IRQn External interrupt number. Value cannot be negative.
822 */
csi_vic_clear_wakeup_irq(int32_t IRQn)823 __STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
824 {
825 IRQn &= 0x7FUL;
826
827 VIC->IWDR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
828 }
829
830 /**
831 \brief Get Interrupt is Active or not
832 \details Read the active register in the VIC and returns the active bit for the device specific interrupt.
833 \param [in] IRQn Device specific interrupt number.
834 \return 0 Interrupt status is not active.
835 \return 1 Interrupt status is active.
836 \note IRQn must not be negative.
837 */
csi_vic_get_active(int32_t IRQn)838 __STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
839 {
840 IRQn &= 0x7FUL;
841
842 return ((uint32_t)(((VIC->IABR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
843 }
844
845 /**
846 \brief Set Threshold register
847 \details set the threshold register in the VIC.
848 \param [in] VectThreshold specific vector threshold.
849 \param [in] PrioThreshold specific priority threshold.
850 */
csi_vic_set_threshold(uint32_t VectThreshold,uint32_t PrioThreshold)851 __STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
852 {
853 VectThreshold &= 0x7FUL;
854
855 if (VectThreshold <= 31) {
856 VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x3) << 6);
857 }
858
859 if (VectThreshold > 31 && VectThreshold < 96) {
860 VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x7) << 5);
861 }
862
863 if (VectThreshold > 95) {
864 VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0xF) << 4);
865 }
866 }
867
868 /**
869 \brief Set Interrupt Priority
870 \details Set the priority of an interrupt.
871 \note The priority cannot be set for every core interrupt.
872 \param [in] IRQn Interrupt number.
873 \param [in] priority Priority to set.
874 */
csi_vic_set_prio(int32_t IRQn,uint32_t priority)875 __STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
876 {
877 VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
878 (((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
879 }
880
881 /**
882 \brief Get Interrupt Priority
883 \details Read the priority of an interrupt.
884 The interrupt number can be positive to specify an external (device specific) interrupt,
885 or negative to specify an internal (core) interrupt.
886 \param [in] IRQn Interrupt number.
887 \return Interrupt Priority.
888 Value is aligned automatically to the implemented priority bits of the microcontroller.
889 */
csi_vic_get_prio(int32_t IRQn)890 __STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
891 {
892 return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
893 }
894
895 /**
896 \brief Set interrupt handler
897 \details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
898 \param [in] IRQn Interrupt number.
899 \param [in] handler Interrupt handler.
900 */
csi_vic_set_vector(int32_t IRQn,uint32_t handler)901 __STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
902 {
903 if (IRQn >= 0 && IRQn < 128) {
904 uint32_t *vectors = (uint32_t *)__get_VBR();
905 vectors[32 + IRQn] = handler;
906 }
907 }
908
909 /**
910 \brief Get interrupt handler
911 \details Get the address of interrupt handler function.
912 \param [in] IRQn Interrupt number.
913 */
csi_vic_get_vector(int32_t IRQn)914 __STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
915 {
916 if (IRQn >= 0 && IRQn < 128) {
917 uint32_t *vectors = (uint32_t *)__get_VBR();
918 return (uint32_t)vectors[32 + IRQn];
919 }
920
921 return 0;
922 }
923
924 /*@} end of CSI_Core_VICFunctions */
925
926 /* ################################## SysTick function ############################################ */
927 /**
928 \ingroup CSI_Core_FunctionInterface
929 \defgroup CSI_Core_SysTickFunctions SysTick Functions
930 \brief Functions that configure the System.
931 @{
932 */
933
934
935 /**
936 \brief CORE timer Configuration
937 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
938 Counter is in free running mode to generate periodic interrupts.
939 \param [in] ticks Number of ticks between two interrupts.
940 \param [in] IRQn core timer Interrupt number.
941 \return 0 Function succeeded.
942 \return 1 Function failed.
943 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
944 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
945 must contain a vendor-specific implementation of this function.
946 */
csi_coret_config(uint32_t ticks,int32_t IRQn)947 __STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
948 {
949 if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
950 return (1UL); /* Reload value impossible */
951 }
952
953 CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
954 CORET->VAL = 0UL; /* Load the CORET Counter Value */
955 CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
956 CORET_CTRL_TICKINT_Msk |
957 CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
958 return (0UL); /* Function successful */
959 }
960
961 /**
962 \brief get CORE timer reload value
963 \return CORE timer counter value.
964 */
csi_coret_get_load(void)965 __STATIC_INLINE uint32_t csi_coret_get_load(void)
966 {
967 return CORET->LOAD;
968 }
969
970 /**
971 \brief get CORE timer counter value
972 \return CORE timer counter value.
973 */
csi_coret_get_value(void)974 __STATIC_INLINE uint32_t csi_coret_get_value(void)
975 {
976 return CORET->VAL;
977 }
978
979 /**
980 \brief clean CORE timer interrupt flag
981 */
csi_coret_clear_irq(void)982 __STATIC_INLINE void csi_coret_clear_irq(void)
983 {
984 CORET->CTRL;
985 }
986
987 /*@} end of CSI_Core_SysTickFunctions */
988
989 /* ##################################### DCC function ########################################### */
990 /**
991 \ingroup CSI_Core_FunctionInterface
992 \defgroup CSI_core_DebugFunctions HAD Functions
993 \brief Functions that access the HAD debug interface.
994 @{
995 */
996
997 /**
998 \brief HAD Send Character
999 \details Transmits a character via the HAD channel 0, and
1000 \li Just returns when no debugger is connected that has booked the output.
1001 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1002 \param [in] ch Character to transmit.
1003 \returns Character to transmit.
1004 */
csi_had_send_char(uint32_t ch)1005 __STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
1006 {
1007 DCC->DERJR = (uint8_t)ch;
1008
1009 return (ch);
1010 }
1011
1012
1013 /**
1014 \brief HAD Receive Character
1015 \details Inputs a character via the external variable \ref HAD_RxBuffer.
1016 \return Received character.
1017 \return -1 No character pending.
1018 */
csi_had_receive_char(void)1019 __STATIC_INLINE int32_t csi_had_receive_char(void)
1020 {
1021 int32_t ch = -1; /* no character available */
1022
1023 if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
1024 ch = DCC->DERJW;
1025 }
1026
1027 return (ch);
1028 }
1029
1030
1031 /**
1032 \brief HAD Check Character
1033 \details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
1034 \return 0 No character available.
1035 \return 1 Character available.
1036 */
csi_had_check_char(void)1037 __STATIC_INLINE int32_t csi_had_check_char(void)
1038 {
1039 return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
1040 }
1041
1042 /*@} end of CSI_core_DebugFunctions */
1043
1044 /* ########################## Cache functions #################################### */
1045 /**
1046 \ingroup CSI_Core_FunctionInterface
1047 \defgroup CSI_Core_CacheFunctions Cache Functions
1048 \brief Functions that configure Instruction and Data cache.
1049 @{
1050 */
1051
1052 /**
1053 \brief Enable I-Cache
1054 \details Turns on I-Cache
1055 */
csi_icache_enable(void)1056 __STATIC_INLINE void csi_icache_enable (void)
1057 {
1058 #if (__ICACHE_PRESENT == 1U)
1059 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1060 CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
1061 #endif
1062 }
1063
1064
1065 /**
1066 \brief Disable I-Cache
1067 \details Turns off I-Cache
1068 */
csi_icache_disable(void)1069 __STATIC_INLINE void csi_icache_disable (void)
1070 {
1071 #if (__ICACHE_PRESENT == 1U)
1072 CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
1073 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1074 #endif
1075 }
1076
1077
1078 /**
1079 \brief Invalidate I-Cache
1080 \details Invalidates I-Cache
1081 */
csi_icache_invalid(void)1082 __STATIC_INLINE void csi_icache_invalid (void)
1083 {
1084 #if (__ICACHE_PRESENT == 1U)
1085 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1086 #endif
1087 }
1088
1089
1090 /**
1091 \brief Enable D-Cache
1092 \details Turns on D-Cache
1093 \note I-Cache also turns on.
1094 */
csi_dcache_enable(void)1095 __STATIC_INLINE void csi_dcache_enable (void)
1096 {
1097 #if (__DCACHE_PRESENT == 1U)
1098 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1099 CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_WB_Msk | CACHE_CER_DCW_Msk) & (~CACHE_CER_CFIG_Msk); /* enable all Cache */
1100 #endif
1101 }
1102
1103
1104 /**
1105 \brief Disable D-Cache
1106 \details Turns off D-Cache
1107 \note I-Cache also turns off.
1108 */
csi_dcache_disable(void)1109 __STATIC_INLINE void csi_dcache_disable (void)
1110 {
1111 #if (__DCACHE_PRESENT == 1U)
1112 CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
1113 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1114 #endif
1115 }
1116
1117
1118 /**
1119 \brief Invalidate D-Cache
1120 \details Invalidates D-Cache
1121 \note I-Cache also invalid
1122 */
csi_dcache_invalid(void)1123 __STATIC_INLINE void csi_dcache_invalid (void)
1124 {
1125 #if (__DCACHE_PRESENT == 1U)
1126 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1127 #endif
1128 }
1129
1130
1131 /**
1132 \brief Clean D-Cache
1133 \details Cleans D-Cache
1134 \note I-Cache also cleans
1135 */
csi_dcache_clean(void)1136 __STATIC_INLINE void csi_dcache_clean (void)
1137 {
1138 #if (__DCACHE_PRESENT == 1U)
1139 CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
1140 #endif
1141 }
1142
1143
1144 /**
1145 \brief Clean & Invalidate D-Cache
1146 \details Cleans and Invalidates D-Cache
1147 \note I-Cache also flush.
1148 */
csi_dcache_clean_invalid(void)1149 __STATIC_INLINE void csi_dcache_clean_invalid (void)
1150 {
1151 #if (__DCACHE_PRESENT == 1U)
1152 CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
1153 #endif
1154 }
1155
1156
1157 /**
1158 \brief D-Cache Invalidate by address
1159 \details Invalidates D-Cache for the given address
1160 \param[in] addr address (aligned to 16-byte boundary)
1161 \param[in] dsize size of memory block (aligned to 16-byte boundary)
1162 */
1163
csi_dcache_invalid_range(uint32_t * addr,int32_t dsize)1164 __STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
1165 {
1166 #if (__DCACHE_PRESENT == 1U)
1167 int32_t op_size = dsize + (uint32_t)addr % 16;
1168 uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
1169 int32_t linesize = 16;
1170
1171 op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
1172
1173 while (op_size >= 128) {
1174 CACHE->CIR = op_addr;
1175 op_addr += linesize;
1176 CACHE->CIR = op_addr;
1177 op_addr += linesize;
1178 CACHE->CIR = op_addr;
1179 op_addr += linesize;
1180 CACHE->CIR = op_addr;
1181 op_addr += linesize;
1182 CACHE->CIR = op_addr;
1183 op_addr += linesize;
1184 CACHE->CIR = op_addr;
1185 op_addr += linesize;
1186 CACHE->CIR = op_addr;
1187 op_addr += linesize;
1188 CACHE->CIR = op_addr;
1189 op_addr += linesize;
1190
1191 op_size -= 128;
1192 }
1193
1194 while (op_size > 0) {
1195 CACHE->CIR = op_addr;
1196 op_addr += linesize;
1197 op_size -= linesize;
1198 }
1199 #endif
1200 }
1201
1202
1203 /**
1204 \brief D-Cache Clean by address
1205 \details Cleans D-Cache for the given address
1206 \param[in] addr address (aligned to 16-byte boundary)
1207 \param[in] dsize size of memory block (aligned to 16-byte boundary)
1208 */
csi_dcache_clean_range(uint32_t * addr,int32_t dsize)1209 __STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
1210 {
1211 #if (__DCACHE_PRESENT == 1)
1212 int32_t op_size = dsize + (uint32_t)addr % 16;
1213 uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
1214 int32_t linesize = 16;
1215
1216 op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
1217
1218 while (op_size >= 128) {
1219 CACHE->CIR = op_addr;
1220 op_addr += linesize;
1221 CACHE->CIR = op_addr;
1222 op_addr += linesize;
1223 CACHE->CIR = op_addr;
1224 op_addr += linesize;
1225 CACHE->CIR = op_addr;
1226 op_addr += linesize;
1227 CACHE->CIR = op_addr;
1228 op_addr += linesize;
1229 CACHE->CIR = op_addr;
1230 op_addr += linesize;
1231 CACHE->CIR = op_addr;
1232 op_addr += linesize;
1233 CACHE->CIR = op_addr;
1234 op_addr += linesize;
1235
1236 op_size -= 128;
1237 }
1238
1239 while (op_size > 0) {
1240 CACHE->CIR = op_addr;
1241 op_addr += linesize;
1242 op_size -= linesize;
1243 }
1244 #endif
1245 }
1246
1247
1248 /**
1249 \brief D-Cache Clean and Invalidate by address
1250 \details Cleans and invalidates D_Cache for the given address
1251 \param[in] addr address (aligned to 16-byte boundary)
1252 \param[in] dsize size of memory block (aligned to 16-byte boundary)
1253 */
csi_dcache_clean_invalid_range(uint32_t * addr,int32_t dsize)1254 __STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
1255 {
1256 #if (__DCACHE_PRESENT == 1U)
1257 int32_t op_size = dsize + (uint32_t)addr % 16;
1258 uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
1259 int32_t linesize = 16;
1260
1261 op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
1262
1263 while (op_size >= 128) {
1264 CACHE->CIR = op_addr;
1265 op_addr += linesize;
1266 CACHE->CIR = op_addr;
1267 op_addr += linesize;
1268 CACHE->CIR = op_addr;
1269 op_addr += linesize;
1270 CACHE->CIR = op_addr;
1271 op_addr += linesize;
1272 CACHE->CIR = op_addr;
1273 op_addr += linesize;
1274 CACHE->CIR = op_addr;
1275 op_addr += linesize;
1276 CACHE->CIR = op_addr;
1277 op_addr += linesize;
1278 CACHE->CIR = op_addr;
1279 op_addr += linesize;
1280
1281 op_size -= 128;
1282 }
1283
1284 while (op_size > 0) {
1285 CACHE->CIR = op_addr;
1286 op_addr += linesize;
1287 op_size -= linesize;
1288 }
1289 #endif
1290 }
1291
1292 /**
1293 \brief setup cacheable range Cache
1294 \details setup Cache range
1295 */
csi_cache_set_range(uint32_t index,uint32_t baseAddr,uint32_t size,uint32_t enable)1296 __STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
1297 {
1298 CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
1299 (_VAL2FLD(CACHE_CRCR_SIZE, size)) |
1300 (_VAL2FLD(CACHE_CRCR_EN, enable)));
1301 }
1302
1303 /**
1304 \brief Enable cache profile
1305 \details Turns on Cache profile
1306 */
csi_cache_enable_profile(void)1307 __STATIC_INLINE void csi_cache_enable_profile (void)
1308 {
1309 CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
1310 }
1311
1312 /**
1313 \brief Disable cache profile
1314 \details Turns off Cache profile
1315 */
csi_cache_disable_profile(void)1316 __STATIC_INLINE void csi_cache_disable_profile (void)
1317 {
1318 CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
1319 }
1320
1321 /**
1322 \brief Reset cache profile
1323 \details Reset Cache profile
1324 */
csi_cache_reset_profile(void)1325 __STATIC_INLINE void csi_cache_reset_profile (void)
1326 {
1327 CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
1328 }
1329
1330 /**
1331 \brief cache access times
1332 \details Cache access times
1333 \note every 256 access add 1.
1334 \return cache access times, actual times should be multiplied by 256
1335 */
csi_cache_get_access_time(void)1336 __STATIC_INLINE uint32_t csi_cache_get_access_time (void)
1337 {
1338 return CACHE->CPFATR;
1339 }
1340
1341 /**
1342 \brief cache miss times
1343 \details Cache miss times
1344 \note every 256 miss add 1.
1345 \return cache miss times, actual times should be multiplied by 256
1346 */
csi_cache_get_miss_time(void)1347 __STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
1348 {
1349 return CACHE->CPFMTR;
1350 }
1351
1352 /*@} end of CSI_Core_CacheFunctions */
1353
1354 /* ########################## MPU functions #################################### */
1355 /**
1356 \ingroup CSI_Core_FunctionInterface
1357 \defgroup CSI_Core_MPUFunctions MPU Functions
1358 \brief Functions that configure MPU.
1359 @{
1360 */
1361
1362 typedef enum {
1363 REGION_SIZE_4KB = 0xB,
1364 REGION_SIZE_8KB = 0xC,
1365 REGION_SIZE_16KB = 0xD,
1366 REGION_SIZE_32KB = 0xE,
1367 REGION_SIZE_64KB = 0xF,
1368 REGION_SIZE_128KB = 0x10,
1369 REGION_SIZE_256KB = 0x11,
1370 REGION_SIZE_512KB = 0x12,
1371 REGION_SIZE_1MB = 0x13,
1372 REGION_SIZE_2MB = 0x14,
1373 REGION_SIZE_4MB = 0x15,
1374 REGION_SIZE_8MB = 0x16,
1375 REGION_SIZE_16MB = 0x17,
1376 REGION_SIZE_32MB = 0x18,
1377 REGION_SIZE_64MB = 0x19,
1378 REGION_SIZE_128MB = 0x1A,
1379 REGION_SIZE_256MB = 0x1B,
1380 REGION_SIZE_512MB = 0x1C,
1381 REGION_SIZE_1GB = 0x1D,
1382 REGION_SIZE_2GB = 0x1E,
1383 REGION_SIZE_4GB = 0x1F
1384 } region_size_e;
1385
1386 typedef enum {
1387 AP_BOTH_INACCESSIBLE = 0,
1388 AP_SUPER_RW_USER_INACCESSIBLE,
1389 AP_SUPER_RW_USER_RDONLY,
1390 AP_BOTH_RW
1391 } access_permission_e;
1392
1393 typedef struct {
1394 uint32_t nx: 1; /* instruction fetched excution */
1395 access_permission_e ap: 2; /* super user and normal user access.*/
1396 uint32_t s: 1; /* security */
1397 } mpu_region_attr_t;
1398
1399 /**
1400 \brief enable mpu.
1401 \details
1402 */
csi_mpu_enable(void)1403 __STATIC_INLINE void csi_mpu_enable(void)
1404 {
1405 __set_CCR(__get_CCR() | CCR_MP_Msk);
1406 }
1407
1408 /**
1409 \brief disable mpu.
1410 \details
1411 */
csi_mpu_disable(void)1412 __STATIC_INLINE void csi_mpu_disable(void)
1413 {
1414 __set_CCR(__get_CCR() & (~CCR_MP_Msk));
1415 }
1416
1417 /**
1418 \brief configure memory protected region.
1419 \details
1420 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1421 \param [in] base_addr base address must be aligned with page size.
1422 \param [in] size \ref region_size_e. memory protected region size.
1423 \param [in] attr \ref region_size_t. memory protected region attribute.
1424 \param [in] enable enable or disable memory protected region.
1425 */
csi_mpu_config_region(uint32_t idx,uint32_t base_addr,region_size_e size,mpu_region_attr_t attr,uint32_t enable)1426 __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
1427 mpu_region_attr_t attr, uint32_t enable)
1428 {
1429 if (idx > 7) {
1430 return;
1431 }
1432
1433 CAPR_Type capr;
1434 PACR_Type pacr;
1435 PRSR_Type prsr;
1436
1437 capr.w = __get_CAPR();
1438 pacr.w = __get_PACR();
1439 prsr.w = __get_PRSR();
1440
1441 pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
1442
1443 prsr.b.RID = idx;
1444 __set_PRSR(prsr.w);
1445
1446 if (size != REGION_SIZE_4KB) {
1447 pacr.w &= ~(((1u << (size -11)) - 1) << 12);
1448 }
1449
1450 pacr.b.size = size;
1451
1452 capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
1453 capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
1454 __set_CAPR(capr.w);
1455
1456 pacr.b.E = enable;
1457 __set_PACR(pacr.w);
1458 }
1459
1460 /**
1461 \brief enable mpu region by idx.
1462 \details
1463 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1464 */
csi_mpu_enable_region(uint32_t idx)1465 __STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
1466 {
1467 if (idx > 7) {
1468 return;
1469 }
1470
1471 __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
1472 __set_PACR(__get_PACR() | PACR_E_Msk);
1473 }
1474
1475 /**
1476 \brief disable mpu region by idx.
1477 \details
1478 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1479 */
csi_mpu_disable_region(uint32_t idx)1480 __STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
1481 {
1482 if (idx > 7) {
1483 return;
1484 }
1485
1486 __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
1487 __set_PACR(__get_PACR() & (~PACR_E_Msk));
1488 }
1489
1490 /*@} end of CSI_Core_MMUFunctions */
1491
1492
1493 /* ################################## IRQ Functions ############################################ */
1494
1495 /**
1496 \brief Save the Irq context
1497 \details save the psr result before disable irq.
1498 \param [in] irq_num External interrupt number. Value cannot be negative.
1499 */
csi_irq_save(void)1500 __STATIC_INLINE uint32_t csi_irq_save(void)
1501 {
1502 uint32_t result;
1503 result = __get_PSR();
1504 __disable_irq();
1505 return(result);
1506 }
1507
1508 /**
1509 \brief Restore the Irq context
1510 \details restore saved primask state.
1511 \param [in] irq_state psr irq state.
1512 */
csi_irq_restore(uint32_t irq_state)1513 __STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
1514 {
1515 __set_PSR(irq_state);
1516 }
1517
1518 /*@} end of IRQ Functions */
1519
1520 /**
1521 \brief System Reset
1522 \details Initiates a system reset request to reset the MCU.
1523 */
csi_system_reset(void)1524 __STATIC_INLINE void csi_system_reset(void)
1525 {
1526 CHR_Type chr;
1527
1528 chr.w = __get_CHR();
1529 #ifdef __RESET_CONST
1530 chr.b.SRST_VAL = __RESET_CONST;
1531 #else
1532 chr.b.SRST_VAL = 0xABCD;
1533 #endif
1534
1535 __DSB(); /* Ensure all outstanding memory accesses included
1536 buffered write are completed before reset */
1537 __set_CHR(chr.w);
1538
1539 __DSB(); /* Ensure completion of memory access */
1540
1541 for(;;) /* wait until reset */
1542 {
1543 __NOP();
1544 }
1545 }
1546
1547 /* ################################## Old Interfaces ############################################ */
1548
1549 /* These interfaces are deprecated */
1550 #define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
1551 #define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
1552 #define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
1553 #define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
1554 #define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
1555 #define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
1556 #define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
1557 #define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
1558 #define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
1559 #define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
1560 #define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
1561 #define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
1562 #define NVIC_SystemReset() csi_system_reset()
1563
1564 #define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
1565 #define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
1566
1567 #define SCB_EnableICache() csi_icache_enable()
1568 #define SCB_DisableICache() csi_icache_disable()
1569 #define SCB_InvalidateICache() csi_icache_invalid()
1570 #define SCB_EnableDCache() csi_dcache_enable()
1571 #define SCB_DisableDCache() csi_dcache_disable()
1572 #define SCB_InvalidateDCache() csi_dcache_invalid()
1573 #define SCB_CleanDCache() csi_dcache_clean()
1574 #define SCB_CleanInvalidateDCache() csi_dcache_clean_invalid()
1575 #define SCB_InvalidateDCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize)
1576 #define SCB_CleanDCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
1577 #define SCB_CleanInvalidateDCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
1578 #define SCB_Cacheable_Range(index, baseAddr, size, enable) csi_cache_set_range(index, baseAddr, size, enable)
1579 #define SCB_EnableCacheProfile() csi_cache_enable_profile()
1580 #define SCB_DisableCacheProfile() csi_cache_disable_profile()
1581 #define SCB_ResetCacheProfile() csi_cache_reset_profile()
1582 #define SCB_CacheAccessTime() csi_cache_get_access_time()
1583 #define SCB_CacheMissTime() csi_cache_get_miss_time()
1584 #define SCB_EnableCache() csi_icache_enable();csi_dcache_enable()
1585 #define SCB_DisableCache() csi_icache_disable();csi_dcache_disable()
1586 #define SCB_InvalidateCache() csi_icache_invalid();csi_dcache_invalid()
1587 #define SCB_CleanCache() csi_dcache_clean()
1588 #define SCB_CleanInvalidateCache() csi_icache_invalid();csi_dcache_clean();csi_dcache_invalid()
1589 #define SCB_InvalidateCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize);csi_icache_invalid()
1590 #define SCB_CleanCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
1591 #define SCB_CleanInvalidateCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
1592
1593 #ifdef __cplusplus
1594 }
1595 #endif
1596
1597 #endif /* __CORE_804_H_DEPENDANT */
1598
1599 #endif /* __CSI_GENERIC */
1600