1 /**************************************************************************//**
2  * @file     best1000.h
3  * @brief    CMSIS Core Peripheral Access Layer Header File for
4  *           ARMCM4 Device Series
5  * @version  V2.02
6  * @date     10. September 2014
7  *
8  * @note     configured for CM4 with FPU
9  *
10  ******************************************************************************/
11 /* Copyright (c) 2011 - 2014 ARM LIMITED
12 
13    All rights reserved.
14    Redistribution and use in source and binary forms, with or without
15    modification, are permitted provided that the following conditions are met:
16    - Redistributions of source code must retain the above copyright
17      notice, this list of conditions and the following disclaimer.
18    - Redistributions in binary form must reproduce the above copyright
19      notice, this list of conditions and the following disclaimer in the
20      documentation and/or other materials provided with the distribution.
21    - Neither the name of ARM nor the names of its contributors may be used
22      to endorse or promote products derived from this software without
23      specific prior written permission.
24    *
25    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
29    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35    POSSIBILITY OF SUCH DAMAGE.
36    ---------------------------------------------------------------------------*/
37 
38 
39 #ifndef __FPGA1000_H__
40 #define __FPGA1000_H__
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
46 #ifndef __ASSEMBLER__
47 /* -------------------------  Interrupt Number Definition  ------------------------ */
48 
49 typedef enum IRQn
50 {
51 /* -------------------  Cortex-M4 Processor Exceptions Numbers  ------------------- */
52   NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt          */
53   HardFault_IRQn                = -13,      /*!<  3 HardFault Interrupt             */
54   MemoryManagement_IRQn         = -12,      /*!<  4 Memory Management Interrupt     */
55   BusFault_IRQn                 = -11,      /*!<  5 Bus Fault Interrupt             */
56   UsageFault_IRQn               = -10,      /*!<  6 Usage Fault Interrupt           */
57   SVCall_IRQn                   =  -5,      /*!< 11 SV Call Interrupt               */
58   DebugMonitor_IRQn             =  -4,      /*!< 12 Debug Monitor Interrupt         */
59   PendSV_IRQn                   =  -2,      /*!< 14 Pend SV Interrupt               */
60   SysTick_IRQn                  =  -1,      /*!< 15 System Tick Interrupt           */
61 
62 /* ----------------------  BEST1000 Specific Interrupt Numbers  --------------------- */
63   FPU_IRQn                      =   0,      /*!< FPU Interrupt                      */
64   SDIO_IRQn                     =   1,      /*!< SDIO Interrupt                     */
65   SDMMC_IRQn                    =   2,      /*!< SDMMC Interrupt                    */
66   AUDMA_IRQn                    =   3,      /*!< Audio DMA Interrupt                */
67   GPDMA_IRQn                    =   4,      /*!< General Purpose DMA Interrupt      */
68   DPDRX_IRQn                    =   5,      /*!< DPD RX Interrupt                   */
69   DPDTX_IRQn                    =   6,      /*!< DPD TX Interrupt                   */
70   USB_IRQn                      =   7,      /*!< USB Interrupt                      */
71   WAKEUP_IRQn                   =   8,      /*!< Reserved Interrupt                 */
72   GPIO_IRQn                     =   9,      /*!< GPIO Interrupt                     */
73   WDT_IRQn                      =  10,      /*!< Watchdog Timer Interrupt           */
74   RTC_IRQn                      =  11,      /*!< RTC Interrupt                      */
75   TIMER00_IRQn                  =  12,      /*!< Timer00 Interrupt                  */
76   TIMER01_IRQn                  =  13,      /*!< Timer01 Interrupt                  */
77   I2C0_IRQn                     =  14,      /*!< I2C0 Interrupt                     */
78   SPI0_IRQn                     =  15,      /*!< SPI0 Interrupt                     */
79   SPILCD_IRQn                   =  16,      /*!< SPILCD Interrupt                   */
80   UART0_IRQn                    =  17,      /*!< UART0 Interrupt                    */
81   UART1_IRQn                    =  18,      /*!< UART1 Interrupt                    */
82   CODEC_IRQn                    =  19,      /*!< CODEC Interrupt                    */
83   BTPCM_IRQn                    =  20,      /*!< BTPCM Interrupt                    */
84   I2S0_IRQn                     =  21,      /*!< I2S0 Interrupt                     */
85   SPDIF_IRQn                    =  22,      /*!< SPDIF Interrupt                    */
86   ITNSPI_IRQn                   =  23,      /*!< Reserved Interrupt                 */
87   BT_IRQn                       =  24,      /*!< Reserved Interrupt                 */
88   GPADC_IRQn                    =  25,      /*!< Reserved Interrupt                 */
89   NONE4_IRQn                    =  26,      /*!< Reserved Interrupt                 */
90   USB_PIN_IRQn                  =  27,      /*!< Reserved Interrupt                 */
91   ISDONE_IRQn                   =  28,      /*!< Intersys MCU2BT Data Done Interrupt */
92   ISDONE1_IRQn                  =  29,      /*!< Intersys MCU2BT Data1 Done Interrupt */
93   ISDATA_IRQn                   =  30,      /*!< Intersys BT2MCU Data Indication Interrupt */
94   ISDATA1_IRQn                  =  31,      /*!< Intersys BT2MCU Data1 Indication Interrupt */
95   CHARGER_IRQn                  =  32,      /*!< Charger IRQ                        */
96   PWRKEY_IRQn                   =  33,      /*!< Power key IRQ                      */
97 
98   USER_IRQn_QTY,
99   INVALID_IRQn                  = USER_IRQn_QTY,
100 } IRQn_Type;
101 
102 #endif
103 
104 /* ================================================================================ */
105 /* ================      Processor and Core Peripheral Section     ================ */
106 /* ================================================================================ */
107 
108 /* --------  Configuration of the Cortex-M4 Processor and Core Peripherals  ------- */
109 #define __CM4_REV                 0x0001    /*!< Core revision r0p1                              */
110 #define __MPU_PRESENT             1         /*!< MPU present or not                              */
111 #define __VTOR_PRESENT            1U        /* VTOR present */
112 #define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels         */
113 #define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used    */
114 #define __FPU_PRESENT             1         /*!< FPU present                                     */
115 #define __NUM_CODE_PATCH          32
116 #define __NUM_LIT_PATCH           32
117 
118 #include "core_cm4.h"                       /* Processor and core peripherals                    */
119 
120 #ifndef __ASSEMBLER__
121 
122 #include "system_ARMCM.h"                  /* System Header                                     */
123 
124 #endif
125 
126 /* ================================================================================ */
127 /* ================       Device Specific Peripheral Section       ================ */
128 /* ================================================================================ */
129 
130 /* -------------------  Start of section using anonymous unions  ------------------ */
131 #if   defined (__CC_ARM)
132   #pragma push
133   #pragma anon_unions
134 #elif defined (__ICCARM__)
135   #pragma language=extended
136 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
137   #pragma clang diagnostic push
138   #pragma clang diagnostic ignored "-Wc11-extensions"
139   #pragma clang diagnostic ignored "-Wreserved-id-macro"
140 #elif defined (__GNUC__)
141   /* anonymous unions are enabled by default */
142 #elif defined (__TMS470__)
143   /* anonymous unions are enabled by default */
144 #elif defined (__TASKING__)
145   #pragma warning 586
146 #elif defined (__CSMC__)
147   /* anonymous unions are enabled by default */
148 #else
149   #warning Not supported compiler type
150 #endif
151 
152 /* --------------------  End of section using anonymous unions  ------------------- */
153 #if   defined (__CC_ARM)
154   #pragma pop
155 #elif defined (__ICCARM__)
156   /* leave anonymous unions enabled */
157 #elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
158   #pragma clang diagnostic pop
159 #elif defined (__GNUC__)
160   /* anonymous unions are enabled by default */
161 #elif defined (__TMS470__)
162   /* anonymous unions are enabled by default */
163 #elif defined (__TASKING__)
164   #pragma warning restore
165 #elif defined (__CSMC__)
166   /* anonymous unions are enabled by default */
167 #else
168   #warning Not supported compiler type
169 #endif
170 
171 #ifdef __cplusplus
172 }
173 #endif
174 
175 #endif
176