1 /**************************************************************************//**
2  * @file     haas1000.h
3  * @brief    CMSIS Core Peripheral Access Layer Header File for
4  *           ARMCM4 Device Series
5  * @version  V2.02
6  * @date     10. September 2014
7  *
8  * @note     configured for CM4 with FPU
9  *
10  ******************************************************************************/
11 /* Copyright (c) 2011 - 2014 ARM LIMITED
12 
13    All rights reserved.
14    Redistribution and use in source and binary forms, with or without
15    modification, are permitted provided that the following conditions are met:
16    - Redistributions of source code must retain the above copyright
17      notice, this list of conditions and the following disclaimer.
18    - Redistributions in binary form must reproduce the above copyright
19      notice, this list of conditions and the following disclaimer in the
20      documentation and/or other materials provided with the distribution.
21    - Neither the name of ARM nor the names of its contributors may be used
22      to endorse or promote products derived from this software without
23      specific prior written permission.
24    *
25    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
29    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35    POSSIBILITY OF SUCH DAMAGE.
36    ---------------------------------------------------------------------------*/
37 
38 
39 #ifndef __HAAS1000_H__
40 #define __HAAS1000_H__
41 
42 #ifdef CHIP_HAAS1000_DSP
43 
44 #include "ca/haas1000_dsp.h"
45 
46 #else
47 
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
51 
52 #ifndef __ASSEMBLER__
53 /* -------------------------  Interrupt Number Definition  ------------------------ */
54 
55 typedef enum IRQn
56 {
57 /* -------------------  Cortex-M33 Processor Exceptions Numbers  ------------------ */
58     NonMaskableInt_IRQn         = -14,      /*!<  2 Non Maskable Interrupt          */
59     HardFault_IRQn              = -13,      /*!<  3 HardFault Interrupt             */
60     MemoryManagement_IRQn       = -12,      /*!<  4 Memory Management Interrupt     */
61     BusFault_IRQn               = -11,      /*!<  5 Bus Fault Interrupt             */
62     UsageFault_IRQn             = -10,      /*!<  6 Usage Fault Interrupt           */
63     SVCall_IRQn                 =  -5,      /*!< 11 SV Call Interrupt               */
64     DebugMonitor_IRQn           =  -4,      /*!< 12 Debug Monitor Interrupt         */
65     PendSV_IRQn                 =  -2,      /*!< 14 Pend SV Interrupt               */
66     SysTick_IRQn                =  -1,      /*!< 15 System Tick Interrupt           */
67 
68 /* ----------------------  Chip Specific Interrupt Numbers  ----------------------- */
69     FPU_IRQn                    =   0,      /*!< FPU Interrupt                      */
70     WAKEUP_IRQn                 =   1,      /*!< Wakeup Interrupt                   */
71     CODEC_IRQn                  =   2,      /*!< CODEC Interrupt                    */
72     CODEC_TX_PEAK_IRQn          =   3,      /*!< CODEC TX PEAK Interrupt            */
73     SDMMC_IRQn                  =   4,      /*!< SDMMC Interrupt                    */
74     BES2001_AUDMA_IRQn          =   5,      /*!< Audio DMA Interrupt                */
75     BES2001_GPDMA_IRQn          =   6,      /*!< General Purpose DMA Interrupt      */
76     USB_IRQn                    =   7,      /*!< USB Interrupt                      */
77     USB_PHY_IRQn                =   8,      /*!< USB PHY Interrupt                  */
78     USB_CAL_IRQn                =   9,      /*!< USB Calibration Interrupt          */
79     RESERVED10_IRQn             =  10,      /*!< Reserved Interrupt                 */
80     SEC_ENG_IRQn                =  11,      /*!< Security Engine Interrupt          */
81     SEDMA_IRQn                  =  12,      /*!< Security Engine DMA Interrupt      */
82     DUMP_IRQn                   =  13,      /*!< DUMP Interrupt                     */
83     MCU_WDT_IRQn                =  14,      /*!< Watchdog Timer Interrupt           */
84     MCU_TIMER00_IRQn            =  15,      /*!< Timer00 Interrupt                  */
85     MCU_TIMER01_IRQn            =  16,      /*!< Timer01 Interrupt                  */
86     MCU_TIMER10_IRQn            =  17,      /*!< Timer10 Interrupt                  */
87     MCU_TIMER11_IRQn            =  18,      /*!< Timer11 Interrupt                  */
88     MCU_TIMER20_IRQn            =  19,      /*!< Timer20 Interrupt                  */
89     MCU_TIMER21_IRQn            =  20,      /*!< Timer21 Interrupt                  */
90     I2C0_IRQn                   =  21,      /*!< I2C0 Interrupt                     */
91     I2C1_IRQn                   =  22,      /*!< I2C1 Interrupt                     */
92     SPI0_IRQn                   =  23,      /*!< SPI0 Interrupt                     */
93     SPILCD_IRQn                 =  24,      /*!< SPILCD Interrupt                   */
94     ITNSPI_IRQn                 =  25,      /*!< Internal SPI Interrupt             */
95     SPIPHY_IRQn                 =  26,      /*!< SPIPHY Interrupt                   */
96     UART0_IRQn                  =  27,      /*!< UART0 Interrupt                    */
97     UART1_IRQn                  =  28,      /*!< UART1 Interrupt                    */
98     UART2_IRQn                  =  29,      /*!< UART2 Interrupt                    */
99     BTPCM_IRQn                  =  30,      /*!< BTPCM Interrupt                    */
100     I2S0_IRQn                   =  31,      /*!< I2S0 Interrupt                     */
101     SPDIF0_IRQn                 =  32,      /*!< SPDIF0 Interrupt                   */
102     TRNG_IRQn                   =  33,      /*!< TRNG Interrupt                     */
103     AON_GPIO_IRQn               =  34,      /*!< AON GPIO Interrupt                 */
104     AON_GPIOAUX_IRQn            =  35,      /*!< AON GPIOAUX Interrupt              */
105     AON_WDT_IRQn                =  36,      /*!< AON Watchdog Timer Interrupt       */
106     AON_TIMER00_IRQn            =  37,      /*!< AON Timer00 Interrupt              */
107     AON_TIMER01_IRQn            =  38,      /*!< AON Timer01 Interrupt              */
108     MCU2CP_DONE_IRQn            =  39,      /*!< Intersys MCU2CP Data Done Interrupt */
109     MCU2CP_DONE1_IRQn           =  40,      /*!< Intersys MCU2CP Data Done Interrupt */
110     MCU2CP_DONE2_IRQn           =  41,      /*!< Intersys MCU2CP Data Done Interrupt */
111     MCU2CP_DONE3_IRQn           =  42,      /*!< Intersys MCU2CP Data Done Interrupt */
112     CP2MCU_DATA_IRQn            =  43,      /*!< Intersys CP2MCU Data Indication Interrupt */
113     CP2MCU_DATA1_IRQn           =  44,      /*!< Intersys CP2MCU Data1 Indication Interrupt */
114     CP2MCU_DATA2_IRQn           =  45,      /*!< Intersys CP2MCU Data Indication Interrupt */
115     CP2MCU_DATA3_IRQn           =  46,      /*!< Intersys CP2MCU Data1 Indication Interrupt */
116     TRANSQD_LCL_IRQn            =  47,      /*!< TRANSQ-DSP Local Interrupt         */
117     TRANSQD_RMT_IRQn            =  48,      /*!< TRANSQ-DSP Peer Remote Interrupt   */
118     DSP_IRQn                    =  49,      /*!< DSP to MCU Interrupt               */
119     TRANSQW_LCL_IRQn            =  50,      /*!< TRANSQ-WIFI Local Interrupt        */
120     TRANSQW_RMT_IRQn            =  51,      /*!< TRANSQ-WIFI Peer Remote Interrupt  */
121     WIFI_IRQn                   =  52,      /*!< DSP to MCU Interrupt               */
122     ISDONE_IRQn                 =  53,      /*!< Intersys MCU2BT Data Done Interrupt */
123     ISDONE1_IRQn                =  54,      /*!< Intersys MCU2BT Data1 Done Interrupt */
124     ISDATA_IRQn                 =  55,      /*!< Intersys BT2MCU Data Indication Interrupt */
125     ISDATA1_IRQn                =  56,      /*!< Intersys BT2MCU Data1 Indication Interrupt */
126     BT_IRQn                     =  57,      /*!< BT to MCU Interrupt                */
127     USB_PIN_IRQn                =  58,      /*!< USB Pin Interrupt                  */
128     RTC_IRQn                    =  59,      /*!< RTC Interrupt                      */
129     GPADC_IRQn                  =  60,      /*!< GPADC Interrupt                    */
130     CHARGER_IRQn                =  61,      /*!< Charger Interrupt                  */
131     PWRKEY_IRQn                 =  62,      /*!< Power key Interrupt                */
132     WIFIDUMP_IRQn               =  63,      /*!< WIFIDUMP Interrupt                 */
133     CHKSUM_IRQn                 =  64,      /*!< Checksum Interrupt                 */
134     CRC_IRQn                    =  65,      /*!< CRC Interrupt                      */
135     CP_DSLP_IRQn                =  66,      /*!< CP Deep Sleep Interrupt            */
136     AON_SPIDPD_IRQn             =  67,      /*!< AON SPIDPD Interrupt               */
137     TRUSTZONE_IRQn              =  68,      /*!< TrustZone Interrupt                */
138 
139     USER_IRQn_QTY,
140     INVALID_IRQn                = USER_IRQn_QTY,
141 } IRQn_Type;
142 
143 #ifndef DSP_USE_AUDMA
144 #define AUDMA_IRQn              BES2001_AUDMA_IRQn
145 #define GPDMA_IRQn              BES2001_GPDMA_IRQn
146 #else
147 #define AUDMA_IRQn              BES2001_GPDMA_IRQn //MCU use GPDMA
148 #endif
149 
150 #define GPIO_IRQn               AON_GPIO_IRQn
151 #define GPIOAUX_IRQn            AON_GPIOAUX_IRQn
152 #define TIMER00_IRQn            MCU_TIMER00_IRQn
153 #define TIMER01_IRQn            MCU_TIMER01_IRQn
154 #define WDT_IRQn                AON_WDT_IRQn
155 
156 #define TRANSQ0_RMT_IRQn        TRANSQW_RMT_IRQn
157 #define TRANSQ0_LCL_IRQn        TRANSQW_LCL_IRQn
158 #define TRANSQ1_RMT_IRQn        TRANSQD_RMT_IRQn
159 #define TRANSQ1_LCL_IRQn        TRANSQD_LCL_IRQn
160 
161 #endif
162 
163 /* ================================================================================ */
164 /* ================      Processor and Core Peripheral Section     ================ */
165 /* ================================================================================ */
166 
167 /* --------  Configuration of Core Peripherals  ----------------------------------- */
168 #define __CM33_REV                0x0000U   /* Core revision r0p1 */
169 #define __SAUREGION_PRESENT       0U        /* SAU regions present */
170 #define __MPU_PRESENT             1U        /* MPU present */
171 #define __VTOR_PRESENT            1U        /* VTOR present */
172 #define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */
173 #define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */
174 #define __FPU_PRESENT             1U        /* FPU present */
175 #define __DSP_PRESENT             1U        /* DSP extension present */
176 
177 #if (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || defined(CHIP_HAAS1000_ARCH_ENHANCE)
178 #include "core_cm33.h"                      /* Processor and core peripherals */
179 #else
180 #define __NUM_CODE_PATCH          32
181 #define __NUM_LIT_PATCH           32
182 #include "core_cm4.h"                      /* Processor and core peripherals */
183 #endif
184 
185 #ifndef __ASSEMBLER__
186 
187 #include "system_ARMCM.h"                  /* System Header                                     */
188 
189 #endif
190 
191 /* ================================================================================ */
192 /* ================       Device Specific Peripheral Section       ================ */
193 /* ================================================================================ */
194 
195 /* -------------------  Start of section using anonymous unions  ------------------ */
196 #if   defined (__CC_ARM)
197   #pragma push
198   #pragma anon_unions
199 #elif defined (__ICCARM__)
200   #pragma language=extended
201 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
202   #pragma clang diagnostic push
203   #pragma clang diagnostic ignored "-Wc11-extensions"
204   #pragma clang diagnostic ignored "-Wreserved-id-macro"
205 #elif defined (__GNUC__)
206   /* anonymous unions are enabled by default */
207 #elif defined (__TMS470__)
208   /* anonymous unions are enabled by default */
209 #elif defined (__TASKING__)
210   #pragma warning 586
211 #elif defined (__CSMC__)
212   /* anonymous unions are enabled by default */
213 #else
214   #warning Not supported compiler type
215 #endif
216 
217 /* --------------------  End of section using anonymous unions  ------------------- */
218 #if   defined (__CC_ARM)
219   #pragma pop
220 #elif defined (__ICCARM__)
221   /* leave anonymous unions enabled */
222 #elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
223   #pragma clang diagnostic pop
224 #elif defined (__GNUC__)
225   /* anonymous unions are enabled by default */
226 #elif defined (__TMS470__)
227   /* anonymous unions are enabled by default */
228 #elif defined (__TASKING__)
229   #pragma warning restore
230 #elif defined (__CSMC__)
231   /* anonymous unions are enabled by default */
232 #else
233   #warning Not supported compiler type
234 #endif
235 
236 #ifdef __cplusplus
237 }
238 #endif
239 
240 #endif
241 
242 #endif
243