1 /**************************************************************************//**
2 * @file cmsis_gcc.h
3 * @brief CMSIS Cortex-M Core Function/Instruction Header File
4 * @version V5.00
5 * @date 20. December 2016
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #ifndef __CMSIS_GCC_H
26 #define __CMSIS_GCC_H
27
28 /* ignore some GCC warnings */
29 #pragma GCC diagnostic push
30 #pragma GCC diagnostic ignored "-Wsign-conversion"
31 #pragma GCC diagnostic ignored "-Wconversion"
32 #pragma GCC diagnostic ignored "-Wunused-parameter"
33
34 /* CMSIS compiler specific defines */
35 #ifndef __ASM
36 #define __ASM __asm
37 #endif
38 #ifndef __INLINE
39 #define __INLINE inline
40 #endif
41 #ifndef __STATIC_INLINE
42 #define __STATIC_INLINE static inline __attribute__((always_inline))
43 #endif
44 #ifndef __NO_RETURN
45 #define __NO_RETURN __attribute__((noreturn))
46 #endif
47 #ifndef __USED
48 #define __USED __attribute__((used))
49 #endif
50 #ifndef __WEAK
51 #define __WEAK __attribute__((weak))
52 #endif
53 #ifndef __UNALIGNED_UINT32
54 #pragma GCC diagnostic push
55 #pragma GCC diagnostic ignored "-Wpacked"
56 #pragma GCC diagnostic ignored "-Wattributes"
57 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
58 #pragma GCC diagnostic pop
59 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
60 #endif
61 #ifndef __ALIGNED
62 #define __ALIGNED(x) __attribute__((aligned(x)))
63 #endif
64 #ifndef __PACKED
65 #define __PACKED __attribute__((packed, aligned(1)))
66 #endif
67
68
69 /* ########################### Core Function Access ########################### */
70 /** \ingroup CMSIS_Core_FunctionInterface
71 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
72 @{
73 */
74
75 /**
76 \brief Enable IRQ Interrupts
77 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
78 Can only be executed in Privileged modes.
79 */
__enable_irq(void)80 __attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
81 {
82 __ASM volatile ("cpsie i" : : : "memory");
83 }
84
85
86 /**
87 \brief Disable IRQ Interrupts
88 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
89 Can only be executed in Privileged modes.
90 */
__disable_irq(void)91 __attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
92 {
93 __ASM volatile ("cpsid i" : : : "memory");
94 }
95
96
97 /**
98 \brief Get Control Register
99 \details Returns the content of the Control Register.
100 \return Control Register value
101 */
__get_CONTROL(void)102 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
103 {
104 uint32_t result;
105
106 __ASM volatile ("MRS %0, control" : "=r" (result) );
107 return(result);
108 }
109
110
111 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
112 /**
113 \brief Get Control Register (non-secure)
114 \details Returns the content of the non-secure Control Register when in secure mode.
115 \return non-secure Control Register value
116 */
__TZ_get_CONTROL_NS(void)117 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
118 {
119 uint32_t result;
120
121 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
122 return(result);
123 }
124 #endif
125
126
127 /**
128 \brief Set Control Register
129 \details Writes the given value to the Control Register.
130 \param [in] control Control Register value to set
131 */
__set_CONTROL(uint32_t control)132 __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
133 {
134 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
135 }
136
137
138 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
139 /**
140 \brief Set Control Register (non-secure)
141 \details Writes the given value to the non-secure Control Register when in secure state.
142 \param [in] control Control Register value to set
143 */
__TZ_set_CONTROL_NS(uint32_t control)144 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
145 {
146 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
147 }
148 #endif
149
150
151 /**
152 \brief Get IPSR Register
153 \details Returns the content of the IPSR Register.
154 \return IPSR Register value
155 */
__get_IPSR(void)156 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
157 {
158 uint32_t result;
159
160 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
161 return(result);
162 }
163
164
165 /**
166 \brief Get APSR Register
167 \details Returns the content of the APSR Register.
168 \return APSR Register value
169 */
__get_APSR(void)170 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
171 {
172 uint32_t result;
173
174 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
175 return(result);
176 }
177
178
179 /**
180 \brief Get xPSR Register
181 \details Returns the content of the xPSR Register.
182 \return xPSR Register value
183 */
__get_xPSR(void)184 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
185 {
186 uint32_t result;
187
188 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
189 return(result);
190 }
191
192
193 /**
194 \brief Get Process Stack Pointer
195 \details Returns the current value of the Process Stack Pointer (PSP).
196 \return PSP Register value
197 */
__get_PSP(void)198 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
199 {
200 register uint32_t result;
201
202 __ASM volatile ("MRS %0, psp" : "=r" (result) );
203 return(result);
204 }
205
206
207 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
208 /**
209 \brief Get Process Stack Pointer (non-secure)
210 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
211 \return PSP Register value
212 */
__TZ_get_PSP_NS(void)213 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
214 {
215 register uint32_t result;
216
217 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
218 return(result);
219 }
220 #endif
221
222
223 /**
224 \brief Set Process Stack Pointer
225 \details Assigns the given value to the Process Stack Pointer (PSP).
226 \param [in] topOfProcStack Process Stack Pointer value to set
227 */
__set_PSP(uint32_t topOfProcStack)228 __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
229 {
230 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");
231 }
232
233
234 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
235 /**
236 \brief Set Process Stack Pointer (non-secure)
237 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
238 \param [in] topOfProcStack Process Stack Pointer value to set
239 */
__TZ_set_PSP_NS(uint32_t topOfProcStack)240 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
241 {
242 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp");
243 }
244 #endif
245
246
247 /**
248 \brief Get Main Stack Pointer
249 \details Returns the current value of the Main Stack Pointer (MSP).
250 \return MSP Register value
251 */
__get_MSP(void)252 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
253 {
254 register uint32_t result;
255
256 __ASM volatile ("MRS %0, msp" : "=r" (result) );
257 return(result);
258 }
259
260
261 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
262 /**
263 \brief Get Main Stack Pointer (non-secure)
264 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
265 \return MSP Register value
266 */
__TZ_get_MSP_NS(void)267 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
268 {
269 register uint32_t result;
270
271 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
272 return(result);
273 }
274 #endif
275
276
277 /**
278 \brief Set Main Stack Pointer
279 \details Assigns the given value to the Main Stack Pointer (MSP).
280 \param [in] topOfMainStack Main Stack Pointer value to set
281 */
__set_MSP(uint32_t topOfMainStack)282 __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
283 {
284 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");
285 }
286
287
288 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
289 /**
290 \brief Set Main Stack Pointer (non-secure)
291 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
292 \param [in] topOfMainStack Main Stack Pointer value to set
293 */
__TZ_set_MSP_NS(uint32_t topOfMainStack)294 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
295 {
296 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp");
297 }
298 #endif
299
300
301 /**
302 \brief Get Priority Mask
303 \details Returns the current state of the priority mask bit from the Priority Mask Register.
304 \return Priority Mask value
305 */
__get_PRIMASK(void)306 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
307 {
308 uint32_t result;
309
310 __ASM volatile ("MRS %0, primask" : "=r" (result) );
311 return(result);
312 }
313
314
315 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
316 /**
317 \brief Get Priority Mask (non-secure)
318 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
319 \return Priority Mask value
320 */
__TZ_get_PRIMASK_NS(void)321 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
322 {
323 uint32_t result;
324
325 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
326 return(result);
327 }
328 #endif
329
330
331 /**
332 \brief Set Priority Mask
333 \details Assigns the given value to the Priority Mask Register.
334 \param [in] priMask Priority Mask
335 */
__set_PRIMASK(uint32_t priMask)336 __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
337 {
338 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
339 }
340
341
342 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
343 /**
344 \brief Set Priority Mask (non-secure)
345 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
346 \param [in] priMask Priority Mask
347 */
__TZ_set_PRIMASK_NS(uint32_t priMask)348 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
349 {
350 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
351 }
352 #endif
353
354
355 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
356 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
357 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
358 /**
359 \brief Enable FIQ
360 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
361 Can only be executed in Privileged modes.
362 */
__enable_fault_irq(void)363 __attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
364 {
365 __ASM volatile ("cpsie f" : : : "memory");
366 }
367
368
369 /**
370 \brief Disable FIQ
371 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
372 Can only be executed in Privileged modes.
373 */
__disable_fault_irq(void)374 __attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
375 {
376 __ASM volatile ("cpsid f" : : : "memory");
377 }
378
379
380 /**
381 \brief Get Base Priority
382 \details Returns the current value of the Base Priority register.
383 \return Base Priority register value
384 */
__get_BASEPRI(void)385 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
386 {
387 uint32_t result;
388
389 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
390 return(result);
391 }
392
393
394 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
395 /**
396 \brief Get Base Priority (non-secure)
397 \details Returns the current value of the non-secure Base Priority register when in secure state.
398 \return Base Priority register value
399 */
__TZ_get_BASEPRI_NS(void)400 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
401 {
402 uint32_t result;
403
404 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
405 return(result);
406 }
407 #endif
408
409
410 /**
411 \brief Set Base Priority
412 \details Assigns the given value to the Base Priority register.
413 \param [in] basePri Base Priority value to set
414 */
__set_BASEPRI(uint32_t basePri)415 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
416 {
417 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
418 }
419
420
421 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
422 /**
423 \brief Set Base Priority (non-secure)
424 \details Assigns the given value to the non-secure Base Priority register when in secure state.
425 \param [in] basePri Base Priority value to set
426 */
__TZ_set_BASEPRI_NS(uint32_t basePri)427 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
428 {
429 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
430 }
431 #endif
432
433
434 /**
435 \brief Set Base Priority with condition
436 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
437 or the new value increases the BASEPRI priority level.
438 \param [in] basePri Base Priority value to set
439 */
__set_BASEPRI_MAX(uint32_t basePri)440 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
441 {
442 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
443 }
444
445
446 /**
447 \brief Get Fault Mask
448 \details Returns the current value of the Fault Mask register.
449 \return Fault Mask register value
450 */
__get_FAULTMASK(void)451 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
452 {
453 uint32_t result;
454
455 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
456 return(result);
457 }
458
459
460 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
461 /**
462 \brief Get Fault Mask (non-secure)
463 \details Returns the current value of the non-secure Fault Mask register when in secure state.
464 \return Fault Mask register value
465 */
__TZ_get_FAULTMASK_NS(void)466 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
467 {
468 uint32_t result;
469
470 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
471 return(result);
472 }
473 #endif
474
475
476 /**
477 \brief Set Fault Mask
478 \details Assigns the given value to the Fault Mask register.
479 \param [in] faultMask Fault Mask value to set
480 */
__set_FAULTMASK(uint32_t faultMask)481 __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
482 {
483 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
484 }
485
486
487 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
488 /**
489 \brief Set Fault Mask (non-secure)
490 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
491 \param [in] faultMask Fault Mask value to set
492 */
__TZ_set_FAULTMASK_NS(uint32_t faultMask)493 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
494 {
495 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
496 }
497 #endif
498
499 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
500 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
501 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
502
503
504 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
505 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
506
507 /**
508 \brief Get Process Stack Pointer Limit
509 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
510 \return PSPLIM Register value
511 */
__get_PSPLIM(void)512 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
513 {
514 register uint32_t result;
515
516 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
517 return(result);
518 }
519
520
521 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
522 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
523 /**
524 \brief Get Process Stack Pointer Limit (non-secure)
525 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
526 \return PSPLIM Register value
527 */
__TZ_get_PSPLIM_NS(void)528 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
529 {
530 register uint32_t result;
531
532 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
533 return(result);
534 }
535 #endif
536
537
538 /**
539 \brief Set Process Stack Pointer Limit
540 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
541 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
542 */
__set_PSPLIM(uint32_t ProcStackPtrLimit)543 __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
544 {
545 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
546 }
547
548
549 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
550 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
551 /**
552 \brief Set Process Stack Pointer (non-secure)
553 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
554 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
555 */
__TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)556 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
557 {
558 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
559 }
560 #endif
561
562
563 /**
564 \brief Get Main Stack Pointer Limit
565 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
566 \return MSPLIM Register value
567 */
__get_MSPLIM(void)568 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
569 {
570 register uint32_t result;
571
572 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
573
574 return(result);
575 }
576
577
578 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
579 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
580 /**
581 \brief Get Main Stack Pointer Limit (non-secure)
582 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
583 \return MSPLIM Register value
584 */
__TZ_get_MSPLIM_NS(void)585 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
586 {
587 register uint32_t result;
588
589 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
590 return(result);
591 }
592 #endif
593
594
595 /**
596 \brief Set Main Stack Pointer Limit
597 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
598 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
599 */
__set_MSPLIM(uint32_t MainStackPtrLimit)600 __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
601 {
602 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
603 }
604
605
606 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
607 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
608 /**
609 \brief Set Main Stack Pointer Limit (non-secure)
610 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
611 \param [in] MainStackPtrLimit Main Stack Pointer value to set
612 */
__TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)613 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
614 {
615 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
616 }
617 #endif
618
619 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
620 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
621
622
623 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
624 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
625
626 /**
627 \brief Get FPSCR
628 \details Returns the current value of the Floating Point Status/Control register.
629 \return Floating Point Status/Control register value
630 */
__get_FPSCR(void)631 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
632 {
633 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
634 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
635 uint32_t result;
636
637 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
638 return(result);
639 #else
640 return(0U);
641 #endif
642 }
643
644
645 /**
646 \brief Set FPSCR
647 \details Assigns the given value to the Floating Point Status/Control register.
648 \param [in] fpscr Floating Point Status/Control value to set
649 */
__set_FPSCR(uint32_t fpscr)650 __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
651 {
652 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
653 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
654 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
655 #else
656 (void)fpscr;
657 #endif
658 }
659
660 #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
661 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
662
663
664
665 /*@} end of CMSIS_Core_RegAccFunctions */
666
667
668 /* ########################## Core Instruction Access ######################### */
669 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
670 Access to dedicated instructions
671 @{
672 */
673
674 /* Define macros for porting to both thumb1 and thumb2.
675 * For thumb1, use low register (r0-r7), specified by constraint "l"
676 * Otherwise, use general registers, specified by constraint "r" */
677 #if defined (__thumb__) && !defined (__thumb2__)
678 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
679 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
680 #define __CMSIS_GCC_USE_REG(r) "l" (r)
681 #else
682 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
683 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
684 #define __CMSIS_GCC_USE_REG(r) "r" (r)
685 #endif
686
687 /**
688 \brief No Operation
689 \details No Operation does nothing. This instruction can be used for code alignment purposes.
690 */
691 //__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
692 //{
693 // __ASM volatile ("nop");
694 //}
695 #define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
696
697 /**
698 \brief Wait For Interrupt
699 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
700 */
701 //__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
702 //{
703 // __ASM volatile ("wfi");
704 //}
705 #define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
706
707
708 /**
709 \brief Wait For Event
710 \details Wait For Event is a hint instruction that permits the processor to enter
711 a low-power state until one of a number of events occurs.
712 */
713 //__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
714 //{
715 // __ASM volatile ("wfe");
716 //}
717 #define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
718
719
720 /**
721 \brief Send Event
722 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
723 */
724 //__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
725 //{
726 // __ASM volatile ("sev");
727 //}
728 #define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
729
730
731 /**
732 \brief Instruction Synchronization Barrier
733 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
734 so that all instructions following the ISB are fetched from cache or memory,
735 after the instruction has been completed.
736 */
__ISB(void)737 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
738 {
739 __ASM volatile ("isb 0xF":::"memory");
740 }
741
742
743 /**
744 \brief Data Synchronization Barrier
745 \details Acts as a special kind of Data Memory Barrier.
746 It completes when all explicit memory accesses before this instruction complete.
747 */
__DSB(void)748 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
749 {
750 __ASM volatile ("dsb 0xF":::"memory");
751 }
752
753
754 /**
755 \brief Data Memory Barrier
756 \details Ensures the apparent order of the explicit memory operations before
757 and after the instruction, without ensuring their completion.
758 */
__DMB(void)759 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
760 {
761 __ASM volatile ("dmb 0xF":::"memory");
762 }
763
764
765 /**
766 \brief Reverse byte order (32 bit)
767 \details Reverses the byte order in integer value.
768 \param [in] value Value to reverse
769 \return Reversed value
770 */
__REV(uint32_t value)771 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
772 {
773 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
774 return __builtin_bswap32(value);
775 #else
776 uint32_t result;
777
778 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
779 return(result);
780 #endif
781 }
782
783
784 /**
785 \brief Reverse byte order (16 bit)
786 \details Reverses the byte order in two unsigned short values.
787 \param [in] value Value to reverse
788 \return Reversed value
789 */
__REV16(uint32_t value)790 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
791 {
792 uint32_t result;
793
794 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
795 return(result);
796 }
797
798
799 /**
800 \brief Reverse byte order in signed short value
801 \details Reverses the byte order in a signed short value with sign extension to integer.
802 \param [in] value Value to reverse
803 \return Reversed value
804 */
__REVSH(int32_t value)805 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
806 {
807 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
808 return (short)__builtin_bswap16(value);
809 #else
810 int32_t result;
811
812 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
813 return(result);
814 #endif
815 }
816
817
818 /**
819 \brief Rotate Right in unsigned value (32 bit)
820 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
821 \param [in] op1 Value to rotate
822 \param [in] op2 Number of Bits to rotate
823 \return Rotated value
824 */
__ROR(uint32_t op1,uint32_t op2)825 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
826 {
827 return (op1 >> op2) | (op1 << (32U - op2));
828 }
829
830
831 /**
832 \brief Breakpoint
833 \details Causes the processor to enter Debug state.
834 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
835 \param [in] value is ignored by the processor.
836 If required, a debugger can use it to store additional information about the breakpoint.
837 */
838 #define __BKPT(value) __ASM volatile ("bkpt "#value)
839
840
841 /**
842 \brief Reverse bit order of value
843 \details Reverses the bit order of the given value.
844 \param [in] value Value to reverse
845 \return Reversed value
846 */
__RBIT(uint32_t value)847 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
848 {
849 uint32_t result;
850
851 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
852 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
853 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
854 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
855 #else
856 int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
857
858 result = value; /* r will be reversed bits of v; first get LSB of v */
859 for (value >>= 1U; value; value >>= 1U)
860 {
861 result <<= 1U;
862 result |= value & 1U;
863 s--;
864 }
865 result <<= s; /* shift when v's highest bits are zero */
866 #endif
867 return(result);
868 }
869
870
871 /**
872 \brief Count leading zeros
873 \details Counts the number of leading zeros of a data value.
874 \param [in] value Value to count the leading zeros
875 \return number of leading zeros in value
876 */
877 #define __CLZ __builtin_clz
878
879
880 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
881 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
882 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
883 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
884 /**
885 \brief LDR Exclusive (8 bit)
886 \details Executes a exclusive LDR instruction for 8 bit value.
887 \param [in] ptr Pointer to data
888 \return value of type uint8_t at (*ptr)
889 */
__LDREXB(volatile uint8_t * addr)890 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
891 {
892 uint32_t result;
893
894 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
895 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
896 #else
897 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
898 accepted by assembler. So has to use following less efficient pattern.
899 */
900 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
901 #endif
902 return ((uint8_t) result); /* Add explicit type cast here */
903 }
904
905
906 /**
907 \brief LDR Exclusive (16 bit)
908 \details Executes a exclusive LDR instruction for 16 bit values.
909 \param [in] ptr Pointer to data
910 \return value of type uint16_t at (*ptr)
911 */
__LDREXH(volatile uint16_t * addr)912 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
913 {
914 uint32_t result;
915
916 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
917 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
918 #else
919 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
920 accepted by assembler. So has to use following less efficient pattern.
921 */
922 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
923 #endif
924 return ((uint16_t) result); /* Add explicit type cast here */
925 }
926
927
928 /**
929 \brief LDR Exclusive (32 bit)
930 \details Executes a exclusive LDR instruction for 32 bit values.
931 \param [in] ptr Pointer to data
932 \return value of type uint32_t at (*ptr)
933 */
__LDREXW(volatile uint32_t * addr)934 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
935 {
936 uint32_t result;
937
938 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
939 return(result);
940 }
941
942
943 /**
944 \brief STR Exclusive (8 bit)
945 \details Executes a exclusive STR instruction for 8 bit values.
946 \param [in] value Value to store
947 \param [in] ptr Pointer to location
948 \return 0 Function succeeded
949 \return 1 Function failed
950 */
__STREXB(uint8_t value,volatile uint8_t * addr)951 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
952 {
953 uint32_t result;
954
955 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
956 return(result);
957 }
958
959
960 /**
961 \brief STR Exclusive (16 bit)
962 \details Executes a exclusive STR instruction for 16 bit values.
963 \param [in] value Value to store
964 \param [in] ptr Pointer to location
965 \return 0 Function succeeded
966 \return 1 Function failed
967 */
__STREXH(uint16_t value,volatile uint16_t * addr)968 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
969 {
970 uint32_t result;
971
972 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
973 return(result);
974 }
975
976
977 /**
978 \brief STR Exclusive (32 bit)
979 \details Executes a exclusive STR instruction for 32 bit values.
980 \param [in] value Value to store
981 \param [in] ptr Pointer to location
982 \return 0 Function succeeded
983 \return 1 Function failed
984 */
__STREXW(uint32_t value,volatile uint32_t * addr)985 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
986 {
987 uint32_t result;
988
989 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
990 return(result);
991 }
992
993
994 /**
995 \brief Remove the exclusive lock
996 \details Removes the exclusive lock which is created by LDREX.
997 */
__CLREX(void)998 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
999 {
1000 __ASM volatile ("clrex" ::: "memory");
1001 }
1002
1003 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1004 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1005 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1006 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1007
1008
1009 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1010 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1011 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
1012 /**
1013 \brief Signed Saturate
1014 \details Saturates a signed value.
1015 \param [in] value Value to be saturated
1016 \param [in] sat Bit position to saturate to (1..32)
1017 \return Saturated value
1018 */
1019 #define __SSAT(ARG1,ARG2) \
1020 ({ \
1021 int32_t __RES, __ARG1 = (ARG1); \
1022 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1023 __RES; \
1024 })
1025
1026
1027 /**
1028 \brief Unsigned Saturate
1029 \details Saturates an unsigned value.
1030 \param [in] value Value to be saturated
1031 \param [in] sat Bit position to saturate to (0..31)
1032 \return Saturated value
1033 */
1034 #define __USAT(ARG1,ARG2) \
1035 ({ \
1036 uint32_t __RES, __ARG1 = (ARG1); \
1037 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1038 __RES; \
1039 })
1040
1041
1042 /**
1043 \brief Rotate Right with Extend (32 bit)
1044 \details Moves each bit of a bitstring right by one bit.
1045 The carry input is shifted in at the left end of the bitstring.
1046 \param [in] value Value to rotate
1047 \return Rotated value
1048 */
__RRX(uint32_t value)1049 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
1050 {
1051 uint32_t result;
1052
1053 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
1054 return(result);
1055 }
1056
1057
1058 /**
1059 \brief LDRT Unprivileged (8 bit)
1060 \details Executes a Unprivileged LDRT instruction for 8 bit value.
1061 \param [in] ptr Pointer to data
1062 \return value of type uint8_t at (*ptr)
1063 */
__LDRBT(volatile uint8_t * ptr)1064 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
1065 {
1066 uint32_t result;
1067
1068 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1069 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
1070 #else
1071 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
1072 accepted by assembler. So has to use following less efficient pattern.
1073 */
1074 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
1075 #endif
1076 return ((uint8_t) result); /* Add explicit type cast here */
1077 }
1078
1079
1080 /**
1081 \brief LDRT Unprivileged (16 bit)
1082 \details Executes a Unprivileged LDRT instruction for 16 bit values.
1083 \param [in] ptr Pointer to data
1084 \return value of type uint16_t at (*ptr)
1085 */
__LDRHT(volatile uint16_t * ptr)1086 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
1087 {
1088 uint32_t result;
1089
1090 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1091 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
1092 #else
1093 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
1094 accepted by assembler. So has to use following less efficient pattern.
1095 */
1096 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
1097 #endif
1098 return ((uint16_t) result); /* Add explicit type cast here */
1099 }
1100
1101
1102 /**
1103 \brief LDRT Unprivileged (32 bit)
1104 \details Executes a Unprivileged LDRT instruction for 32 bit values.
1105 \param [in] ptr Pointer to data
1106 \return value of type uint32_t at (*ptr)
1107 */
__LDRT(volatile uint32_t * ptr)1108 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
1109 {
1110 uint32_t result;
1111
1112 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
1113 return(result);
1114 }
1115
1116
1117 /**
1118 \brief STRT Unprivileged (8 bit)
1119 \details Executes a Unprivileged STRT instruction for 8 bit values.
1120 \param [in] value Value to store
1121 \param [in] ptr Pointer to location
1122 */
__STRBT(uint8_t value,volatile uint8_t * ptr)1123 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
1124 {
1125 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1126 }
1127
1128
1129 /**
1130 \brief STRT Unprivileged (16 bit)
1131 \details Executes a Unprivileged STRT instruction for 16 bit values.
1132 \param [in] value Value to store
1133 \param [in] ptr Pointer to location
1134 */
__STRHT(uint16_t value,volatile uint16_t * ptr)1135 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
1136 {
1137 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1138 }
1139
1140
1141 /**
1142 \brief STRT Unprivileged (32 bit)
1143 \details Executes a Unprivileged STRT instruction for 32 bit values.
1144 \param [in] value Value to store
1145 \param [in] ptr Pointer to location
1146 */
__STRT(uint32_t value,volatile uint32_t * ptr)1147 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
1148 {
1149 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
1150 }
1151
1152 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1153 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1154 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
1155
1156
1157 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1158 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
1159 /**
1160 \brief Load-Acquire (8 bit)
1161 \details Executes a LDAB instruction for 8 bit value.
1162 \param [in] ptr Pointer to data
1163 \return value of type uint8_t at (*ptr)
1164 */
__LDAB(volatile uint8_t * ptr)1165 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
1166 {
1167 uint32_t result;
1168
1169 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
1170 return ((uint8_t) result);
1171 }
1172
1173
1174 /**
1175 \brief Load-Acquire (16 bit)
1176 \details Executes a LDAH instruction for 16 bit values.
1177 \param [in] ptr Pointer to data
1178 \return value of type uint16_t at (*ptr)
1179 */
__LDAH(volatile uint16_t * ptr)1180 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
1181 {
1182 uint32_t result;
1183
1184 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
1185 return ((uint16_t) result);
1186 }
1187
1188
1189 /**
1190 \brief Load-Acquire (32 bit)
1191 \details Executes a LDA instruction for 32 bit values.
1192 \param [in] ptr Pointer to data
1193 \return value of type uint32_t at (*ptr)
1194 */
__LDA(volatile uint32_t * ptr)1195 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
1196 {
1197 uint32_t result;
1198
1199 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
1200 return(result);
1201 }
1202
1203
1204 /**
1205 \brief Store-Release (8 bit)
1206 \details Executes a STLB instruction for 8 bit values.
1207 \param [in] value Value to store
1208 \param [in] ptr Pointer to location
1209 */
__STLB(uint8_t value,volatile uint8_t * ptr)1210 __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
1211 {
1212 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1213 }
1214
1215
1216 /**
1217 \brief Store-Release (16 bit)
1218 \details Executes a STLH instruction for 16 bit values.
1219 \param [in] value Value to store
1220 \param [in] ptr Pointer to location
1221 */
__STLH(uint16_t value,volatile uint16_t * ptr)1222 __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
1223 {
1224 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1225 }
1226
1227
1228 /**
1229 \brief Store-Release (32 bit)
1230 \details Executes a STL instruction for 32 bit values.
1231 \param [in] value Value to store
1232 \param [in] ptr Pointer to location
1233 */
__STL(uint32_t value,volatile uint32_t * ptr)1234 __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
1235 {
1236 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1237 }
1238
1239
1240 /**
1241 \brief Load-Acquire Exclusive (8 bit)
1242 \details Executes a LDAB exclusive instruction for 8 bit value.
1243 \param [in] ptr Pointer to data
1244 \return value of type uint8_t at (*ptr)
1245 */
__LDAEXB(volatile uint8_t * ptr)1246 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
1247 {
1248 uint32_t result;
1249
1250 __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
1251 return ((uint8_t) result);
1252 }
1253
1254
1255 /**
1256 \brief Load-Acquire Exclusive (16 bit)
1257 \details Executes a LDAH exclusive instruction for 16 bit values.
1258 \param [in] ptr Pointer to data
1259 \return value of type uint16_t at (*ptr)
1260 */
__LDAEXH(volatile uint16_t * ptr)1261 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
1262 {
1263 uint32_t result;
1264
1265 __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
1266 return ((uint16_t) result);
1267 }
1268
1269
1270 /**
1271 \brief Load-Acquire Exclusive (32 bit)
1272 \details Executes a LDA exclusive instruction for 32 bit values.
1273 \param [in] ptr Pointer to data
1274 \return value of type uint32_t at (*ptr)
1275 */
__LDAEX(volatile uint32_t * ptr)1276 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
1277 {
1278 uint32_t result;
1279
1280 __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
1281 return(result);
1282 }
1283
1284
1285 /**
1286 \brief Store-Release Exclusive (8 bit)
1287 \details Executes a STLB exclusive instruction for 8 bit values.
1288 \param [in] value Value to store
1289 \param [in] ptr Pointer to location
1290 \return 0 Function succeeded
1291 \return 1 Function failed
1292 */
__STLEXB(uint8_t value,volatile uint8_t * ptr)1293 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
1294 {
1295 uint32_t result;
1296
1297 __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
1298 return(result);
1299 }
1300
1301
1302 /**
1303 \brief Store-Release Exclusive (16 bit)
1304 \details Executes a STLH exclusive instruction for 16 bit values.
1305 \param [in] value Value to store
1306 \param [in] ptr Pointer to location
1307 \return 0 Function succeeded
1308 \return 1 Function failed
1309 */
__STLEXH(uint16_t value,volatile uint16_t * ptr)1310 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
1311 {
1312 uint32_t result;
1313
1314 __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
1315 return(result);
1316 }
1317
1318
1319 /**
1320 \brief Store-Release Exclusive (32 bit)
1321 \details Executes a STL exclusive instruction for 32 bit values.
1322 \param [in] value Value to store
1323 \param [in] ptr Pointer to location
1324 \return 0 Function succeeded
1325 \return 1 Function failed
1326 */
__STLEX(uint32_t value,volatile uint32_t * ptr)1327 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
1328 {
1329 uint32_t result;
1330
1331 __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
1332 return(result);
1333 }
1334
1335 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1336 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1337
1338 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
1339
1340
1341 /* ################### Compiler specific Intrinsics ########################### */
1342 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
1343 Access to dedicated SIMD instructions
1344 @{
1345 */
1346
1347 #if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
1348
__SADD8(uint32_t op1,uint32_t op2)1349 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
1350 {
1351 uint32_t result;
1352
1353 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1354 return(result);
1355 }
1356
__QADD8(uint32_t op1,uint32_t op2)1357 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
1358 {
1359 uint32_t result;
1360
1361 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1362 return(result);
1363 }
1364
__SHADD8(uint32_t op1,uint32_t op2)1365 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
1366 {
1367 uint32_t result;
1368
1369 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1370 return(result);
1371 }
1372
__UADD8(uint32_t op1,uint32_t op2)1373 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
1374 {
1375 uint32_t result;
1376
1377 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1378 return(result);
1379 }
1380
__UQADD8(uint32_t op1,uint32_t op2)1381 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
1382 {
1383 uint32_t result;
1384
1385 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1386 return(result);
1387 }
1388
__UHADD8(uint32_t op1,uint32_t op2)1389 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
1390 {
1391 uint32_t result;
1392
1393 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1394 return(result);
1395 }
1396
1397
__SSUB8(uint32_t op1,uint32_t op2)1398 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
1399 {
1400 uint32_t result;
1401
1402 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1403 return(result);
1404 }
1405
__QSUB8(uint32_t op1,uint32_t op2)1406 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
1407 {
1408 uint32_t result;
1409
1410 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1411 return(result);
1412 }
1413
__SHSUB8(uint32_t op1,uint32_t op2)1414 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
1415 {
1416 uint32_t result;
1417
1418 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1419 return(result);
1420 }
1421
__USUB8(uint32_t op1,uint32_t op2)1422 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
1423 {
1424 uint32_t result;
1425
1426 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1427 return(result);
1428 }
1429
__UQSUB8(uint32_t op1,uint32_t op2)1430 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
1431 {
1432 uint32_t result;
1433
1434 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1435 return(result);
1436 }
1437
__UHSUB8(uint32_t op1,uint32_t op2)1438 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
1439 {
1440 uint32_t result;
1441
1442 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1443 return(result);
1444 }
1445
1446
__SADD16(uint32_t op1,uint32_t op2)1447 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
1448 {
1449 uint32_t result;
1450
1451 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1452 return(result);
1453 }
1454
__QADD16(uint32_t op1,uint32_t op2)1455 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
1456 {
1457 uint32_t result;
1458
1459 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1460 return(result);
1461 }
1462
__SHADD16(uint32_t op1,uint32_t op2)1463 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
1464 {
1465 uint32_t result;
1466
1467 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1468 return(result);
1469 }
1470
__UADD16(uint32_t op1,uint32_t op2)1471 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
1472 {
1473 uint32_t result;
1474
1475 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1476 return(result);
1477 }
1478
__UQADD16(uint32_t op1,uint32_t op2)1479 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
1480 {
1481 uint32_t result;
1482
1483 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1484 return(result);
1485 }
1486
__UHADD16(uint32_t op1,uint32_t op2)1487 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
1488 {
1489 uint32_t result;
1490
1491 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1492 return(result);
1493 }
1494
__SSUB16(uint32_t op1,uint32_t op2)1495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
1496 {
1497 uint32_t result;
1498
1499 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1500 return(result);
1501 }
1502
__QSUB16(uint32_t op1,uint32_t op2)1503 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
1504 {
1505 uint32_t result;
1506
1507 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1508 return(result);
1509 }
1510
__SHSUB16(uint32_t op1,uint32_t op2)1511 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
1512 {
1513 uint32_t result;
1514
1515 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1516 return(result);
1517 }
1518
__USUB16(uint32_t op1,uint32_t op2)1519 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
1520 {
1521 uint32_t result;
1522
1523 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1524 return(result);
1525 }
1526
__UQSUB16(uint32_t op1,uint32_t op2)1527 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
1528 {
1529 uint32_t result;
1530
1531 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1532 return(result);
1533 }
1534
__UHSUB16(uint32_t op1,uint32_t op2)1535 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
1536 {
1537 uint32_t result;
1538
1539 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1540 return(result);
1541 }
1542
__SASX(uint32_t op1,uint32_t op2)1543 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
1544 {
1545 uint32_t result;
1546
1547 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1548 return(result);
1549 }
1550
__QASX(uint32_t op1,uint32_t op2)1551 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
1552 {
1553 uint32_t result;
1554
1555 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1556 return(result);
1557 }
1558
__SHASX(uint32_t op1,uint32_t op2)1559 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
1560 {
1561 uint32_t result;
1562
1563 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1564 return(result);
1565 }
1566
__UASX(uint32_t op1,uint32_t op2)1567 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
1568 {
1569 uint32_t result;
1570
1571 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1572 return(result);
1573 }
1574
__UQASX(uint32_t op1,uint32_t op2)1575 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
1576 {
1577 uint32_t result;
1578
1579 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1580 return(result);
1581 }
1582
__UHASX(uint32_t op1,uint32_t op2)1583 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
1584 {
1585 uint32_t result;
1586
1587 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1588 return(result);
1589 }
1590
__SSAX(uint32_t op1,uint32_t op2)1591 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
1592 {
1593 uint32_t result;
1594
1595 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1596 return(result);
1597 }
1598
__QSAX(uint32_t op1,uint32_t op2)1599 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
1600 {
1601 uint32_t result;
1602
1603 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1604 return(result);
1605 }
1606
__SHSAX(uint32_t op1,uint32_t op2)1607 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
1608 {
1609 uint32_t result;
1610
1611 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1612 return(result);
1613 }
1614
__USAX(uint32_t op1,uint32_t op2)1615 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
1616 {
1617 uint32_t result;
1618
1619 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1620 return(result);
1621 }
1622
__UQSAX(uint32_t op1,uint32_t op2)1623 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
1624 {
1625 uint32_t result;
1626
1627 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1628 return(result);
1629 }
1630
__UHSAX(uint32_t op1,uint32_t op2)1631 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
1632 {
1633 uint32_t result;
1634
1635 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1636 return(result);
1637 }
1638
__USAD8(uint32_t op1,uint32_t op2)1639 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
1640 {
1641 uint32_t result;
1642
1643 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1644 return(result);
1645 }
1646
__USADA8(uint32_t op1,uint32_t op2,uint32_t op3)1647 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
1648 {
1649 uint32_t result;
1650
1651 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1652 return(result);
1653 }
1654
1655 #define __SSAT16(ARG1,ARG2) \
1656 ({ \
1657 int32_t __RES, __ARG1 = (ARG1); \
1658 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1659 __RES; \
1660 })
1661
1662 #define __USAT16(ARG1,ARG2) \
1663 ({ \
1664 uint32_t __RES, __ARG1 = (ARG1); \
1665 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1666 __RES; \
1667 })
1668
__UXTB16(uint32_t op1)1669 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
1670 {
1671 uint32_t result;
1672
1673 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
1674 return(result);
1675 }
1676
__UXTAB16(uint32_t op1,uint32_t op2)1677 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
1678 {
1679 uint32_t result;
1680
1681 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1682 return(result);
1683 }
1684
__SXTB16(uint32_t op1)1685 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
1686 {
1687 uint32_t result;
1688
1689 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
1690 return(result);
1691 }
1692
__SXTAB16(uint32_t op1,uint32_t op2)1693 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
1694 {
1695 uint32_t result;
1696
1697 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1698 return(result);
1699 }
1700
__SMUAD(uint32_t op1,uint32_t op2)1701 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
1702 {
1703 uint32_t result;
1704
1705 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1706 return(result);
1707 }
1708
__SMUADX(uint32_t op1,uint32_t op2)1709 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
1710 {
1711 uint32_t result;
1712
1713 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1714 return(result);
1715 }
1716
__SMLAD(uint32_t op1,uint32_t op2,uint32_t op3)1717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
1718 {
1719 uint32_t result;
1720
1721 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1722 return(result);
1723 }
1724
__SMLADX(uint32_t op1,uint32_t op2,uint32_t op3)1725 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
1726 {
1727 uint32_t result;
1728
1729 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1730 return(result);
1731 }
1732
__SMLALD(uint32_t op1,uint32_t op2,uint64_t acc)1733 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
1734 {
1735 union llreg_u{
1736 uint32_t w32[2];
1737 uint64_t w64;
1738 } llr;
1739 llr.w64 = acc;
1740
1741 #ifndef __ARMEB__ /* Little endian */
1742 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1743 #else /* Big endian */
1744 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1745 #endif
1746
1747 return(llr.w64);
1748 }
1749
__SMLALDX(uint32_t op1,uint32_t op2,uint64_t acc)1750 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
1751 {
1752 union llreg_u{
1753 uint32_t w32[2];
1754 uint64_t w64;
1755 } llr;
1756 llr.w64 = acc;
1757
1758 #ifndef __ARMEB__ /* Little endian */
1759 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1760 #else /* Big endian */
1761 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1762 #endif
1763
1764 return(llr.w64);
1765 }
1766
__SMUSD(uint32_t op1,uint32_t op2)1767 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
1768 {
1769 uint32_t result;
1770
1771 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1772 return(result);
1773 }
1774
__SMUSDX(uint32_t op1,uint32_t op2)1775 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
1776 {
1777 uint32_t result;
1778
1779 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1780 return(result);
1781 }
1782
__SMLSD(uint32_t op1,uint32_t op2,uint32_t op3)1783 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
1784 {
1785 uint32_t result;
1786
1787 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1788 return(result);
1789 }
1790
__SMLSDX(uint32_t op1,uint32_t op2,uint32_t op3)1791 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
1792 {
1793 uint32_t result;
1794
1795 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1796 return(result);
1797 }
1798
__SMLSLD(uint32_t op1,uint32_t op2,uint64_t acc)1799 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
1800 {
1801 union llreg_u{
1802 uint32_t w32[2];
1803 uint64_t w64;
1804 } llr;
1805 llr.w64 = acc;
1806
1807 #ifndef __ARMEB__ /* Little endian */
1808 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1809 #else /* Big endian */
1810 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1811 #endif
1812
1813 return(llr.w64);
1814 }
1815
__SMLSLDX(uint32_t op1,uint32_t op2,uint64_t acc)1816 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
1817 {
1818 union llreg_u{
1819 uint32_t w32[2];
1820 uint64_t w64;
1821 } llr;
1822 llr.w64 = acc;
1823
1824 #ifndef __ARMEB__ /* Little endian */
1825 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1826 #else /* Big endian */
1827 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1828 #endif
1829
1830 return(llr.w64);
1831 }
1832
__SEL(uint32_t op1,uint32_t op2)1833 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
1834 {
1835 uint32_t result;
1836
1837 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1838 return(result);
1839 }
1840
__QADD(int32_t op1,int32_t op2)1841 __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
1842 {
1843 int32_t result;
1844
1845 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1846 return(result);
1847 }
1848
__QSUB(int32_t op1,int32_t op2)1849 __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
1850 {
1851 int32_t result;
1852
1853 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1854 return(result);
1855 }
1856
1857 #if 0
1858 #define __PKHBT(ARG1,ARG2,ARG3) \
1859 ({ \
1860 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
1861 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
1862 __RES; \
1863 })
1864
1865 #define __PKHTB(ARG1,ARG2,ARG3) \
1866 ({ \
1867 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
1868 if (ARG3 == 0) \
1869 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
1870 else \
1871 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
1872 __RES; \
1873 })
1874 #endif
1875
1876 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
1877 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
1878
1879 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
1880 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
1881
__SMMLA(int32_t op1,int32_t op2,int32_t op3)1882 __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
1883 {
1884 int32_t result;
1885
1886 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
1887 return(result);
1888 }
1889
1890 #endif /* (__ARM_FEATURE_DSP == 1) */
1891 /*@} end of group CMSIS_SIMD_intrinsics */
1892
1893
1894 #pragma GCC diagnostic pop
1895
1896 #endif /* __CMSIS_GCC_H */
1897