1 /**************************************************************************//** 2 * @file mpu_config.c 3 * @brief Defines macros for the MPU configuration for the Secure region. 4 * 5 * @version V1.00 6 * @date 2017-03-21 7 * 8 * @note 9 * 10 ****************************************************************************** 11 * 12 * Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. 13 * 14 * SPDX-License-Identifier: Apache-2.0 15 * 16 * Licensed under the Apache License, Version 2.0 (the License); you may 17 * not use this file except in compliance with the License. 18 * You may obtain a copy of the License at 19 * 20 * http://www.apache.org/licenses/LICENSE-2.0 21 * 22 * Unless required by applicable law or agreed to in writing, software 23 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 24 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 * See the License for the specific language governing permissions and 26 * limitations under the License. 27 * 28 ******************************************************************************/ 29 30 #ifndef _MPU_CONFIG_S_H_ 31 #define _MPU_CONFIG_S_H_ 32 33 #include "mpu.h" 34 35 /** @defgroup mpu_config_define 36 * @{ 37 * note: MPU_INIT_CTRL_ENABLE 38 * <q> Enable MPU 39 * <i> Value for MPU->CTRL register bit ENABLE 40 * <0=> MPU is disabled. 41 * <1=> MPU is enabled. 42 * note: MPU_INIT_CTRL_PRIVDEFENA 43 * <i> Value for MPU->CTRL register bit PRIVDEFENA 44 * Privileged background region enable: 45 * <0=> All accesses to unmapped addresses result in faults. 46 * <1=> Enables the default memory map for privilege code when the address accessed 47 * does not map into any MPU region. Unprivileged accesses to unmapped addresses 48 * result in faults. 49 * note: MPU_INIT_CTRL_HFNMIENA 50 * <i> Value for MPU->CTRL register bit HFNMIENA MPU Enable for HardFault and NMI (Non-Maskable Interrupt): 51 * <0=> HardFault and NMI handlers bypass MPU configuration as if MPU is disabled. 52 * <1=> MPU access rules apply to HardFault and NMI handlers. 53 */ 54 #define MPU_INIT_CTRL_ENABLE 1 55 #define MPU_INIT_CTRL_PRIVDEFENA 1 56 #define MPU_INIT_CTRL_HFNMIENA 0 57 /** 58 * @} 59 */ 60 61 /** @defgroup mpu_mem_attri_typical_define 62 * @{ 63 * note: MPU_MEM_ATTR0~MPU_MEM_ATTR7 64 * no cache 65 * write-through + read allocation 66 * write-back + read allocation + write allocation 67 68 * <1=> MPU is enabled. 69 */ 70 #define MPU_MEM_ATTR0 ((NORMAL_NC << 4) | NORMAL_NC) // The memory attribute configuration of the MAIR[Attr0] 71 #define MPU_MEM_ATTR1 ((NORMAL_WT_T_RA << 4) | NORMAL_WT_T_RA) // The memory attribute configuration of the MAIR[Attr1] 72 #define MPU_MEM_ATTR2 ((NORMAL_WB_T_RWA << 4) | NORMAL_WB_T_RWA) // The memory attribute configuration of the MAIR[Attr2] 73 #define MPU_MEM_ATTR3 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr3] 74 #define MPU_MEM_ATTR4 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr4] 75 #define MPU_MEM_ATTR5 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr5] 76 #define MPU_MEM_ATTR6 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr6] 77 #define MPU_MEM_ATTR7 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr7] 78 79 #define MPU_MEM_ATTR_IDX_NC 0 80 #define MPU_MEM_ATTR_IDX_WT_T_RA 1 81 #define MPU_MEM_ATTR_IDX_WB_T_RWA 2 82 #define MPU_MEM_ATTR_IDX_DEVICE 3 83 /** 84 * @} 85 */ 86 87 #endif //_MPU_CONFIG_S_H_ 88 89