1/*
2 * Arm SCP/MCP Software
3 * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#ifndef ASM_MACROS_S
8#define ASM_MACROS_S
9
10#include <common/asm_macros_common.S>
11
12/*
13 * TLBI instruction with type specifier that implements the workaround for
14 * errata 813419 of Cortex-A57.
15 */
16#if ERRATA_A57_813419
17#define TLB_INVALIDATE(_type) \
18    tlbi    _type; \
19    dsb ish; \
20    tlbi    _type
21#else
22#define TLB_INVALIDATE(_type) \
23    tlbi    _type
24#endif
25
26
27    .macro  func_prologue
28    stp x29, x30, [sp, #-0x10]!
29    mov x29,sp
30    .endm
31
32    .macro  func_epilogue
33    ldp x29, x30, [sp], #0x10
34    .endm
35
36
37    .macro  dcache_line_size  reg, tmp
38    mrs \tmp, ctr_el0
39    ubfx    \tmp, \tmp, #16, #4
40    mov \reg, #4
41    lsl \reg, \reg, \tmp
42    .endm
43
44
45    .macro  icache_line_size  reg, tmp
46    mrs \tmp, ctr_el0
47    and \tmp, \tmp, #0xf
48    mov \reg, #4
49    lsl \reg, \reg, \tmp
50    .endm
51
52
53    .macro  smc_check  label
54    mrs x0, esr_el3
55    ubfx    x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
56    cmp x0, #EC_AARCH64_SMC
57    b.ne    $label
58    .endm
59
60    /*
61     * Declare the exception vector table, enforcing it is aligned on a
62     * 2KB boundary, as required by the ARMv8 architecture.
63     * Use zero bytes as the fill value to be stored in the padding bytes
64     * so that it inserts illegal AArch64 instructions. This increases
65     * security, robustness and potentially facilitates debugging.
66     */
67    .macro vector_base  label, section_name=.vectors
68    .section \section_name, "ax"
69    .align 11, 0
70    \label:
71    .endm
72
73    /*
74     * Create an entry in the exception vector table, enforcing it is
75     * aligned on a 128-byte boundary, as required by the ARMv8 architecture.
76     * Use zero bytes as the fill value to be stored in the padding bytes
77     * so that it inserts illegal AArch64 instructions. This increases
78     * security, robustness and potentially facilitates debugging.
79     */
80    .macro vector_entry  label, section_name=.vectors
81    .cfi_sections .debug_frame
82    .section \section_name, "ax"
83    .align 7, 0
84    .type \label, %function
85    .cfi_startproc
86    \label:
87    .endm
88
89    /*
90     * Add the bytes until fill the full exception vector, whose size is always
91     * 32 instructions. If there are more than 32 instructions in the
92     * exception vector then an error is emitted.
93     */
94    .macro end_vector_entry label
95    .cfi_endproc
96    .fill   \label + (32 * 4) - .
97    .endm
98
99    /*
100     * This macro calculates the base address of the current CPU's MP stack
101     * using the plat_my_core_pos() index, the name of the stack storage
102     * and the size of each stack
103     * Out: X0 = physical address of stack base
104     * Clobber: X30, X1, X2
105     */
106    .macro get_my_mp_stack _name, _size
107    bl  plat_my_core_pos
108    adrp    x2, (\_name + \_size)
109    add x2, x2, :lo12:(\_name + \_size)
110    mov x1, #\_size
111    madd x0, x0, x1, x2
112    .endm
113
114    /*
115     * This macro calculates the base address of a UP stack using the
116     * name of the stack storage and the size of the stack
117     * Out: X0 = physical address of stack base
118     */
119    .macro get_up_stack _name, _size
120    adrp    x0, (\_name + \_size)
121    add x0, x0, :lo12:(\_name + \_size)
122    .endm
123
124    /*
125     * Helper macro to generate the best mov/movk combinations according
126     * the value to be moved. The 16 bits from '_shift' are tested and
127     * if not zero, they are moved into '_reg' without affecting
128     * other bits.
129     */
130    .macro _mov_imm16 _reg, _val, _shift
131        .if (\_val >> \_shift) & 0xffff
132            .if (\_val & (1 << \_shift - 1))
133                movk    \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift
134            .else
135                mov \_reg, \_val & (0xffff << \_shift)
136            .endif
137        .endif
138    .endm
139
140    /*
141     * Helper macro to load arbitrary values into 32 or 64-bit registers
142     * which generates the best mov/movk combinations. Many base addresses
143     * are 64KB aligned the macro will eliminate updating bits 15:0 in
144     * that case
145     */
146    .macro mov_imm _reg, _val
147        .if (\_val) == 0
148            mov \_reg, #0
149        .else
150            _mov_imm16  \_reg, (\_val), 0
151            _mov_imm16  \_reg, (\_val), 16
152            _mov_imm16  \_reg, (\_val), 32
153            _mov_imm16  \_reg, (\_val), 48
154        .endif
155    .endm
156
157    /*
158     * Macro to mark instances where we're jumping to a function and don't
159     * expect a return. To provide the function being jumped to with
160     * additional information, we use 'bl' instruction to jump rather than
161     * 'b'.
162         *
163     * Debuggers infer the location of a call from where LR points to, which
164     * is usually the instruction after 'bl'. If this macro expansion
165     * happens to be the last location in a function, that'll cause the LR
166     * to point a location beyond the function, thereby misleading debugger
167     * back trace. We therefore insert a 'nop' after the function call for
168     * debug builds, unless 'skip_nop' parameter is non-zero.
169     */
170    .macro no_ret _func:req, skip_nop=0
171    bl  \_func
172#if DEBUG
173    .ifeq \skip_nop
174    nop
175    .endif
176#endif
177    .endm
178
179    /*
180     * Reserve space for a spin lock in assembly file.
181     */
182    .macro define_asm_spinlock _name:req
183    .align  SPINLOCK_ASM_ALIGN
184    \_name:
185    .space  SPINLOCK_ASM_SIZE
186    .endm
187
188#if RAS_EXTENSION
189    .macro esb
190    .inst   0xd503221f
191    .endm
192#endif
193
194#endif /* ASM_MACROS_S */
195