1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * Definitions and utility functions for the CMN600 module. 9 */ 10 11 /* The use of "manager" may not be in sync with older versions of TRM */ 12 13 #ifndef CMN600_H 14 #define CMN600_H 15 16 #include <fwk_macros.h> 17 18 #include <stdbool.h> 19 #include <stdint.h> 20 21 #define CMN600_MAX_NUM_RNF 32 22 #define CMN600_MAX_NUM_HNF 32 23 #define CMN600_MAX_NUM_SCG 4 24 25 #define SAM_GRANULARITY (64 * FWK_MIB) 26 27 enum node_id_size { 28 NODE_ID_SIZE_7BITS, 29 NODE_ID_SIZE_9BITS, 30 }; 31 32 enum node_type { 33 NODE_TYPE_INVALID = 0x0, 34 NODE_TYPE_DVM = 0x1, 35 NODE_TYPE_CFG = 0x2, 36 NODE_TYPE_DTC = 0x3, 37 NODE_TYPE_HN_I = 0x4, 38 NODE_TYPE_HN_F = 0x5, 39 NODE_TYPE_XP = 0x6, 40 NODE_TYPE_SBSX = 0x7, 41 NODE_TYPE_RN_I = 0xA, 42 NODE_TYPE_RN_D = 0xD, 43 NODE_TYPE_RN_SAM = 0xF, 44 /* Coherent Multichip Link (CML) node types */ 45 NODE_TYPE_CML_BASE = 0x100, 46 NODE_TYPE_CXRA = 0x100, 47 NODE_TYPE_CXHA = 0x101, 48 NODE_TYPE_CXLA = 0x102, 49 }; 50 51 enum device_type { 52 DEVICE_TYPE_CXHA = 0x11, // 0b10001 53 DEVICE_TYPE_CXRA = 0x12, // 0b10010 54 DEVICE_TYPE_CXRH = 0x13, // 0b10011 55 }; 56 57 /* Common node header */ 58 struct node_header { 59 FWK_R uint64_t NODE_INFO; 60 uint8_t RESERVED0[0x80 - 0x8]; 61 FWK_R uint64_t CHILD_INFO; 62 uint8_t RESERVED1[0x100 - 0x88]; 63 FWK_R uint64_t CHILD_POINTER[256]; 64 }; 65 66 struct cluster_mapping { 67 unsigned int node_id; 68 struct node_header *node; 69 }; 70 71 enum sam_node_type { 72 SAM_NODE_TYPE_HN_F = 0, 73 SAM_NODE_TYPE_HN_I = 1, 74 SAM_NODE_TYPE_CXRA = 2, 75 SAM_NODE_TYPE_COUNT 76 }; 77 78 /* 79 * Request Node System Address Map (RN-SAM) registers 80 */ 81 struct cmn600_rnsam_reg { 82 FWK_R uint64_t NODE_INFO; 83 uint8_t RESERVED0[0x80 - 0x8]; 84 FWK_R uint64_t CHILD_INFO; 85 uint8_t RESERVED1[0x900 - 0x88]; 86 FWK_R uint64_t UNIT_INFO; 87 uint8_t RESERVED2[0x980 - 0x908]; 88 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 89 uint8_t RESERVED3[0xC00 - 0x988]; 90 FWK_RW uint64_t STATUS; 91 FWK_RW uint64_t NON_HASH_MEM_REGION[5]; 92 FWK_RW uint64_t NON_HASH_TGT_NODEID[3]; 93 FWK_RW uint64_t SYS_CACHE_GRP_REGION[2]; 94 FWK_RW uint64_t SYS_CACHE_GRP_HN_NODEID[8]; 95 FWK_RW uint64_t SYS_CACHE_GRP_NOHASH_NODEID; 96 uint8_t RESERVED4[0xCE0 - 0xCA0]; 97 FWK_RW uint64_t NON_HASH_TGT_NODEID_GRP2[2]; 98 uint8_t RESERVED5[0xD00 - 0xCF0]; 99 FWK_RW uint64_t SYS_CACHE_GRP_HN_COUNT; 100 FWK_RW uint64_t SYS_CACHE_GRP_SN_NODEID[8]; 101 FWK_RW uint64_t SYS_CACHE_GRP_SN_SAM_CFG[2]; 102 uint8_t RESERVED6[0xF10 - 0xD58]; 103 FWK_RW uint64_t SYS_CACHE_GRP_CAL_MODE; 104 }; 105 106 /* 107 * Debug and Trace registers 108 */ 109 struct cmn600_dt_reg { 110 FWK_R uint64_t NODE_INFO; 111 uint8_t RESERVED0[0x80 - 0x8]; 112 FWK_R uint64_t CHILD_INFO; 113 uint8_t RESERVED1[0x980 - 0x88]; 114 FWK_RW uint64_t SECURE_ACCESS; 115 uint8_t RESERVED2[0xA00 - 0x988]; 116 FWK_RW uint64_t DTC_CTL; 117 uint8_t RESERVED3[0xA10 - 0xA08]; 118 FWK_R uint64_t TRIGGER_STATUS; 119 uint8_t RESERVED4[0xA20 - 0xA18]; 120 FWK_W uint64_t TRIGGER_STATUS_CLR; 121 uint8_t RESERVED5[0xA30 - 0xA28]; 122 FWK_RW uint64_t TRACE_CONTROL; 123 uint8_t RESERVED6[0xA40 - 0xA38]; 124 FWK_R uint64_t DBG_ID; 125 FWK_RW uint64_t TRACE_ID; 126 uint8_t RESERVED7[0x2000 - 0xA50]; 127 FWK_RW uint64_t PMEVCNT[8]; 128 FWK_RW uint64_t PMCCNTR; 129 uint8_t RESERVED8[0x2050 - 0x2048]; 130 FWK_RW uint64_t PMEVCNTSR[8]; 131 FWK_RW uint64_t PMCCNTRSR; 132 uint8_t RESERVED9[0x2100 - 0x2098]; 133 FWK_RW uint64_t PMCR; 134 FWK_RW uint64_t PMEVCNT_LOCALNUM; 135 uint8_t RESERVED10[0x2118 - 0x2110]; 136 FWK_R uint64_t PMOVSR; 137 FWK_W uint64_t PMOVSR_CLR; 138 FWK_R uint64_t PMSR; 139 FWK_W uint64_t PMSR_REQ; 140 FWK_W uint64_t PMSR_CLR; 141 uint8_t RESERVED11[0x2DA0 - 0x2140]; 142 FWK_RW uint64_t CLAIM; 143 FWK_R uint64_t DEVAFF; 144 FWK_R uint64_t LSR; 145 FWK_R uint64_t AUTHSTATUS_DEVARCH; 146 FWK_R uint64_t DEVID; 147 FWK_R uint64_t DEVTYPE; 148 FWK_R uint64_t PIDR45; 149 FWK_R uint64_t PIDR67; 150 FWK_R uint64_t PIDR01; 151 FWK_R uint64_t PIDR23; 152 FWK_R uint64_t CIDR01; 153 FWK_R uint64_t CIDR23; 154 }; 155 156 /* 157 * Device Node registers 158 */ 159 struct cmn600_dn_reg { 160 FWK_R uint64_t NODE_INFO; 161 uint8_t RESERVED0[0x80 - 0x8]; 162 FWK_R uint64_t CHILD_INFO; 163 uint8_t RESERVED1[0x900 - 0x88]; 164 FWK_R uint64_t BUILD_INFO; 165 uint8_t RESERVED2[0x980 - 0x908]; 166 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 167 uint8_t RESERVED3[0xA00 - 0x988]; 168 FWK_RW uint64_t AUX_CTL; 169 uint8_t RESERVED4[0xC00 - 0xA08]; 170 FWK_RW uint64_t VMF0_CTRL; 171 FWK_RW uint64_t VMF0_RNF[4]; 172 uint8_t RESERVED5[0xC40 - 0xC28]; 173 FWK_RW uint64_t VMF0_RND; 174 uint8_t RESERVED6[0xC60 - 0xC48]; 175 FWK_RW uint64_t VMF0_RNC; 176 uint8_t RESERVED7[0xC80 - 0xC68]; 177 FWK_RW uint64_t VMF1_CTRL; 178 FWK_RW uint64_t VMF1_RNF[4]; 179 uint8_t RESERVED8[0xCC0 - 0xCA8]; 180 FWK_RW uint64_t VMF1_RND; 181 uint8_t RESERVED9[0xCE0 - 0xCC8]; 182 FWK_RW uint64_t VMF1_RNC; 183 uint8_t RESERVED10[0xD00 - 0xCE8]; 184 FWK_RW uint64_t VMF2_CTRL; 185 FWK_RW uint64_t VMF2_RNF[4]; 186 uint8_t RESERVED11[0xD40 - 0xD28]; 187 FWK_RW uint64_t VMF2_RND; 188 uint8_t RESERVED12[0xD60 - 0xD48]; 189 FWK_RW uint64_t VMF2_RNC; 190 uint8_t RESERVED13[0xD80 - 0xD68]; 191 FWK_RW uint64_t VMF3_CTRL; 192 FWK_RW uint64_t VMF3_RNF[4]; 193 uint8_t RESERVED14[0xDC0 - 0xDA8]; 194 FWK_RW uint64_t VMF3_RND; 195 uint8_t RESERVED15[0xDE0 - 0xDC8]; 196 FWK_RW uint64_t VMF3_RNC; 197 uint8_t RESERVED16[0x2000 - 0xDE8]; 198 FWK_RW uint64_t PMU_EVEN_SEL; 199 }; 200 201 202 /* 203 * Quality of Service (QoS) registers 204 */ 205 struct cmn600_qos_reg { 206 FWK_RW uint64_t QOS_CONTROL; 207 FWK_RW uint64_t QOS_LAST_TGT; 208 FWK_RW uint64_t QOS_LAST_SCALE; 209 FWK_RW uint64_t QOS_LAST_RANGE; 210 }; 211 212 /* 213 * Request Node Device (RN-D) registers 214 */ 215 struct cmn600_rnd_reg { 216 FWK_R uint64_t NODE_INFO; 217 uint8_t RESERVED0[0x80 - 0x8]; 218 FWK_R uint64_t CHILD_INFO; 219 uint8_t RESERVED1[0x900 - 0x88]; 220 FWK_R uint64_t UNIT_INFO; 221 uint8_t RESERVED2[0x980 - 0x908]; 222 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 223 uint8_t RESERVED3[0xA00 - 0x988]; 224 FWK_RW uint64_t CFG_CTL; 225 FWK_RW uint64_t AUX_CTL; 226 FWK_RW uint64_t S_PORT_CONTROL[3]; 227 uint8_t RESERVED4[0xA80 - 0xA28]; 228 struct cmn600_qos_reg S_QOS[3]; 229 uint8_t RESERVED5[0x1000 - 0xAE0]; 230 FWK_RW uint64_t SYSCOREQ_CTL; 231 FWK_R uint64_t SYSCOACK_STATUS; 232 uint8_t RESERVED6[0x2000 - 0x1010]; 233 FWK_RW uint64_t PMU_EVENT_SEL; 234 }; 235 236 /* 237 * Fully Coherent Home Node (HN-F) registers 238 */ 239 struct cmn600_hnf_reg { 240 FWK_R uint64_t NODE_INFO; 241 uint8_t RESERVED0[0x80 - 0x8]; 242 FWK_R uint64_t CHILD_INFO; 243 uint8_t RESERVED1[0x900 - 0x88]; 244 FWK_R uint64_t UNIT_INFO; 245 uint8_t RESERVED2[0x980 - 0x908]; 246 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 247 uint8_t RESERVED3[0xA00 - 0x988]; 248 FWK_RW uint64_t CFG_CTL; 249 FWK_RW uint64_t AUX_CTL; 250 uint8_t RESERVED4[0xA80 - 0xA10]; 251 FWK_R uint64_t QOS_BAND; 252 FWK_RW uint64_t QOS_RESERVATION; 253 FWK_RW uint64_t RN_STARVATION; 254 uint8_t RESERVED5[0xB80 - 0xA98]; 255 FWK_W uint64_t CFG_L3SF_DBGRD; 256 FWK_R uint64_t L3_CACHE_ACCESS_L3_TAG; 257 FWK_R uint64_t L3_CACHE_ACCESS_L3_DATA; 258 FWK_R uint64_t L3_CACHE_ACCESS_SF_DATA; 259 uint8_t RESERVED6[0xC00 - 0xBA0]; 260 FWK_RW uint64_t L3_LOCK_WAYS; 261 FWK_RW uint64_t L3_LOCK_BASE[4]; 262 uint8_t RESERVED7[0xC30 - 0xC28]; 263 FWK_RW uint64_t RNID_REGION_VEC; 264 FWK_RW uint64_t RNF_REGION_VEC; 265 uint8_t RESERVED8[0xD00 - 0xC40]; 266 FWK_RW uint64_t SAM_CONTROL; 267 FWK_RW uint64_t SAM_MEMREGION[2]; 268 FWK_RW uint64_t SAM_SN_PROPERTIES; 269 FWK_RW uint64_t SAM_6SN_NODEID; 270 FWK_RW uint64_t RN_PHYS_ID[32]; 271 uint8_t RESERVED9[0xF00 - 0xE28]; 272 FWK_RW uint64_t SF_CXG_BLOCKED_WAYS; 273 uint8_t RESERVED10[0xF10 - 0xF08]; 274 FWK_RW uint64_t CML_PORT_AGGR_GRP0_ADD_MASK; 275 uint8_t RESERVED11[0xF28 - 0xF18]; 276 FWK_RW uint64_t CML_PORT_AGGR_GRP0_ADD_REG; 277 uint8_t RESERVED12[0x1000 - 0xF30]; 278 FWK_RW uint64_t PPU_PWPR; 279 FWK_R uint64_t PPU_PWSR; 280 uint8_t RESERVED13[0x1014 - 0x1010]; 281 FWK_R uint32_t PPU_MISR; 282 uint8_t RESERVED14[0x1100 - 0x1018]; 283 FWK_RW uint64_t PPU_DYN_RET_THRESHOLD; 284 uint8_t RESERVED15[0x1FB0 - 0x1108]; 285 FWK_R uint32_t PPU_IDR[2]; 286 uint8_t RESERVED16[0x1FC8 - 0x1FB8]; 287 FWK_R uint32_t PPU_IIDR; 288 FWK_R uint32_t PPU_AIDR; 289 uint8_t RESERVED17[0x2000 - 0x1FD0]; 290 FWK_RW uint64_t PMU_EVENT_SEL; 291 uint8_t RESERVED18[0x3000 - 0x2008]; 292 FWK_R uint64_t ERRFR; 293 FWK_RW uint64_t ERRCTLR; 294 FWK_RW uint64_t ERRSTATUS; 295 FWK_RW uint64_t ERRADDR; 296 FWK_RW uint64_t ERRMISC; 297 uint8_t RESERVED19[0x3030 - 0x3028]; 298 FWK_RW uint64_t RN_ERR_INJ; 299 FWK_W uint64_t RN_BYTE_PAR_ERR_INJ; 300 uint8_t RESERVED20[0x3100 - 0x3040]; 301 FWK_R uint64_t ERRFR_NS; 302 FWK_RW uint64_t ERRCTLR_NS; 303 FWK_RW uint64_t ERRSTATUS_NS; 304 FWK_RW uint64_t ERRADDR_NS; 305 FWK_RW uint64_t ERRMISC_NS; 306 }; 307 308 /* 309 * AMBA 5 CHI to AXI bridge registers 310 */ 311 struct cmn600_sbsx_reg { 312 FWK_R uint64_t NODE_INFO; 313 uint8_t RESERVED0[0x80 - 0x8]; 314 FWK_R uint64_t CHILD_INFO; 315 uint8_t RESERVED1[0x900 - 0x88]; 316 FWK_R uint64_t UNIT_INFO; 317 uint8_t RESERVED2[0xA00 - 0x908]; 318 FWK_RW uint64_t AUX_CTL; 319 uint8_t RESERVED3[0x2000 - 0xA08]; 320 FWK_RW uint64_t PMU_EVENT_SEL; 321 uint8_t RESERVED4[0x3000 - 0x2008]; 322 FWK_R uint64_t ERRFR; 323 FWK_RW uint64_t ERRCTL; 324 FWK_RW uint64_t ERRSTATUS; 325 FWK_RW uint64_t ERRADDR; 326 FWK_RW uint64_t ERRMISC; 327 uint8_t RESERVED5[0x3100 - 0x3028]; 328 FWK_R uint64_t ERRFR_NS; 329 FWK_RW uint64_t ERRCTL_NS; 330 FWK_RW uint64_t ERRSTATUS_NS; 331 FWK_RW uint64_t ERRADDR_NS; 332 FWK_RW uint64_t ERRMISC_NS; 333 }; 334 335 /* 336 * Configuration manager registers 337 */ 338 struct cmn600_cfgm_reg { 339 FWK_R uint64_t NODE_INFO; 340 FWK_RW uint64_t PERIPH_ID[4]; 341 FWK_RW uint64_t COMPONENT_ID[2]; 342 uint8_t RESERVED0[0x80 - 0x38]; 343 FWK_R uint64_t CHILD_INFO; 344 uint8_t RESERVED1[0x100 - 0x88]; 345 FWK_R uint64_t CHILD_POINTER[256]; 346 FWK_R uint64_t INFO_GLOBAL; 347 uint8_t RESERVED2[0x980 - 0x908]; 348 FWK_RW uint64_t SECURE_ACCESS; 349 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 350 uint8_t RESERVED3[0x1000 - 0x990]; 351 FWK_RW uint64_t PPU_INT_MASK; 352 FWK_RW uint64_t PPU_INT_STATUS; 353 uint8_t RESERVED4[0x3000 - 0x1010]; 354 FWK_R uint64_t ERRGSR[8]; 355 uint8_t RESERVED5[0x3100 - 0x3040]; 356 FWK_R uint64_t ERRGSR_NS[8]; 357 uint8_t RESERVED6[0x3FA8 - 0x3140]; 358 FWK_R uint64_t ERRDEVAFF; 359 uint8_t RESERVED7[0x3FB8 - 0x3FB0]; 360 FWK_R uint64_t ERRDEVARCH; 361 uint8_t RESERVED8[0x3FC8 - 0x3FC0]; 362 FWK_R uint64_t ERRIDR; 363 FWK_R uint64_t ERRPIDR45; 364 FWK_R uint64_t ERRPIDR67; 365 FWK_R uint64_t ERRPIDR01; 366 FWK_R uint64_t ERRPIDR23; 367 FWK_R uint64_t ERRCIDR01; 368 FWK_R uint64_t ERRCIDR23; 369 }; 370 371 /* 372 * Crosspoint (XP) registers 373 */ 374 struct cmn600_mxp_reg { 375 FWK_R uint64_t NODE_INFO; 376 FWK_R uint64_t PORT_CONNECT_INFO[2]; 377 uint8_t RESERVED0[0x80 - 0x18]; 378 FWK_R uint64_t CHILD_INFO; 379 uint8_t RESERVED1[0x100 - 0x88]; 380 FWK_R uint64_t CHILD_POINTER[16]; 381 uint8_t RESERVED2[0x900 - 0x180]; 382 FWK_R uint64_t P0_INFO; 383 FWK_R uint64_t P1_INFO; 384 uint8_t RESERVED3[0x980 - 0x910]; 385 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 386 uint8_t RESERVED4[0xA00 - 0x988]; 387 FWK_RW uint64_t AUX_CTL; 388 uint8_t RESERVED5[0xA80 - 0xA08]; 389 struct cmn600_qos_reg P_QOS[2]; 390 uint8_t RESERVED6[0x1000 - 0xAC0]; 391 FWK_RW uint64_t P_SYSCOREQ_CTL[2]; 392 FWK_R uint64_t P_SYSCOACK_STATUS[2]; 393 uint8_t RESERVED7[0x2000 - 0x1020]; 394 FWK_RW uint64_t PMU_EVENT_SEL; 395 uint8_t RESERVED8[0x2100 - 0x2008]; 396 FWK_RW uint64_t DTM_CONTROL; 397 uint8_t RESERVED9[0x2118 - 0x2108]; 398 FWK_R uint64_t DTM_FIFO_ENTRY_READY; 399 FWK_R uint64_t DTM_FIFO_ENTRY0[3]; 400 FWK_R uint64_t DTM_FIFO_ENTRY1[3]; 401 FWK_R uint64_t DTM_FIFO_ENTRY2[3]; 402 FWK_R uint64_t DTM_FIFO_ENTRY3[3]; 403 uint8_t RESERVED10[0x21A0 - 0x2180]; 404 FWK_RW uint64_t DTM_WP0_CONFIG; 405 FWK_RW uint64_t DTM_WP0_VAL; 406 FWK_RW uint64_t DTM_WP0_MASK; 407 FWK_RW uint64_t DTM_WP1_CONFIG; 408 FWK_RW uint64_t DTM_WP1_VAL; 409 FWK_RW uint64_t DTM_WP1_MASK; 410 FWK_RW uint64_t DTM_WP2_CONFIG; 411 FWK_RW uint64_t DTM_WP2_VAL; 412 FWK_RW uint64_t DTM_WP2_MASK; 413 FWK_RW uint64_t DTM_WP3_CONFIG; 414 FWK_RW uint64_t DTM_WP3_VAL; 415 FWK_RW uint64_t DTM_WP3_MASK; 416 FWK_RW uint64_t PMSICR; 417 FWK_RW uint64_t PMSIRR; 418 FWK_RW uint64_t DTM_PMU_CONFIG; 419 uint8_t RESERVED11[0x2220 - 0x2218]; 420 FWK_RW uint64_t PMEVCNT[4]; 421 FWK_RW uint64_t PMEVCNTSR[4]; 422 uint8_t RESERVED12[0x3000 - 0x2260]; 423 FWK_R uint64_t ERRFR; 424 FWK_RW uint64_t ERRCTL; 425 FWK_RW uint64_t ERRSTATUS; 426 uint8_t RESERVED13[0x3028 - 0x3018]; 427 FWK_RW uint64_t ERRMISC; 428 FWK_W uint64_t P_BYTE_PAR_ERR_INJ[2]; 429 uint8_t RESERVED14[0x3100 - 0x3040]; 430 FWK_R uint64_t ERRFR_NS; 431 FWK_RW uint64_t ERRCTL_NS; 432 FWK_RW uint64_t ERRSTATUS_NS; 433 uint8_t RESERVED15[0x3128 - 0x3118]; 434 FWK_RW uint64_t ERRMISC_NS; 435 }; 436 437 /* 438 * Request Node I/O (RN-I)registers 439 */ 440 struct cmn600_rni_reg { 441 FWK_R uint64_t NODE_INFO; 442 uint8_t RESERVED0[0x80 - 0x8]; 443 FWK_R uint64_t CHILD_INFO; 444 uint8_t RESERVED1[0x900 - 0x88]; 445 FWK_R uint64_t UNIT_INFO; 446 uint8_t RESERVED2[0x980 - 0x908]; 447 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 448 uint8_t RESERVED3[0xA00 - 0x988]; 449 FWK_RW uint64_t CFG_CTL; 450 FWK_RW uint64_t AUX_CTL; 451 FWK_RW uint64_t S0_PORT_CONTRL; 452 FWK_RW uint64_t S1_PORT_CONTRL; 453 FWK_RW uint64_t S2_PORT_CONTRL; 454 uint8_t RESERVED4[0xA80 - 0xA28]; 455 struct cmn600_qos_reg S_QOS[3]; 456 uint8_t RESERVED5[0x2000 - 0xAE0]; 457 FWK_RW uint64_t PMU_EVENT_SEL; 458 }; 459 460 /* 461 * Home Node I/O (HN-I) registers 462 */ 463 struct cmn600_hni_reg { 464 FWK_R uint64_t NODE_INFO; 465 uint8_t RESERVED0[0x80 - 0x8]; 466 FWK_R uint64_t CHILD_INFO; 467 uint8_t RESERVED1[0x900 - 0x88]; 468 FWK_R uint64_t UNIT_INFO; 469 uint8_t RESERVED2[0x980 - 0x908]; 470 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 471 uint8_t RESERVED3[0xA00 - 0x988]; 472 FWK_RW uint64_t CFG_CTL; 473 FWK_RW uint64_t AUX_CTL; 474 uint8_t RESERVED4[0xC00 - 0xA10]; 475 FWK_RW uint64_t SAM_ADDRREGION_CFG[4]; 476 uint8_t RESERVED5[0x2000 - 0xC20]; 477 FWK_RW uint64_t PMU_EVENT_SEL; 478 uint8_t RESERVED6[0x3000 - 0x2008]; 479 FWK_R uint64_t ERRFR; 480 FWK_RW uint64_t ERRCTL; 481 FWK_RW uint64_t ERRSTATUS; 482 FWK_RW uint64_t ERRADDR; 483 FWK_RW uint64_t ERRMISC; 484 uint8_t RESERVED7[0x3100 - 0x3028]; 485 FWK_R uint64_t ERRFR_NS; 486 FWK_RW uint64_t ERRCTL_NS; 487 FWK_RW uint64_t ERRSTATUS_NS; 488 FWK_RW uint64_t ERRADDR_NS; 489 FWK_RW uint64_t ERRMISC_NS; 490 }; 491 492 #define CMN600_NODE_INFO_TYPE UINT64_C(0x000000000000FFFF) 493 #define CMN600_NODE_INFO_ID UINT64_C(0x00000000FFFF0000) 494 #define CMN600_NODE_INFO_ID_POS 16 495 #define CMN600_NODE_INFO_LOGICAL_ID UINT64_C(0x0000FFFF00000000) 496 #define CMN600_NODE_INFO_LOGICAL_ID_POS 32 497 498 #define CMN600_CHILD_INFO_COUNT UINT64_C(0x000000000000FFFF) 499 500 #define CMN600_CHILD_POINTER UINT64_C(0x00000000FFFFFFFF) 501 #define CMN600_CHILD_POINTER_OFFSET UINT64_C(0x000000000FFFFFFF) 502 #define CMN600_CHILD_POINTER_EXT UINT64_C(0x0000000080000000) 503 504 /* External child node */ 505 #define CMN600_CHILD_POINTER_EXT_REGISTER_OFFSET UINT64_C(0x0000000000003FFF) 506 #define CMN600_CHILD_POINTER_EXT_NODE_POINTER UINT64_C(0x000000000FFFC000) 507 #define CMN600_CHILD_POINTER_EXT_NODE_POINTER_POS 14 508 509 /* Used by NON_HASH_MEM_REGIONx and SYS_CACHE_GRP_REGIONx group registers */ 510 #define CMN600_RNSAM_REGION_ENTRY_VALID_POS 0 511 #define CMN600_RNSAM_REGION_ENTRY_EN_POS 1 /* Not available for all regions */ 512 #define CMN600_RNSAM_REGION_ENTRY_TYPE_POS 2 513 #define CMN600_RNSAM_REGION_ENTRY_SIZE_POS 4 514 #define CMN600_RNSAM_REGION_ENTRY_BASE_POS 9 515 #define CMN600_RNSAM_REGION_ENTRY_BITS_WIDTH 32 516 #define CMN600_RNSAM_REGION_ENTRY_VALID UINT64_C(0x0000000000000001) 517 #define CMN600_RNSAM_REGION_ENTRY_MASK UINT64_C(0xFFFFFFFF) 518 #define CMN600_RNSAM_REGION_ENTRIES_PER_GROUP 2 519 #define CMN600_RNSAM_MAX_HASH_MEM_REGION_ENTRIES 4 520 #define CMN600_RNSAM_SCG_HNF_CAL_MODE_EN UINT64_C(0x01) 521 #define CMN600_RNSAM_SCG_HNF_CAL_MODE_SHIFT 16 522 523 #define CMN600_RNSAM_STATUS_UNSTALL UINT64_C(0x0000000000000002) 524 525 #define CMN600_HNF_SAM_MEMREGION_SIZE_POS 12 526 #define CMN600_HNF_SAM_MEMREGION_BASE_POS 26 527 #define CMN600_HNF_SAM_MEMREGION_VALID UINT64_C(0x8000000000000000) 528 529 #define CMN600_HNF_CACHE_GROUP_ENTRIES_MAX 32 530 #define CMN600_HNF_CACHE_GROUP_ENTRIES_PER_GROUP 4 531 #define CMN600_HNF_CACHE_GROUP_ENTRY_BITS_WIDTH 12 532 533 #define CMN600_HNI_SAM_REGION_CFG_SER_DEVNE_WR UINT64_C(0x1000000000000000) 534 535 #define CMN600_RND_CFG_CTL_PCIE_MSTR_PRESENT UINT64_C(0x0000000000000020) 536 537 #define CMN600_RNSAM_NON_HASH_TGT_NODEID_ENTRY_BITS_WIDTH 12 538 #define CMN600_RNSAM_NON_HASH_TGT_NODEID_ENTRY_MASK UINT64_C(0xFFF) 539 #define CMN600_RNSAM_NON_HASH_TGT_NODEID_ENTRIES_PER_GROUP 4 540 #define CMN600_RNSAM_MAX_NON_HASH_MEM_REGION_ENTRIES(nr_reg) \ 541 ((nr_reg)*CMN600_RNSAM_NON_HASH_TGT_NODEID_ENTRIES_PER_GROUP) 542 543 /*! 544 * r1p0, r1p1 and r1p3 revisions of CMN600 has two NON_HASH_TGT_NODEID registers 545 */ 546 #define CMN600_RNSAM_NON_HASH_TGT_NODEID_REGS_2 2 547 548 /*! 549 * r1p2 and r2p0 revisions of CMN600 has three NON_HASH_TGT_NODEID registers 550 */ 551 #define CMN600_RNSAM_NON_HASH_TGT_NODEID_REGS_3 3 552 553 /*! 554 * r3p0 and above revisions of CMN600 has five NON_HASH_TGT_NODEID 555 * registers 556 */ 557 #define CMN600_RNSAM_NON_HASH_TGT_NODEID_REGS_5 5 558 559 #define CMN600_PPU_PWPR_POLICY_OFF UINT64_C(0x0000000000000000) 560 #define CMN600_PPU_PWPR_POLICY_MEM_RET UINT64_C(0x0000000000000002) 561 #define CMN600_PPU_PWPR_POLICY_FUNC_RET UINT64_C(0x000000000000007) 562 #define CMN600_PPU_PWPR_POLICY_ON UINT64_C(0x0000000000000008) 563 #define CMN600_PPU_PWPR_OPMODE_NOSFSLC UINT64_C(0x0000000000000000) 564 #define CMN600_PPU_PWPR_OPMODE_SFONLY UINT64_C(0x0000000000000010) 565 #define CMN600_PPU_PWPR_OPMODE_HAM UINT64_C(0x0000000000000020) 566 #define CMN600_PPU_PWPR_OPMODE_FAM UINT64_C(0x0000000000000030) 567 #define CMN600_PPU_PWPR_DYN_EN UINT64_C(0x0000000000000100) 568 569 /* Mesh and Node ID mapping */ 570 #define CMN600_MESH_X_MAX 8 571 #define CMN600_MESH_Y_MAX 8 572 573 #define CMN600_NODE_ID_PORT_POS 2 574 #define CMN600_NODE_ID_PORT_MASK 0x1 575 #define CMN600_NODE_ID_Y_POS 3 576 577 #define CMN600_MXP_PORT_CONNECT_INFO_DEVICE_TYPE_MASK UINT64_C(0x1F) 578 579 #define CMN600_ROOT_NODE_OFFSET_PORT_POS 14 580 #define CMN600_ROOT_NODE_OFFSET_Y_POS 20 581 582 /* Peripheral ID Revision Numbers */ 583 enum peripheral_id_revision { 584 CMN600_PERIPH_ID_2_REV_R1_P0, 585 CMN600_PERIPH_ID_2_REV_R1_P1, 586 CMN600_PERIPH_ID_2_REV_R1_P2, 587 CMN600_PERIPH_ID_2_REV_R1_P3, 588 CMN600_PERIPH_ID_2_REV_R2_P0, 589 CMN600_PERIPH_ID_2_REV_R3_P0, 590 CMN600_PERIPH_ID_2_REV_R3_P1, 591 CMN600_PERIPH_ID_2_REV_R3_P2, 592 CMN600_PERIPH_ID_UNKNOWN_REV, 593 }; 594 595 /* Peripheral ID Revision Numbers */ 596 #define CMN600_PERIPH_ID_2_MASK UINT64_C(0xFF) 597 #define CMN600_PERIPH_ID_2_REV_POS 4 598 599 /* 600 * Retrieve the number of child nodes of a given node 601 * 602 * \param node_base Pointer to the node descriptor 603 * \pre The node pointer must be valid 604 * 605 * \return Number of child nodes 606 */ 607 unsigned int get_node_child_count(void *node_base); 608 609 /* 610 * Retrieve node type identifier 611 * 612 * \param node_base Pointer to the node descriptor 613 * \pre The node pointer must be valid 614 * 615 * \return Node's type identifier 616 */ 617 enum node_type get_node_type(void *node_base); 618 619 /* 620 * Retrieve the physical identifier of a node from its hardware node descriptor. 621 * This identifier encodes the node's position in the mesh. 622 * 623 * Note: Multiple node descriptors can share the same identifier if they are 624 * related to the same device node in the mesh. 625 * 626 * \param node_base Pointer to the node descriptor 627 * \pre The node pointer must be valid 628 * 629 * \return Node's physical identifier 630 */ 631 unsigned int get_node_id(void *node_base); 632 633 /* 634 * Retrieve the logical identifier of a node from its hardware node descriptor. 635 * This is an unique identifier (index) among nodes of the same type in the 636 * system. 637 * 638 * \param node_base Pointer to the node base address 639 * \pre The node pointer must be valid 640 * 641 * \return An integer representing the node's logical identifier 642 */ 643 unsigned int get_node_logical_id(void *node_base); 644 645 /* 646 * Retrieve a child node given a node and child index 647 * 648 * \param node_base Pointer to the node descriptor 649 * \pre The node pointer must be valid 650 * \param child_index Child index 651 * \pre The child index must be valid 652 * 653 * \return Pointer to the child's node descriptor 654 */ 655 void *get_child_node(uintptr_t base, void *node_base, unsigned int child_index); 656 657 /* 658 * Retrieve the physical identifier of a node using its child pointer in the 659 * parent's node hardware descriptor 660 * 661 * This function is used to extract a node's identifier without accessing the 662 * node descriptor. This is specially useful for external nodes that are in an 663 * unavailable power or clock domain. 664 * 665 * \param node_base Pointer to the parent node descriptor 666 * \pre The node pointer must be valid 667 * \param child_index Child index 668 * \pre The child index must be valid 669 * 670 * \return Physical child node identifier 671 */ 672 unsigned int get_child_node_id(void *node_base, unsigned int child_index); 673 674 /* 675 * Retrieve the revision number of CMN-600. 676 * 677 * \param root Pointer to the CMN-600 configuration manager register. 678 * 679 * \return CMN-600 revision as integer value. 680 */ 681 unsigned int get_cmn600_revision(struct cmn600_cfgm_reg *root); 682 683 /* 684 * Retrieve the revision name of CMN-600. 685 * 686 * \param root Pointer to the CMN-600 configuration manager register base. 687 * 688 * \return Pointer to the CMN-600 revision name string. 689 */ 690 const char *get_cmn600_revision_name(struct cmn600_cfgm_reg *root); 691 692 /* 693 * Verify if a child node (given a parent node base and child index) is an 694 * external node from the CMN600 instance point of view. 695 * 696 * \param node_base Pointer to the parent node descriptor 697 * \pre The node pointer must be valid 698 * \param child_index Child index 699 * \pre The child index must be valid 700 * 701 * \retval true if the node is external 702 * \retval false if the node is internal 703 */ 704 bool is_child_external(void *node_base, unsigned int child_index); 705 706 /* 707 * Returns the port number from the child node id. 708 * 709 * \param child_node_id Child node id calculated from the child pointer. 710 * 711 * \retval port number (either 0 or 1). 712 */ 713 bool get_port_number(unsigned int child_node_id); 714 715 /* 716 * Returns the device type from the MXP's port connect info register. 717 * 718 * \param mxp_base Pointer to the cross point node descriptor 719 * \pre The cross point node pointer must be valid 720 * \param port Port number 721 * \pre The port number should be either 0 or 1. 722 * 723 * \retval device type (por_mxp_por_mxp_device_port_connect_info_p[port] & 0x1F) 724 */ 725 unsigned int get_device_type(void *mxp_base, bool port); 726 727 /* 728 * Convert a memory region size into a size format used by the CMN600 registers 729 * The format is the binary logarithm of the memory region size represented as 730 * blocks multiple of the CMN600's granularity: 731 * n = log2(size / SAM_GRANULARITY) 732 * 733 * \param size Memory region size to be converted 734 * \pre size must be a multiple of SAM_GRANULARITY 735 * 736 * \return log2(size / SAM_GRANULARITY) 737 */ 738 uint64_t sam_encode_region_size(uint64_t size); 739 740 /* 741 * Configure a memory region 742 * 743 * \param[out] reg Region group descriptor to be configured 744 * \pre Must be a valid pointer 745 * \param bit_offset Bit offset of the memory region in the group descriptor 746 * \param base Region base address 747 * \param size Region size 748 * \param node_type Type of the target node 749 * 750 * \return None 751 */ 752 void configure_region(volatile uint64_t *reg, unsigned int bit_offset, 753 uint64_t base, uint64_t size, enum sam_node_type node_type); 754 755 /* 756 * Retrieve the node type name 757 * 758 * \param node_type Node type 759 * 760 * \return Pointer to the node type name string 761 */ 762 const char *get_node_type_name(enum node_type node_type); 763 764 /* 765 * Retrieve the node's position in the mesh along the X-axis 766 * 767 * \param node_base Pointer to the node descriptor 768 * 769 * \return Zero-indexed position along the X-axis 770 */ 771 unsigned int get_node_pos_x(void *node_base); 772 773 /* 774 * Retrieve the node's position in the mesh along the Y-axis 775 * 776 * \param node_base Pointer to the node descriptor 777 * 778 * \return Zero-indexed position along the Y-axis 779 */ 780 unsigned int get_node_pos_y(void *node_base); 781 782 /* 783 * Get the root node descriptor based on the peripheral base, HN-D node 784 * identifier and mesh size. 785 * 786 * \param base CMN600 peripheral base address 787 * \param hnd_node_id HN-D node identifier containing the global configuration 788 * \param mesh_size_x Size of the mesh along the x-axis 789 * \param mesh_size_y Size of the mesh along the x-axis 790 * 791 * \return Pointer to the root node descriptor 792 */ 793 struct cmn600_cfgm_reg *get_root_node(uintptr_t base, unsigned int hnd_node_id, 794 unsigned int mesh_size_x, unsigned int mesh_size_y); 795 796 /* 797 * Check if CMN600 supports CAL mode. CAL mode is supported from CMN600 r2p0. 798 * 799 * \param root Pointer to the root node descriptor 800 * 801 * \retval true if the CMN600 revision is found to be r2p0 or above 802 * \retval false if the CMN600 revision is found to be r1p3 or below 803 */ 804 bool is_cal_mode_supported(struct cmn600_cfgm_reg *root); 805 806 #endif /* CMN600_H */ 807