1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * Definitions and utility functions for the CMN 650 module. 9 */ 10 11 /* The use of "manager" may not be in sync with older versions of TRM */ 12 13 #ifndef CMN650_H 14 #define CMN650_H 15 16 #include <fwk_macros.h> 17 18 #include <stdbool.h> 19 #include <stdint.h> 20 21 /* Max Node Counts */ 22 #define MAX_HNF_COUNT 64 23 #define MAX_RND_COUNT 32 24 #define MAX_RNI_COUNT 32 25 #define MAX_RNF_COUNT 64 26 27 /* Maximum System Cache Group regions supported by CMN-650 */ 28 #define MAX_SCG_COUNT 4 29 30 /* SAM Granularity of RN-SAM and HN-F SAM */ 31 #define SAM_GRANULARITY (64 * FWK_MIB) 32 33 /* Macros to split 64 bit value two 32 bit values */ 34 #define HIGH_WORD(x) ((unsigned int)((((x)&0xFFFFFFFF00000000ULL) >> 32))) 35 #define LOW_WORD(x) ((unsigned int)((x)&0xFFFFFFFF)) 36 37 /* External nodes that require RN-SAM mapping during run-time */ 38 struct external_rnsam_tuple { 39 unsigned int node_id; 40 struct cmn650_rnsam_reg *node; 41 }; 42 43 /* Pair of CCIX Request Agent (CXG_RA) register and its node-id */ 44 struct cxg_ra_reg_tuple { 45 unsigned int node_id; 46 struct cmn650_cxg_ra_reg *cxg_ra_reg; 47 }; 48 49 /* Pair of CCIX Request Agent (CXG_HA) register and its node-id */ 50 struct cxg_ha_reg_tuple { 51 unsigned int node_id; 52 struct cmn650_cxg_ha_reg *cxg_ha_reg; 53 }; 54 55 /* Pair of CCIX Link Agent (CXLA) register and its node-id */ 56 struct cxla_reg_tuple { 57 unsigned int node_id; 58 struct cmn650_cxla_reg *cxla_reg; 59 }; 60 61 enum node_type { 62 NODE_TYPE_INVALID = 0x0, 63 NODE_TYPE_DVM = 0x1, 64 NODE_TYPE_CFG = 0x2, 65 NODE_TYPE_DTC = 0x3, 66 NODE_TYPE_HN_I = 0x4, 67 NODE_TYPE_HN_F = 0x5, 68 NODE_TYPE_XP = 0x6, 69 NODE_TYPE_SBSX = 0x7, 70 NODE_TYPE_MPAM_S = 0x8, 71 NODE_TYPE_MPAM_NS = 0x9, 72 NODE_TYPE_RN_I = 0xA, 73 NODE_TYPE_RN_D = 0xD, 74 NODE_TYPE_RN_SAM = 0xF, 75 /* Coherent Multichip Link (CML) node types */ 76 NODE_TYPE_CML_BASE = 0x100, 77 NODE_TYPE_CXRA = 0x100, 78 NODE_TYPE_CXHA = 0x101, 79 NODE_TYPE_CXLA = 0x102, 80 }; 81 82 enum device_type { 83 DEVICE_TYPE_RN_F_CHIB_ESAM = 0x5, // 0b00101 84 DEVICE_TYPE_CXHA = 0x11, // 0b10001 85 DEVICE_TYPE_CXRA = 0x12, // 0b10010 86 DEVICE_TYPE_CXRH = 0x13, // 0b10011 87 DEVICE_TYPE_RN_F_CHID_ESAM = 0x15, // 0b10101 88 DEVICE_TYPE_RN_F_CHIC_ESAM = 0x17, // 0b10111 89 }; 90 91 /* Common node header */ 92 struct node_header { 93 FWK_R uint64_t NODE_INFO; 94 uint8_t RESERVED0[0x80 - 0x8]; 95 FWK_R uint64_t CHILD_INFO; 96 uint8_t RESERVED1[0x100 - 0x88]; 97 FWK_R uint64_t CHILD_POINTER[256]; 98 }; 99 100 enum sam_node_type { 101 SAM_NODE_TYPE_HN_F = 0, 102 SAM_NODE_TYPE_HN_I = 1, 103 SAM_NODE_TYPE_CXRA = 2, 104 SAM_NODE_TYPE_COUNT 105 }; 106 107 /* 108 * Request Node System Address Map (RN-SAM) registers 109 */ 110 struct cmn650_rnsam_reg { 111 FWK_R uint64_t NODE_INFO; 112 uint8_t RESERVED0[0x80 - 0x8]; 113 FWK_R uint64_t CHILD_INFO; 114 uint8_t RESERVED1[0x900 - 0x88]; 115 FWK_R uint64_t UNIT_INFO; 116 uint8_t RESERVED2[0xC00 - 0x908]; 117 FWK_RW uint64_t NON_HASH_MEM_REGION[20]; 118 uint8_t RESERVED3[0xD80 - 0xCA0]; 119 FWK_RW uint64_t NON_HASH_TGT_NODEID[5]; 120 uint8_t RESERVED4[0xE00 - 0xDA8]; 121 FWK_RW uint64_t SYS_CACHE_GRP_REGION[4]; 122 uint8_t RESERVED5[0xE80 - 0xE20]; 123 FWK_RW uint64_t RNSAM_HASH_ADDR_MASK_REG; 124 uint8_t RESERVED17[0xEA0 - 0xE88]; 125 FWK_RW uint64_t SYS_CACHE_GRP_HN_COUNT; 126 uint8_t RESERVED6[0xF00 - 0xEA8]; 127 FWK_RW uint64_t SYS_CACHE_GRP_HN_NODEID[16]; 128 uint8_t RESERVED7[0x1000 - 0xF80]; 129 FWK_RW uint64_t SYS_CACHE_GRP_SN_NODEID[16]; 130 uint8_t RESERVED8[0x1100 - 0x1080]; 131 FWK_RW uint64_t STATUS; 132 uint64_t GIC_MEM_REGION; 133 uint8_t RESERVED9[0x1120 - 0x1110]; 134 FWK_RW uint64_t SYS_CACHE_GRP_CAL_MODE; 135 uint8_t RESERVED10[0x1140 - 0x1128]; 136 FWK_RW uint64_t SYS_CACHE_GRP_SN_SAM_CFG[2]; 137 uint8_t RESERVED11[0x1180 - 0x1150]; 138 FWK_RW uint64_t SYS_CACHE_GRP_HN_CPA_EN; 139 uint8_t RESERVED12[0x1190 - 0x1188]; 140 FWK_RW uint64_t SYS_CACHE_GRP_HN_CPA_GRP; 141 uint8_t RESERVED13[0x11A0 - 0x1198]; 142 FWK_RW uint64_t CML_PORT_AGGR_MODE_CTRL[2]; 143 uint8_t RESERVED14[0x11C0 - 0x11B0]; 144 FWK_RW uint64_t CML_PORT_AGGR_GRP_ADD_MASK[5]; 145 uint8_t RESERVED15[0x11F0 - 0x11E8]; 146 FWK_RW uint64_t CML_PORT_AGGR_GRP[2]; 147 uint8_t RESERVED16[0x1208 - 0x1200]; 148 FWK_RW uint64_t CML_PORT_AGGR_CTRL; 149 }; 150 151 /* 152 * Fully Coherent Home Node (HN-F) registers 153 */ 154 struct cmn650_hnf_reg { 155 FWK_R uint64_t NODE_INFO; 156 uint8_t RESERVED0[0x80 - 0x8]; 157 FWK_R uint64_t CHILD_INFO; 158 uint8_t RESERVED1[0x900 - 0x88]; 159 FWK_R uint64_t UNIT_INFO; 160 uint8_t RESERVED2[0xCF0 - 0x908]; 161 FWK_RW uint64_t HN_SAM_HASH_ADDR_MASK_REG; 162 uint8_t RESERVED8[0xD00 - 0xCF8]; 163 FWK_RW uint64_t SAM_CONTROL; 164 FWK_RW uint64_t SAM_MEMREGION[2]; 165 uint8_t RESERVED3[0xD28 - 0xD18]; 166 FWK_RW uint64_t RN_PHYS_ID[64]; 167 uint8_t RESERVED4[0xF80 - 0xF28]; 168 FWK_RW uint64_t CML_PORT_AGGR_GRP_ADD_MASK[5]; 169 uint8_t RESERVED5[0xFB0 - 0xFA8]; 170 FWK_RW uint64_t CML_PORT_AGGR_GRP[2]; 171 uint8_t RESERVED6[0xFD0 - 0xFC0]; 172 FWK_RW uint64_t CML_PORT_AGGR_CTRL; 173 uint8_t RESERVED7[0x1C00 - 0xFD8]; 174 FWK_RW uint64_t PPU_PWPR; 175 }; 176 177 /* 178 * CCIX Gateway (CXG) protocol link control & status registers 179 */ 180 struct cxg_link_regs { 181 FWK_RW uint64_t CXG_PRTCL_LINK_CTRL; 182 FWK_R uint64_t CXG_PRTCL_LINK_STATUS; 183 }; 184 185 /* 186 * CCIX Gateway (CXG) Requesting Agent (RA) registers 187 */ 188 struct cmn650_cxg_ra_reg { 189 FWK_R uint64_t CXG_RA_NODE_INFO; 190 uint8_t RESERVED0[0x80-0x8]; 191 FWK_R uint64_t CXG_RA_CHILD_INFO; 192 uint8_t RESERVED1[0x900-0x88]; 193 FWK_R uint64_t CXG_RA_UNIT_INFO; 194 uint8_t RESERVED2[0x980-0x908]; 195 FWK_RW uint64_t CXG_RA_SEC_REG_GRP_OVERRIDE; 196 uint8_t RESERVED3[0xA00-0x988]; 197 FWK_RW uint64_t CXG_RA_CFG_CTRL; 198 FWK_RW uint64_t CXG_RA_AUX_CTRL; 199 uint8_t RESERVED4[0xDA8-0xA10]; 200 FWK_RW uint64_t CXG_RA_SAM_ADDR_REGION_REG[8]; 201 uint8_t RESERVED5[0xE00-0xDE8]; 202 FWK_RW uint64_t CXG_RA_SAM_MEM_REGION_LIMIT_REG[8]; 203 uint8_t RESERVED6[0xE60-0xE40]; 204 FWK_RW uint64_t CXG_RA_AGENTID_TO_LINKID_REG[8]; 205 FWK_RW uint64_t CXG_RA_RNF_LDID_TO_RAID_REG[8]; 206 FWK_RW uint64_t CXG_RA_RNI_LDID_TO_RAID_REG[4]; 207 FWK_RW uint64_t CXG_RA_RND_LDID_TO_RAID_REG[4]; 208 FWK_RW uint64_t CXG_RA_AGENTID_TO_LINKID_VAL; 209 FWK_RW uint64_t CXG_RA_RNF_LDID_TO_RAID_VAL; 210 FWK_RW uint64_t CXG_RA_RNI_LDID_TO_RAID_VAL; 211 FWK_RW uint64_t CXG_RA_RND_LDID_TO_RAID_VAL; 212 uint8_t RESERVED7[0x1C00-0xF40]; 213 struct cxg_link_regs LINK_REGS[3]; 214 uint8_t RESERVED8[0x2000-0x1030]; 215 FWK_RW uint64_t CXG_RA_PMU_EVENT_SEL; 216 }; 217 218 /* 219 * CCIX Gateway (CXG) Home Agent (HA) registers 220 */ 221 struct cmn650_cxg_ha_reg { 222 FWK_R uint64_t CXG_HA_NODE_INFO; 223 FWK_RW uint64_t CXG_HA_ID; 224 uint8_t RESERVED0[0x80-0x10]; 225 FWK_R uint64_t CXG_HA_CHILD_INFO; 226 uint8_t RESERVED1[0x900-0x88]; 227 FWK_R uint64_t CXG_HA_UNIT_INFO; 228 uint8_t RESERVED2[0x980-0x908]; 229 FWK_RW uint64_t CXG_HA_SEC_REG_GRP_OVERRIDE; 230 uint8_t RESERVED3[0xA08-0x988]; 231 FWK_RW uint64_t CXG_HA_AUX_CTRL; 232 uint8_t RESERVED4[0xC00-0xA10]; 233 FWK_RW uint64_t CXG_HA_RNF_RAID_TO_LDID_REG[8]; 234 FWK_RW uint64_t CXG_HA_AGENTID_TO_LINKID_REG[8]; 235 uint8_t RESERVED5[0xD00-0xC80]; 236 FWK_RW uint64_t CXG_HA_AGENTID_TO_LINKID_VAL; 237 FWK_RW uint64_t CXG_HA_RNF_RAID_TO_LDID_VAL; 238 uint8_t RESERVED6[0x1C00-0xD10]; 239 struct cxg_link_regs LINK_REGS[3]; 240 uint8_t RESERVED7[0x2000-0x1030]; 241 FWK_RW uint64_t CXG_HA_PMU_EVENT_SEL; 242 }; 243 244 /* 245 * CCIX Gateway (CXG) Link Agent (LA) registers 246 */ 247 struct cmn650_cxla_reg { 248 FWK_R uint64_t CXLA_NODE_INFO; 249 uint8_t RESERVED0[0x80-0x8]; 250 FWK_R uint64_t CXLA_CHILD_INFO; 251 uint8_t RESERVED1[0x900-0x88]; 252 FWK_R uint64_t CXLA_UNIT_INFO; 253 uint8_t RESERVED2[0x980-0x908]; 254 FWK_RW uint64_t CXLA_SEC_REG_GRP_OVERRIDE; 255 uint8_t RESERVED3[0xA08-0x988]; 256 FWK_RW uint64_t CXLA_AUX_CTRL; 257 uint8_t RESERVED4[0xC00-0xA10]; 258 FWK_R uint64_t CXLA_CCIX_PROP_CAPABILITIES; 259 FWK_RW uint64_t CXLA_CCIX_PROP_CONFIGURED; 260 FWK_R uint64_t CXLA_TX_CXS_ATTR_CAPABILITIES; 261 FWK_R uint64_t CXLA_RX_CXS_ATTR_CAPABILITIES; 262 uint8_t RESERVED5[0xC30-0xC20]; 263 FWK_RW uint64_t CXLA_AGENTID_TO_LINKID_REG[8]; 264 FWK_RW uint64_t CXLA_AGENTID_TO_LINKID_VAL; 265 FWK_RW uint64_t CXLA_LINKID_TO_PCIE_BUS_NUM; 266 FWK_RW uint64_t CXLA_PCIE_HDR_FIELDS; 267 }; 268 269 /* 270 * Configuration manager registers 271 */ 272 struct cmn650_cfgm_reg { 273 FWK_R uint64_t NODE_INFO; 274 FWK_RW uint64_t PERIPH_ID[4]; 275 FWK_RW uint64_t COMPONENT_ID[2]; 276 uint8_t RESERVED0[0x80 - 0x38]; 277 FWK_R uint64_t CHILD_INFO; 278 }; 279 280 /* 281 * Crosspoint (XP) registers 282 */ 283 struct cmn650_mxp_reg { 284 FWK_R uint64_t NODE_INFO; 285 FWK_R uint64_t PORT_CONNECT_INFO[2]; 286 uint8_t RESERVED0[0x80 - 0x18]; 287 FWK_R uint64_t CHILD_INFO; 288 uint8_t RESERVED1[0x100 - 0x88]; 289 FWK_R uint64_t CHILD_POINTER[16]; 290 }; 291 292 #define CMN650_NODE_INFO_TYPE UINT64_C(0x000000000000FFFF) 293 #define CMN650_NODE_INFO_ID UINT64_C(0x00000000FFFF0000) 294 #define CMN650_NODE_INFO_ID_POS 16 295 #define CMN650_NODE_INFO_LOGICAL_ID UINT64_C(0x0000FFFF00000000) 296 #define CMN650_NODE_INFO_LOGICAL_ID_POS 32 297 298 #define CMN650_CHILD_INFO_COUNT UINT64_C(0x000000000000FFFF) 299 300 #define CMN650_CHILD_POINTER_OFFSET UINT64_C(0x000000000FFFFFFF) 301 #define CMN650_CHILD_POINTER_EXT UINT64_C(0x0000000080000000) 302 303 /* External child node */ 304 #define CMN650_CHILD_POINTER_EXT_REGISTER_OFFSET UINT64_C(0x00003FFF) 305 #define CMN650_CHILD_POINTER_EXT_NODE_POINTER UINT64_C(0x3FFF0000) 306 #define CMN650_CHILD_POINTER_EXT_NODE_POINTER_POS 16 307 308 /* Used by NON_HASH_MEM_REGIONx and SYS_CACHE_GRP_REGIONx group registers */ 309 #define CMN650_RNSAM_REGION_ENTRY_TYPE_POS 2 310 #define CMN650_RNSAM_REGION_ENTRY_SIZE_POS 56 311 #define CMN650_RNSAM_REGION_ENTRY_BASE_POS 26 312 #define CMN650_RNSAM_REGION_ENTRY_BITS_WIDTH 64 313 #define CMN650_RNSAM_REGION_ENTRY_VALID UINT64_C(0x0000000000000001) 314 #define CMN650_RNSAM_REGION_ENTRIES_PER_GROUP 1 315 #define CMN650_RNSAM_SYS_CACHE_GRP_SN_NODEID_ENTRIES_PER_GROUP 4 316 #define CMN650_RNSAM_SCG_HNF_CAL_MODE_EN UINT64_C(0x01) 317 #define CMN650_RNSAM_SCG_HNF_CAL_MODE_SHIFT 16 318 319 #define CMN650_RNSAM_STATUS_UNSTALL UINT64_C(0x0000000000000002) 320 #define CMN650_RNSAM_STATUS_DEFAULT_NODEID_POS 48 321 322 #define CMN650_RNSAM_NON_HASH_TGT_NODEID_ENTRY_BITS_WIDTH 12 323 #define CMN650_RNSAM_NON_HASH_TGT_NODEID_ENTRY_MASK UINT64_C(0xFFF) 324 #define CMN650_RNSAM_NON_HASH_TGT_NODEID_ENTRIES_PER_GROUP 4 325 326 #define CMN650_HNF_SAM_MEMREGION_SIZE_POS 12 327 #define CMN650_HNF_SAM_MEMREGION_BASE_POS 26 328 #define CMN650_HNF_SAM_MEMREGION_VALID UINT64_C(0x8000000000000000) 329 330 #define CMN650_HNF_CACHE_GROUP_ENTRIES_MAX 64 331 #define CMN650_HNF_CACHE_GROUP_ENTRIES_PER_GROUP 4 332 #define CMN650_HNF_CACHE_GROUP_ENTRY_BITS_WIDTH 12 333 334 #define CMN650_PPU_PWPR_POLICY_OFF UINT64_C(0x0000000000000000) 335 #define CMN650_PPU_PWPR_POLICY_MEM_RET UINT64_C(0x0000000000000002) 336 #define CMN650_PPU_PWPR_POLICY_FUNC_RET UINT64_C(0x000000000000007) 337 #define CMN650_PPU_PWPR_POLICY_ON UINT64_C(0x0000000000000008) 338 #define CMN650_PPU_PWPR_OPMODE_NOSFSLC UINT64_C(0x0000000000000000) 339 #define CMN650_PPU_PWPR_OPMODE_SFONLY UINT64_C(0x0000000000000010) 340 #define CMN650_PPU_PWPR_OPMODE_HAM UINT64_C(0x0000000000000020) 341 #define CMN650_PPU_PWPR_OPMODE_FAM UINT64_C(0x0000000000000030) 342 #define CMN650_PPU_PWPR_DYN_EN UINT64_C(0x0000000000000100) 343 344 /* Mesh and Node ID mapping */ 345 #define CMN650_MESH_X_MAX 8 346 #define CMN650_MESH_Y_MAX 8 347 348 #define CMN650_NODE_ID_PORT_POS 2 349 #define CMN650_NODE_ID_PORT_MASK 0x1 350 #define CMN650_NODE_ID_Y_POS 3 351 352 #define CMN650_MXP_PORT_CONNECT_INFO_DEVICE_TYPE_MASK UINT64_C(0x1F) 353 #define CMN650_MXP_PORT_CONNECT_INFO_CAL_CONNECTED_MASK UINT64_C(0x80) 354 #define CMN650_MXP_PORT_CONNECT_INFO_CAL_CONNECTED_POS 7 355 356 #define CMN650_ROOT_NODE_OFFSET_PORT_POS 16 357 #define CMN650_ROOT_NODE_OFFSET_Y_POS 22 358 359 /* Peripheral ID Revision Numbers */ 360 #define CMN650_PERIPH_ID_2_REV_R0_P0 (0x00) 361 #define CMN650_PERIPH_ID_2_REV_R1_P0 (0x01) 362 #define CMN650_PERIPH_ID_2_REV_R1_P1 (0x02) 363 #define CMN650_PERIPH_ID_2_REV_R2_P0 (0x03) 364 #define CMN650_PERIPH_ID_UNKNOWN_REV (CMN650_PERIPH_ID_2_REV_R2_P0 + 1) 365 366 /* Peripheral ID Revision Numbers */ 367 #define CMN650_PERIPH_ID_2_MASK UINT64_C(0xFF) 368 #define CMN650_PERIPH_ID_2_REV_POS 4 369 370 /* 371 * Retrieve the number of child nodes of a given node 372 * 373 * \param node_base Pointer to the node descriptor 374 * \pre The node pointer must be valid 375 * 376 * \return Number of child nodes 377 */ 378 unsigned int get_node_child_count(void *node_base); 379 380 /* 381 * Retrieve node type identifier 382 * 383 * \param node_base Pointer to the node descriptor 384 * \pre The node pointer must be valid 385 * 386 * \return Node's type identifier 387 */ 388 enum node_type get_node_type(void *node_base); 389 390 /* 391 * Retrieve the physical identifier of a node from its hardware node descriptor. 392 * This identifier encodes the node's position in the mesh. 393 * 394 * Note: Multiple node descriptors can share the same identifier if they are 395 * related to the same device node in the mesh. 396 * 397 * \param node_base Pointer to the node descriptor 398 * \pre The node pointer must be valid 399 * 400 * \return Node's physical identifier 401 */ 402 unsigned int get_node_id(void *node_base); 403 404 /* 405 * Retrieve the logical identifier of a node from its hardware node descriptor. 406 * This is an unique identifier (index) among nodes of the same type in the 407 * system. 408 * 409 * \param node_base Pointer to the node base address 410 * \pre The node pointer must be valid 411 * 412 * \return An integer representing the node's logical identifier 413 */ 414 unsigned int get_node_logical_id(void *node_base); 415 416 /* 417 * Retrieve a child node given a node and child index 418 * 419 * \param node_base Pointer to the node descriptor 420 * \pre The node pointer must be valid 421 * \param child_index Child index 422 * \pre The child index must be valid 423 * 424 * \return Pointer to the child's node descriptor 425 */ 426 void *get_child_node(uintptr_t base, void *node_base, unsigned int child_index); 427 428 /* 429 * Retrieve the physical identifier of a node using its child pointer in the 430 * parent's node hardware descriptor 431 * 432 * This function is used to extract a node's identifier without accessing the 433 * node descriptor. This is specially useful for external nodes that are in an 434 * unavailable power or clock domain. 435 * 436 * \param node_base Pointer to the parent node descriptor 437 * \pre The node pointer must be valid 438 * \param child_index Child index 439 * \pre The child index must be valid 440 * 441 * \return Physical child node identifier 442 */ 443 unsigned int get_child_node_id(void *node_base, unsigned int child_index); 444 445 /* 446 * Retrieve the revision name of CMN-650. 447 * 448 * \param root Pointer to the CMN-650 configuration master register base. 449 * 450 * \return Pointer to the CMN-650 revision name string. 451 */ 452 const char *get_cmn650_revision_name(struct cmn650_cfgm_reg *root); 453 454 /* 455 * Verify if a child node (given a parent node base and child index) is an 456 * external node from the CMN 650 instance point of view. 457 * 458 * \param node_base Pointer to the parent node descriptor 459 * \pre The node pointer must be valid 460 * \param child_index Child index 461 * \pre The child index must be valid 462 * 463 * \retval true if the node is external 464 * \retval false if the node is internal 465 */ 466 bool is_child_external(void *node_base, unsigned int child_index); 467 468 /* 469 * Returns the port number from the child node id. 470 * 471 * \param child_node_id Child node id calculated from the child pointer. 472 * 473 * \retval port number (either 0 or 1). 474 */ 475 bool get_port_number(unsigned int child_node_id); 476 477 /* 478 * Returns the device type from the MXP's port connect info register. 479 * 480 * \param mxp_base Pointer to the cross point node descriptor 481 * \pre The cross point node pointer must be valid 482 * \param port Port number 483 * \pre The port number should be either 0 or 1. 484 * 485 * \retval device type (por_mxp_por_mxp_device_port_connect_info_p[port] & 0x1F) 486 */ 487 unsigned int get_device_type(void *mxp_base, bool port); 488 489 /* 490 * Verify if the MXP port has CAL connected to it. 491 * 492 * \param mxp_base Pointer to the cross point node descriptor 493 * \pre The cross point node pointer must be valid 494 * \param port Port number 495 * \pre The port number should be either 0 or 1. 496 * 497 * \retval true if CAL is connected to \param port 498 * \retval false if CAL is non connected to \param port 499 */ 500 bool is_cal_connected(void *mxp_base, uint8_t port); 501 502 /* 503 * Verify if the device type connected to the MXP's port is of one of the RN-F 504 * type. 505 * 506 * \param mxp_base Pointer to the cross point node descriptor 507 * \pre The cross point node pointer must be valid 508 * \param port Port number 509 * \pre The port number should be either 0 or 1. 510 * 511 * \retval true if the device connected to \param port is one of the RN-F types 512 * \retval false if the device connected to \param port not an RN-F type 513 */ 514 bool is_device_type_rnf(void *mxp_base, uint8_t port); 515 516 /* 517 * Convert a memory region size into a size format used by the CMN 650 518 * registers. The format is the binary logarithm of the memory region size 519 * represented as blocks multiple of the CMN 650's granularity: 520 * n = log2(size / SAM_GRANULARITY) 521 * 522 * \param size Memory region size to be converted 523 * \pre size must be a multiple of SAM_GRANULARITY 524 * 525 * \return log2(size / SAM_GRANULARITY) 526 */ 527 uint64_t sam_encode_region_size(uint64_t size); 528 529 /* 530 * Configure a memory region 531 * 532 * \param reg Pointer to the region group descriptor to be configured 533 * \pre Must be a valid pointer 534 * \param region Region entry in the region group descriptor 535 * \param base Region base address 536 * \param size Region size 537 * \param node_type Type of the target node 538 * 539 * \return None 540 */ 541 void configure_region( 542 volatile uint64_t *reg, 543 uint64_t base, 544 uint64_t size, 545 enum sam_node_type node_type); 546 547 /* 548 * Retrieve the node type name 549 * 550 * \param node_type Node type 551 * 552 * \return Pointer to the node type name string 553 */ 554 const char *get_node_type_name(enum node_type node_type); 555 556 /* 557 * Retrieve the node's position in the mesh along the X-axis 558 * 559 * \param node_base Pointer to the node descriptor 560 * 561 * \return Zero-indexed position along the X-axis 562 */ 563 unsigned int get_node_pos_x(void *node_base); 564 565 /* 566 * Retrieve the node's position in the mesh along the Y-axis 567 * 568 * \param node_base Pointer to the node descriptor 569 * 570 * \return Zero-indexed position along the Y-axis 571 */ 572 unsigned int get_node_pos_y(void *node_base); 573 574 /* 575 * Get the root node descriptor based on the peripheral base, HN-D node 576 * identifier and mesh size. 577 * 578 * \param base CMN 650 peripheral base address 579 * \param hnd_node_id HN-D node identifier containing the global configuration 580 * \param mesh_size_x Size of the mesh along the x-axis 581 * \param mesh_size_y Size of the mesh along the x-axis 582 * 583 * \return Pointer to the root node descriptor 584 */ 585 struct cmn650_cfgm_reg *get_root_node( 586 uintptr_t base, 587 unsigned int hnd_node_id, 588 unsigned int mesh_size_x, 589 unsigned int mesh_size_y); 590 591 #endif /* CMN650_H */ 592