1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * CMN-650 CCIX Configuration Interface 9 */ 10 11 #ifndef CMN650_CCIX_H 12 #define CMN650_CCIX_H 13 14 #include <internal/cmn650_ctx.h> 15 16 #include <mod_cmn650.h> 17 18 int ccix_setup( 19 const unsigned int chip_id, 20 struct cmn650_device_ctx *ctx, 21 const struct mod_cmn650_ccix_config *ccix_config); 22 23 int ccix_exchange_protocol_credit( 24 struct cmn650_device_ctx *ctx, 25 const struct mod_cmn650_ccix_config *ccix_config); 26 27 int ccix_enter_system_coherency( 28 struct cmn650_device_ctx *ctx, 29 const struct mod_cmn650_ccix_config *ccix_config); 30 31 int ccix_enter_dvm_domain( 32 struct cmn650_device_ctx *ctx, 33 const struct mod_cmn650_ccix_config *ccix_config); 34 35 /* 36 * CCIX Link UP stages 37 */ 38 enum cxg_link_up_wait_cond { 39 CXG_LINK_CTRL_EN_BIT_SET, 40 CXG_LINK_CTRL_UP_BIT_CLR, 41 CXG_LINK_STATUS_DWN_BIT_SET, 42 CXG_LINK_STATUS_DWN_BIT_CLR, 43 CXG_LINK_STATUS_ACK_BIT_SET, 44 CXG_LINK_STATUS_ACK_BIT_CLR, 45 CXG_LINK_STATUS_HA_DVMDOMAIN_ACK_BIT_SET, 46 CXG_LINK_STATUS_RA_DVMDOMAIN_ACK_BIT_SET, 47 CXG_LINK_UP_SEQ_COUNT, 48 }; 49 50 /* 51 * Structure defining data to be passed to timer API 52 */ 53 struct cxg_wait_condition_data { 54 struct cmn650_device_ctx *ctx; 55 uint8_t linkid; 56 enum cxg_link_up_wait_cond cond; 57 }; 58 59 /* CCIX Gateway (CXG) Home Agent (HA) defines */ 60 #define CXG_HA_RAID_TO_LDID_RNF_MASK (0x80) 61 62 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_MASK UINT64_C(0x0000000000000380) 63 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_SHIFT_VAL 7 64 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_128 0 65 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_256 1 66 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_512 2 67 68 /* CCIX Gateway (CXG) link control & status defines */ 69 70 #define CXG_LINK_CTRL_EN_MASK UINT64_C(0x0000000000000001) 71 #define CXG_LINK_CTRL_REQ_MASK UINT64_C(0x0000000000000002) 72 #define CXG_LINK_CTRL_UP_MASK UINT64_C(0x0000000000000004) 73 #define CXG_LINK_CTRL_DVMDOMAIN_REQ_MASK UINT64_C(0x0000000000000008) 74 #define CXG_LINK_STATUS_ACK_MASK UINT64_C(0x0000000000000001) 75 #define CXG_LINK_STATUS_DOWN_MASK UINT64_C(0x0000000000000002) 76 #define CXG_LINK_STATUS_DVMDOMAIN_ACK_MASK UINT64_C(0x0000000000000004) 77 #define CXG_PRTCL_LINK_CTRL_TIMEOUT UINT32_C(100) 78 #define CXG_PRTCL_LINK_DVMDOMAIN_TIMEOUT UINT32_C(100) 79 80 /* SMP Mode related defines */ 81 #define CXG_RA_AUX_CTRL_SMP_MODE_EN_SHIFT_VAL 16 82 #define CXG_HA_AUX_CTRL_SMP_MODE_EN_SHIFT_VAL 16 83 #define CXLA_AUX_CTRL_SMP_MODE_EN_SHIFT_VAL 47 84 85 #define HNF_RN_PHYS_RN_ID_VALID_SHIFT_VAL 31 86 #define HNF_RN_PHYS_RN_LOCAL_REMOTE_SHIFT_VAL 16 87 #define NUM_BITS_RESERVED_FOR_RAID 8 88 #define NUM_BITS_RESERVED_FOR_LINKID 8 89 #define NUM_BITS_RESERVED_FOR_LDID 8 90 #define NUM_BITS_RESERVED_FOR_PHYS_ID 32 91 #define LOCAL_CCIX_NODE 0 92 #define REMOTE_CCIX_NODE 1 93 #define SAM_ADDR_TARGET_HAID_SHIFT (52) 94 #define SAM_ADDR_REG_VALID_MASK UINT64_C(0x8000000000000000) 95 96 /* 97 * Used by RNSAM and HNSAM CPA registers 98 * 99 * CPA - CCIX Port Aggregation 100 * PAG - Port Aggregation Group 101 * GRPID - Group ID 102 */ 103 104 #define HNF_RN_PHYS_CPA_GRP_RA_SHIFT_VAL 17 105 #define HNF_RN_PHYS_CPA_EN_RA_SHIFT_VAL 30 106 107 #define CML_PORT_AGGR_MODE_CTRL_REGIONS_PER_GROUP 9 108 #define CML_PORT_AGGR_MODE_CTRL_PAG_WIDTH_PER_REGION 6 109 #define CML_PORT_AGGR_MODE_CTRL_PAG_GRPID_OFFSET 1 110 #define CML_PORT_AGGR_CTRL_NUM_CXG_PAG_WIDTH 12 111 #define CMN_PORT_AGGR_GRP_PAG_TGTID_PER_GROUP 5 112 #define CMN_PORT_AGGR_GRP_PAG_TGTID_WIDTH 12 113 #define CMN_PORT_AGGR_GRP_PAG_TGTID_WIDTH_PER_GROUP 60 114 #define NUM_PORTS_PER_CPA_GROUP 2 115 116 #endif /* CMN650_CCIX_H */ 117