1 2 /* 3 * Arm SCP/MCP Software 4 * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 * 8 * Description: 9 * CMN Skeena CCIX Configuration Interface 10 */ 11 12 #ifndef INTERNAL_CMN_SKEENA_CCIX_H 13 #define INTERNAL_CMN_SKEENA_CCIX_H 14 15 #include <internal/cmn_skeena_ctx.h> 16 17 #include <fwk_module_idx.h> 18 19 #include <stdbool.h> 20 #include <stdint.h> 21 22 /* 23 * CMN_SKEENA CCIX Setup Function 24 */ 25 int ccix_setup(struct cmn_skeena_ctx *ctx, void *remote_config); 26 27 /* 28 * CMN_SKEENA CCIX Exchange Protocol Credit Function 29 */ 30 int ccix_exchange_protocol_credit(struct cmn_skeena_ctx *ctx, uint8_t link_id); 31 32 /* 33 * CMN_SKEENA CCIX Enter system Coherency Function 34 */ 35 int ccix_enter_system_coherency(struct cmn_skeena_ctx *ctx, uint8_t link_id); 36 37 /* 38 * CMN_SKEENA CCIX Enter DVM domain Function 39 */ 40 int ccix_enter_dvm_domain(struct cmn_skeena_ctx *ctx, uint8_t link_id); 41 42 /* 43 * CMN_SKEENA CCIX get Capabilities Function 44 */ 45 void ccix_capabilities_get(struct cmn_skeena_ctx *ctx); 46 47 /* 48 * CCIX Gateway (CXG) protocol link control & status registers 49 */ 50 struct cxg_link_regs { 51 FWK_RW uint64_t CXG_PRTCL_LINK_CTRL; 52 FWK_R uint64_t CXG_PRTCL_LINK_STATUS; 53 }; 54 55 /* 56 * CCIX Gateway (CXG) Home Agent (HA) registers 57 */ 58 struct cmn_skeena_cxg_ha_reg { 59 FWK_R uint64_t CXG_HA_NODE_INFO; 60 FWK_RW uint64_t CXG_HA_ID; 61 uint8_t RESERVED0[0x80 - 0x10]; 62 FWK_R uint64_t CXG_HA_CHILD_INFO; 63 uint8_t RESERVED1[0x900 - 0x88]; 64 FWK_R uint64_t CXG_HA_UNIT_INFO; 65 uint8_t RESERVED2[0x980 - 0x908]; 66 FWK_RW uint64_t CXG_HA_SEC_REG_GRP_OVERRIDE; 67 uint8_t RESERVED3[0xA08 - 0x988]; 68 FWK_RW uint64_t CXG_HA_AUX_CTRL; 69 uint8_t RESERVED4[0xC00 - 0xA10]; 70 FWK_RW uint64_t CXG_HA_RNF_RAID_TO_LDID_REG[8]; 71 FWK_RW uint64_t CXG_HA_AGENTID_TO_LINKID_REG[8]; 72 uint8_t RESERVED5[0xD00 - 0xC80]; 73 FWK_RW uint64_t CXG_HA_AGENTID_TO_LINKID_VAL; 74 FWK_RW uint64_t CXG_HA_RNF_RAID_TO_LDID_VAL; 75 uint8_t RESERVED6[0x1000 - 0xD10]; 76 struct cxg_link_regs LINK_REGS[3]; 77 uint8_t RESERVED7[0x2000 - 0x1030]; 78 FWK_RW uint64_t CXG_HA_PMU_EVENT_SEL; 79 uint8_t RESERVED8[0x3000 - 0x2008]; 80 FWK_R uint64_t CXG_HA_ERRFR; 81 FWK_RW uint64_t CXG_HA_ERRCTLR; 82 FWK_RW uint64_t CXG_HA_ERRSTATUS; 83 FWK_RW uint64_t CXG_HA_ERRADDR; 84 FWK_RW uint64_t CXG_HA_ERRMISC; 85 uint8_t RESERVED9[0x3100 - 0x3028]; 86 FWK_R uint64_t CXG_ERRFR_NS; 87 FWK_RW uint64_t CXG_ERRCTLR_NS; 88 FWK_RW uint64_t CXG_ERRSTATUS_NS; 89 FWK_RW uint64_t CXG_ERRADDR_NS; 90 FWK_RW uint64_t CXG_ERRMISC_NS; 91 }; 92 93 /* 94 * CCIX Gateway (CXG) Requesting Agent (RA) registers 95 */ 96 struct cmn_skeena_cxg_ra_reg { 97 FWK_R uint64_t CXG_RA_NODE_INFO; 98 uint8_t RESERVED0[0x80 - 0x8]; 99 FWK_R uint64_t CXG_RA_CHILD_INFO; 100 uint8_t RESERVED1[0x900 - 0x88]; 101 FWK_R uint64_t CXG_RA_UNIT_INFO; 102 uint8_t RESERVED2[0x980 - 0x908]; 103 FWK_RW uint64_t CXG_RA_SEC_REG_GRP_OVERRIDE; 104 uint8_t RESERVED3[0xA00 - 0x988]; 105 FWK_RW uint64_t CXG_RA_CFG_CTRL; 106 FWK_RW uint64_t CXG_RA_AUX_CTRL; 107 uint8_t RESERVED4[0xDA8 - 0xA10]; 108 FWK_RW uint64_t CXG_RA_SAM_ADDR_REGION_REG[8]; 109 uint8_t RESERVED5[0xE00 - 0xDE8]; 110 FWK_RW uint64_t CXG_RA_SAM_MEM_REGION_LIMIT_REG[8]; 111 uint8_t RESERVED6[0xE60 - 0xE40]; 112 FWK_RW uint64_t CXG_RA_AGENTID_TO_LINKID_REG[8]; 113 FWK_RW uint64_t CXG_RA_RNF_LDID_TO_RAID_REG[8]; 114 FWK_RW uint64_t CXG_RA_RNI_LDID_TO_RAID_REG[4]; 115 FWK_RW uint64_t CXG_RA_RND_LDID_TO_RAID_REG[4]; 116 FWK_RW uint64_t CXG_RA_AGENTID_TO_LINKID_VAL; 117 FWK_RW uint64_t CXG_RA_RNF_LDID_TO_RAID_VAL; 118 FWK_RW uint64_t CXG_RA_RNI_LDID_TO_RAID_VAL; 119 FWK_RW uint64_t CXG_RA_RND_LDID_TO_RAID_VAL; 120 uint8_t RESERVED7[0x1000 - 0xF40]; 121 struct cxg_link_regs LINK_REGS[3]; 122 uint8_t RESERVED8[0x2000 - 0x1030]; 123 FWK_RW uint64_t CXG_RA_PMU_EVENT_SEL; 124 }; 125 126 /* 127 * CCIX Gateway (CXG) Link Agent (LA) registers 128 */ 129 struct cmn_skeena_cxla_reg { 130 FWK_R uint64_t CXLA_NODE_INFO; 131 uint8_t RESERVED0[0x80 - 0x8]; 132 FWK_R uint64_t CXLA_CHILD_INFO; 133 uint8_t RESERVED1[0x900 - 0x88]; 134 FWK_R uint64_t CXLA_UNIT_INFO; 135 uint8_t RESERVED2[0x980 - 0x908]; 136 FWK_RW uint64_t CXLA_SEC_REG_GRP_OVERRIDE; 137 uint8_t RESERVED3[0xA08 - 0x988]; 138 FWK_RW uint64_t CXLA_AUX_CTRL; 139 uint8_t RESERVED4[0xC00 - 0xA10]; 140 FWK_R uint64_t CXLA_CCIX_PROP_CAPABILITIES; 141 FWK_RW uint64_t CXLA_CCIX_PROP_CONFIGURED; 142 FWK_R uint64_t CXLA_TX_CXS_ATTR_CAPABILITIES; 143 FWK_R uint64_t CXLA_RX_CXS_ATTR_CAPABILITIES; 144 uint8_t RESERVED5[0xC30 - 0xC20]; 145 FWK_RW uint64_t CXLA_AGENTID_TO_LINKID_REG[8]; 146 FWK_RW uint64_t CXLA_AGENTID_TO_LINKID_VAL; 147 FWK_RW uint64_t CXLA_LINKID_TO_PCIE_BUS_NUM; 148 FWK_RW uint64_t CXLA_PCIE_HDR_FIELDS; 149 uint8_t RESERVED6[0xD00 - 0xC88]; 150 FWK_RW uint64_t CXLA_PERMSG_PYLD_0_63; 151 FWK_RW uint64_t CXLA_PERMSG_PYLD_64_127; 152 FWK_RW uint64_t CXLA_PERMSG_PYLD_128_191; 153 FWK_RW uint64_t CXLA_PERMSG_PYLD_192_255; 154 FWK_RW uint64_t CXLA_PERMSG_CTL; 155 FWK_RW uint64_t CXLA_ERR_AGENT_ID; 156 uint8_t RESERVED7[0x2000 - 0xD30]; 157 FWK_RW uint64_t CXLA_PMU_EVENT_SEL; 158 uint8_t RESERVED8[0x2210 - 0x2008]; 159 FWK_RW uint64_t CXLA_PMU_CONFIG; 160 uint8_t RESERVED9[0x2220 - 0x2218]; 161 FWK_RW uint64_t CXLA_PMEVCNT; 162 uint8_t RESERVED10[0x2240 - 0x2228]; 163 FWK_RW uint64_t CXLA_PMEVCNTSR; 164 }; 165 166 /* 167 * CCIX Definitions 168 */ 169 170 /* 171 * CCIX Link UP stages 172 */ 173 enum cxg_link_up_wait_cond { 174 CXG_LINK_CTRL_EN_BIT_SET, 175 CXG_LINK_CTRL_UP_BIT_CLR, 176 CXG_LINK_STATUS_DWN_BIT_SET, 177 CXG_LINK_STATUS_DWN_BIT_CLR, 178 CXG_LINK_STATUS_ACK_BIT_SET, 179 CXG_LINK_STATUS_ACK_BIT_CLR, 180 CXG_LINK_STATUS_HA_DVMDOMAIN_ACK_BIT_SET, 181 CXG_LINK_STATUS_RA_DVMDOMAIN_ACK_BIT_SET, 182 CXG_LINK_UP_SEQ_COUNT, 183 }; 184 185 /* 186 * Structure defining data to be passed to timer API 187 */ 188 struct cxg_wait_condition_data { 189 struct cmn_skeena_ctx *ctx; 190 uint8_t link_id; 191 enum cxg_link_up_wait_cond cond; 192 }; 193 194 /* CCIX Gateway (CXG) Request Agent (RA) defines */ 195 196 #define CXG_RA_SAM_HA_TGT_ID_SHIFT_VAL 52 197 #define CXG_RA_RNF_LDID_TO_RAID_REG_OFFSET 0xEA0 198 #define CXG_RA_RNI_LDID_TO_RAID_REG_OFFSET 0xEE0 199 #define CXG_RA_RND_LDID_TO_RAID_REG_OFFSET 0xF00 200 #define CXG_RA_RNF_RAID_VALID_REG_OFFSET 0xF28 201 #define CXG_RA_RNI_RAID_VALID_REG_OFFSET 0xF30 202 #define CXG_RA_RND_RAID_VALID_REG_OFFSET 0xF38 203 #define CXG_RA_AGENTID_TO_LINKID_OFFSET 0xE60 204 #define CXG_RA_AGENTID_TO_LINKID_VAL_OFFSET 0xF20 205 #define CXG_RA_REQUEST_TRACKER_DEPTH_MASK UINT64_C(0x0000000001FF0000) 206 #define CXG_RA_REQUEST_TRACKER_DEPTH_VAL 16 207 #define CXG_RA_UNIT_INFO_SMP_MODE_RO_MASK (UINT64_C(1) << 61) 208 #define CXG_RA_AUX_CTRL_SMP_MODE_RW_SHIFT_VAL (16) 209 210 /* CCIX Gateway (CXG) Home Agent (HA) defines */ 211 212 #define CXG_HA_AGENTID_TO_LINKID_OFFSET 0xC40 213 #define CXG_HA_AGENTID_TO_LINKID_VAL_OFFSET 0xD00 214 #define CXG_HA_RAID_TO_LDID_OFFSET (0xC00) 215 #define CXG_HA_RAID_TO_LDID_VALID_OFFSET (0xD08) 216 #define CXG_HA_RAID_TO_LDID_RNF_MASK (0x80) 217 #define CXG_HA_LDID_TO_RAID_OFFSET 0xC00 218 #define CXG_HA_SNOOP_TRACKER_DEPTH_MASK UINT64_C(0x00001FF000000000) 219 #define CXG_HA_SNOOP_TRACKER_DEPTH_VAL 36 220 #define CXG_HA_WDB_DEPTH_MASK UINT64_C(0x0000000007FC0000) 221 #define CXG_HA_WDB_DEPTH_VAL 18 222 #define CXG_HA_UNIT_INFO_SMP_MODE_RO_MASK (UINT64_C(1) << 63) 223 #define CXG_HA_AUX_CTRL_SMP_MODE_RW_SHIFT_VAL (16) 224 225 /* CCIX Gateway (CXG) Link Agent (LA) defines */ 226 227 #define CXLA_AGENTID_TO_LINKID_OFFSET 0xC30 228 #define CXLA_AGENTID_TO_LINKID_VAL_OFFSET 0xC70 229 230 #define CXLA_CCIX_PROP_MSG_PACK_SHIFT_MASK UINT64_C(0x0000000000000400) 231 #define CXLA_CCIX_PROP_MSG_PACK_SHIFT_VAL 10 232 233 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_MASK UINT64_C(0x0000000000000380) 234 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_SHIFT_VAL 7 235 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_128 0 236 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_256 1 237 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_512 2 238 239 #define CXLA_PCIE_HDR_TRAFFIC_CLASS_MASK UINT64_C(0x0000000000007000) 240 #define CXLA_PCIE_HDR_VENDOR_ID_MASK UINT64_C(0x0000FFFF00000000) 241 242 #define CXLA_PCIE_HDR_TRAFFIC_CLASS_SHIFT_VAL 12 243 #define CXLA_PCIE_HDR_VENDOR_ID_SHIFT_VAL 32 244 245 #define CXLA_AUX_CTRL_SMP_MODE_SHIFT_VAL (47) 246 247 /* CCIX Gateway (CXG) link control & status defines */ 248 249 #define CXG_LINK_CTRL_EN_MASK UINT64_C(0x0000000000000001) 250 #define CXG_LINK_CTRL_REQ_MASK UINT64_C(0x0000000000000002) 251 #define CXG_LINK_CTRL_UP_MASK UINT64_C(0x0000000000000004) 252 #define CXG_LINK_CTRL_DVMDOMAIN_REQ_MASK UINT64_C(0x0000000000000008) 253 #define CXG_LINK_STATUS_ACK_MASK UINT64_C(0x0000000000000001) 254 #define CXG_LINK_STATUS_DOWN_MASK UINT64_C(0x0000000000000002) 255 #define CXG_LINK_STATUS_DVMDOMAIN_ACK_MASK UINT64_C(0x0000000000000004) 256 #define CXG_PRTCL_LINK_CTRL_TIMEOUT UINT32_C(100) 257 #define CXG_PRTCL_LINK_DVMDOMAIN_TIMEOUT UINT32_C(100) 258 259 #define RAID_RNF_BIT_SHIFT_VAL 7 260 #define HNF_RN_PHYS_NODE_ID_SHIFT_VAL 16 261 #define HNF_RN_PHYS_RN_ID_VALID_SHIFT_VAL 31 262 #define HNF_RN_PHYS_RN_LOCAL_REMOTE_SHIFT_VAL 16 263 #define NUM_BITS_RESERVED_FOR_RAID 8 264 #define NUM_BITS_RESERVED_FOR_LINK_ID 8 265 #define NUM_BITS_RESERVED_FOR_LDID 8 266 #define NUM_BITS_RESERVED_FOR_PHYS_ID 32 267 #define HNF_RN_PHYS_ID_OFFSET 0xD28 268 #define LOCAL_CCIX_NODE 0 269 #define REMOTE_CCIX_NODE 1 270 #define SAM_ADDR_HOME_AGENT_ID_SHIFT (52) 271 #define SAM_ADDR_REG_VALID_MASK UINT64_C(0x8000000000000000) 272 #define PCIE_OPT_HDR_MASK (0x1ULL << 6) 273 #define CTL_NUM_SNPCRDS_MASK (0xF << 4) 274 #define CCIX_VENDER_ID (0x1E2C) 275 276 #endif /* INTERNAL_CMN_SKEENA_CCIX_H */ 277