1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * Definitions and utility functions for the CMN_SKEENA module. 9 */ 10 11 /* The use of "manager" may not be in sync with older versions of TRM */ 12 13 #ifndef CMN_SKEENA_H 14 #define CMN_SKEENA_H 15 16 #include <fwk_macros.h> 17 18 #include <stdbool.h> 19 #include <stdint.h> 20 21 #define CMN_SKEENA_MAX_NUM_RNF 32 22 #define CMN_SKEENA_MAX_NUM_HNF 32 23 #define CMN_SKEENA_MAX_NUM_SCG 4 24 25 #define SAM_GRANULARITY (64 * FWK_MIB) 26 27 enum node_id_size { 28 NODE_ID_SIZE_7BITS, 29 NODE_ID_SIZE_9BITS, 30 }; 31 32 enum node_type { 33 NODE_TYPE_INVALID = 0x0, 34 NODE_TYPE_DVM = 0x1, 35 NODE_TYPE_CFG = 0x2, 36 NODE_TYPE_DTC = 0x3, 37 NODE_TYPE_HN_I = 0x4, 38 NODE_TYPE_HN_F = 0x5, 39 NODE_TYPE_XP = 0x6, 40 NODE_TYPE_SBSX = 0x7, 41 NODE_TYPE_RN_I = 0xA, 42 NODE_TYPE_RN_D = 0xD, 43 NODE_TYPE_RN_SAM = 0xF, 44 /* Coherent Multichip Link (CML) node types */ 45 NODE_TYPE_CML_BASE = 0x100, 46 NODE_TYPE_CXRA = 0x100, 47 NODE_TYPE_CXHA = 0x101, 48 NODE_TYPE_CXLA = 0x102, 49 }; 50 51 enum device_type { 52 DEVICE_TYPE_CXHA = 0x11, // 0b10001 53 DEVICE_TYPE_CXRA = 0x12, // 0b10010 54 DEVICE_TYPE_CXRH = 0x13, // 0b10011 55 }; 56 57 /* Common node header */ 58 struct node_header { 59 FWK_R uint64_t NODE_INFO; 60 uint8_t RESERVED0[0x80 - 0x8]; 61 FWK_R uint64_t CHILD_INFO; 62 uint8_t RESERVED1[0x100 - 0x88]; 63 FWK_R uint64_t CHILD_POINTER[256]; 64 }; 65 66 struct cluster_mapping { 67 unsigned int node_id; 68 struct node_header *node; 69 }; 70 71 enum sam_node_type { 72 SAM_NODE_TYPE_HN_F = 0, 73 SAM_NODE_TYPE_HN_I = 1, 74 SAM_NODE_TYPE_CXRA = 2, 75 SAM_NODE_TYPE_COUNT 76 }; 77 78 /* 79 * Request Node System Address Map (RN-SAM) registers 80 */ 81 struct cmn_skeena_rnsam_reg { 82 FWK_R uint64_t NODE_INFO; 83 uint8_t RESERVED0[0x80 - 0x8]; 84 FWK_R uint64_t CHILD_INFO; 85 uint8_t RESERVED1[0x900 - 0x88]; 86 FWK_R uint64_t UNIT_INFO; 87 uint8_t RESERVED2[0x980 - 0x908]; 88 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 89 uint8_t RESERVED3[0xC00 - 0x988]; 90 FWK_RW uint64_t STATUS; 91 FWK_RW uint64_t NON_HASH_MEM_REGION0[5]; 92 FWK_RW uint64_t NON_HASH_TGT_NODEID0[3]; 93 FWK_RW uint64_t SYS_CACHE_GRP_REGION[2]; 94 FWK_RW uint64_t SYS_CACHE_GRP_HN_NODEID0[8]; 95 FWK_RW uint64_t SYS_CACHE_GRP_NOHASH_NODEID; 96 FWK_RW uint64_t NON_HASH_MEM_REGION1[5]; 97 uint8_t RESERVED4[0xCE0 - 0xCC8]; 98 FWK_RW uint64_t NON_HASH_TGT_NODEID1[2]; 99 uint8_t RESERVED5[0xD00 - 0xCF0]; 100 FWK_RW uint64_t SYS_CACHE_GRP_HN_COUNT; 101 FWK_RW uint64_t SYS_CACHE_GRP_SN_NODEID0[8]; 102 FWK_RW uint64_t SYS_CACHE_GRP_SN_SAM_CFG[2]; 103 FWK_RW uint64_t GIC_MEM_REGION; 104 FWK_RW uint64_t SYS_CACHE_GRP_SN_ATTR; 105 FWK_RW uint64_t SYS_CACHE_GRP_HN_CPA_EN; 106 FWK_RW uint64_t SYS_CACHE_GRP_HN_CPA_GRP; 107 uint8_t RESERVED6[0xE00 - 0xD78]; 108 FWK_RW uint64_t CML_PORT_AGGR_MODE_CTRL; 109 FWK_RW uint64_t CML_PORT_AGGR_GRP0_ADD_MASK; 110 FWK_RW uint64_t CML_PORT_AGGR_GRP1_ADD_MASK; 111 uint8_t RESERVED7[0xE30 - 0xE18]; 112 FWK_RW uint64_t CML_PORT_AGGR_MODE_CTRL1; 113 uint8_t RESERVED8[0xE40 - 0xE38]; 114 FWK_RW uint64_t CML_PORT_AGGR_GRP0_AGGR; 115 FWK_RW uint64_t CML_PORT_AGGR_GRP1_AGGR; 116 uint8_t RESERVED9[0xF00 - 0xE50]; 117 FWK_RW uint64_t SYS_CACHE_GRP_SECONDARY[2]; 118 FWK_RW uint64_t SYS_CACHE_GRP_CAL_MODE; 119 FWK_RW uint64_t RNSAM_HASH_ADDR_MASK; 120 FWK_RW uint64_t RNSAM_REGION_CMP_ADDR_MASK; 121 uint8_t RESERVED10[0xF58 - 0xF28]; 122 FWK_RW uint64_t SYS_CACHE_GRP_HN_NODEID1[8]; 123 uint8_t RESERVED11[0x1008 - 0xF98]; 124 FWK_RW uint64_t SYS_CACHE_GRP_SN_NODEID1[8]; 125 }; 126 127 /* 128 * Debug and Trace registers 129 */ 130 struct cmn_skeena_dt_reg { 131 FWK_R uint64_t NODE_INFO; 132 uint8_t RESERVED0[0x80 - 0x8]; 133 FWK_R uint64_t CHILD_INFO; 134 uint8_t RESERVED1[0x980 - 0x88]; 135 FWK_RW uint64_t SECURE_ACCESS; 136 uint8_t RESERVED2[0xA00 - 0x988]; 137 FWK_RW uint64_t DTC_CTL; 138 uint8_t RESERVED3[0xA10 - 0xA08]; 139 FWK_R uint64_t TRIGGER_STATUS; 140 uint8_t RESERVED4[0xA20 - 0xA18]; 141 FWK_W uint64_t TRIGGER_STATUS_CLR; 142 uint8_t RESERVED5[0xA30 - 0xA28]; 143 FWK_RW uint64_t TRACE_CONTROL; 144 uint8_t RESERVED6[0xA40 - 0xA38]; 145 FWK_R uint64_t DBG_ID; 146 FWK_RW uint64_t TRACE_ID; 147 uint8_t RESERVED7[0x2000 - 0xA50]; 148 FWK_RW uint64_t PMEVCNT[8]; 149 FWK_RW uint64_t PMCCNTR; 150 uint8_t RESERVED8[0x2050 - 0x2048]; 151 FWK_RW uint64_t PMEVCNTSR[8]; 152 FWK_RW uint64_t PMCCNTRSR; 153 uint8_t RESERVED9[0x2100 - 0x2098]; 154 FWK_RW uint64_t PMCR; 155 FWK_RW uint64_t PMEVCNT_LOCALNUM; 156 uint8_t RESERVED10[0x2118 - 0x2110]; 157 FWK_R uint64_t PMOVSR; 158 FWK_W uint64_t PMOVSR_CLR; 159 FWK_R uint64_t PMSR; 160 FWK_W uint64_t PMSR_REQ; 161 FWK_W uint64_t PMSR_CLR; 162 uint8_t RESERVED11[0x2DA0 - 0x2140]; 163 FWK_RW uint64_t CLAIM; 164 FWK_R uint64_t DEVAFF; 165 FWK_R uint64_t LSR; 166 FWK_R uint64_t AUTHSTATUS_DEVARCH; 167 FWK_R uint64_t DEVID; 168 FWK_R uint64_t DEVTYPE; 169 FWK_R uint64_t PIDR45; 170 FWK_R uint64_t PIDR67; 171 FWK_R uint64_t PIDR01; 172 FWK_R uint64_t PIDR23; 173 FWK_R uint64_t CIDR01; 174 FWK_R uint64_t CIDR23; 175 }; 176 177 /* 178 * Device Node registers 179 */ 180 struct cmn_skeena_dn_reg { 181 FWK_R uint64_t NODE_INFO; 182 uint8_t RESERVED0[0x80 - 0x8]; 183 FWK_R uint64_t CHILD_INFO; 184 uint8_t RESERVED1[0x900 - 0x88]; 185 FWK_R uint64_t BUILD_INFO; 186 uint8_t RESERVED2[0x980 - 0x908]; 187 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 188 uint8_t RESERVED3[0xA00 - 0x988]; 189 FWK_RW uint64_t AUX_CTL; 190 uint8_t RESERVED4[0xC00 - 0xA08]; 191 FWK_RW uint64_t VMF0_CTRL; 192 FWK_RW uint64_t VMF0_RNF[4]; 193 uint8_t RESERVED5[0xC40 - 0xC28]; 194 FWK_RW uint64_t VMF0_RND; 195 uint8_t RESERVED6[0xC60 - 0xC48]; 196 FWK_RW uint64_t VMF0_RNC; 197 uint8_t RESERVED7[0xC80 - 0xC68]; 198 FWK_RW uint64_t VMF1_CTRL; 199 FWK_RW uint64_t VMF1_RNF[4]; 200 uint8_t RESERVED8[0xCC0 - 0xCA8]; 201 FWK_RW uint64_t VMF1_RND; 202 uint8_t RESERVED9[0xCE0 - 0xCC8]; 203 FWK_RW uint64_t VMF1_RNC; 204 uint8_t RESERVED10[0xD00 - 0xCE8]; 205 FWK_RW uint64_t VMF2_CTRL; 206 FWK_RW uint64_t VMF2_RNF[4]; 207 uint8_t RESERVED11[0xD40 - 0xD28]; 208 FWK_RW uint64_t VMF2_RND; 209 uint8_t RESERVED12[0xD60 - 0xD48]; 210 FWK_RW uint64_t VMF2_RNC; 211 uint8_t RESERVED13[0xD80 - 0xD68]; 212 FWK_RW uint64_t VMF3_CTRL; 213 FWK_RW uint64_t VMF3_RNF[4]; 214 uint8_t RESERVED14[0xDC0 - 0xDA8]; 215 FWK_RW uint64_t VMF3_RND; 216 uint8_t RESERVED15[0xDE0 - 0xDC8]; 217 FWK_RW uint64_t VMF3_RNC; 218 uint8_t RESERVED16[0x2000 - 0xDE8]; 219 FWK_RW uint64_t PMU_EVEN_SEL; 220 }; 221 222 /* 223 * Quality of Service (QoS) registers 224 */ 225 struct cmn_skeena_qos_reg { 226 FWK_RW uint64_t QOS_CONTROL; 227 FWK_RW uint64_t QOS_LAST_TGT; 228 FWK_RW uint64_t QOS_LAST_SCALE; 229 FWK_RW uint64_t QOS_LAST_RANGE; 230 }; 231 232 /* 233 * Request Node Device (RN-D) registers 234 */ 235 struct cmn_skeena_rnd_reg { 236 FWK_R uint64_t NODE_INFO; 237 uint8_t RESERVED0[0x80 - 0x8]; 238 FWK_R uint64_t CHILD_INFO; 239 uint8_t RESERVED1[0x900 - 0x88]; 240 FWK_R uint64_t UNIT_INFO; 241 uint8_t RESERVED2[0x980 - 0x908]; 242 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 243 uint8_t RESERVED3[0xA00 - 0x988]; 244 FWK_RW uint64_t CFG_CTL; 245 FWK_RW uint64_t AUX_CTL; 246 FWK_RW uint64_t S_PORT_CONTROL[3]; 247 uint8_t RESERVED4[0xA80 - 0xA28]; 248 struct cmn_skeena_qos_reg S_QOS[3]; 249 uint8_t RESERVED5[0x1000 - 0xAE0]; 250 FWK_RW uint64_t SYSCOREQ_CTL; 251 FWK_R uint64_t SYSCOACK_STATUS; 252 uint8_t RESERVED6[0x2000 - 0x1010]; 253 FWK_RW uint64_t PMU_EVENT_SEL; 254 }; 255 256 /* 257 * Fully Coherent Home Node (HN-F) registers 258 */ 259 struct cmn_skeena_hnf_reg { 260 FWK_R uint64_t NODE_INFO; 261 uint8_t RESERVED0[0x80 - 0x8]; 262 FWK_R uint64_t CHILD_INFO; 263 uint8_t RESERVED1[0x900 - 0x88]; 264 FWK_R uint64_t UNIT_INFO; 265 uint8_t RESERVED2[0x980 - 0x908]; 266 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 267 uint8_t RESERVED3[0xA00 - 0x988]; 268 FWK_RW uint64_t CFG_CTL; 269 FWK_RW uint64_t AUX_CTL; 270 FWK_RW uint64_t R2_AUX_CTL; 271 uint8_t RESERVED4[0xA80 - 0xA18]; 272 FWK_R uint64_t QOS_BAND; 273 FWK_RW uint64_t QOS_RESERVATION; 274 FWK_RW uint64_t RN_STARVATION; 275 uint8_t RESERVED5[0xB80 - 0xA98]; 276 FWK_W uint64_t CFG_L3SF_DBGRD; 277 FWK_R uint64_t L3_CACHE_ACCESS_L3_TAG; 278 FWK_R uint64_t L3_CACHE_ACCESS_L3_DATA; 279 FWK_R uint64_t L3_CACHE_ACCESS_SF_DATA; 280 uint8_t RESERVED6[0xC00 - 0xBA0]; 281 FWK_RW uint64_t L3_LOCK_WAYS; 282 FWK_RW uint64_t L3_LOCK_BASE[4]; 283 uint8_t RESERVED7[0xC30 - 0xC28]; 284 FWK_RW uint64_t RNID_REGION_VEC; 285 FWK_RW uint64_t RNF_REGION_VEC; 286 uint8_t RESERVED8[0xD00 - 0xC40]; 287 FWK_RW uint64_t SAM_CONTROL; 288 FWK_RW uint64_t SAM_MEMREGION[2]; 289 FWK_RW uint64_t SAM_SN_PROPERTIES; 290 FWK_RW uint64_t SAM_6SN_NODEID; 291 FWK_RW uint64_t RN_PHYS_ID[32]; 292 uint8_t RESERVED9[0xF00 - 0xE28]; 293 FWK_RW uint64_t SF_CXG_BLOCKED_WAYS; 294 uint8_t RESERVED10[0xF10 - 0xF08]; 295 FWK_RW uint64_t CML_PORT_AGGR_GRP0_ADD_MASK; 296 uint8_t RESERVED11[0xF28 - 0xF18]; 297 FWK_RW uint64_t CML_PORT_AGGR_GRP0_ADD_REG; 298 uint8_t RESERVED12[0x1000 - 0xF30]; 299 FWK_RW uint64_t PPU_PWPR; 300 FWK_R uint64_t PPU_PWSR; 301 uint8_t RESERVED13[0x1014 - 0x1010]; 302 FWK_R uint32_t PPU_MISR; 303 uint8_t RESERVED14[0x1100 - 0x1018]; 304 FWK_RW uint64_t PPU_DYN_RET_THRESHOLD; 305 uint8_t RESERVED15[0x1FB0 - 0x1108]; 306 FWK_R uint32_t PPU_IDR[2]; 307 uint8_t RESERVED16[0x1FC8 - 0x1FB8]; 308 FWK_R uint32_t PPU_IIDR; 309 FWK_R uint32_t PPU_AIDR; 310 uint8_t RESERVED17[0x2000 - 0x1FD0]; 311 FWK_RW uint64_t PMU_EVENT_SEL; 312 uint8_t RESERVED18[0x3000 - 0x2008]; 313 FWK_R uint64_t ERRFR; 314 FWK_RW uint64_t ERRCTLR; 315 FWK_RW uint64_t ERRSTATUS; 316 FWK_RW uint64_t ERRADDR; 317 FWK_RW uint64_t ERRMISC; 318 uint8_t RESERVED19[0x3030 - 0x3028]; 319 FWK_RW uint64_t RN_ERR_INJ; 320 FWK_W uint64_t RN_BYTE_PAR_ERR_INJ; 321 uint8_t RESERVED20[0x3100 - 0x3040]; 322 FWK_R uint64_t ERRFR_NS; 323 FWK_RW uint64_t ERRCTLR_NS; 324 FWK_RW uint64_t ERRSTATUS_NS; 325 FWK_RW uint64_t ERRADDR_NS; 326 FWK_RW uint64_t ERRMISC_NS; 327 }; 328 329 /* 330 * AMBA 5 CHI to AXI bridge registers 331 */ 332 struct cmn_skeena_sbsx_reg { 333 FWK_R uint64_t NODE_INFO; 334 uint8_t RESERVED0[0x80 - 0x8]; 335 FWK_R uint64_t CHILD_INFO; 336 uint8_t RESERVED1[0x900 - 0x88]; 337 FWK_R uint64_t UNIT_INFO; 338 uint8_t RESERVED2[0xA00 - 0x908]; 339 FWK_RW uint64_t AUX_CTL; 340 uint8_t RESERVED3[0x2000 - 0xA08]; 341 FWK_RW uint64_t PMU_EVENT_SEL; 342 uint8_t RESERVED4[0x3000 - 0x2008]; 343 FWK_R uint64_t ERRFR; 344 FWK_RW uint64_t ERRCTL; 345 FWK_RW uint64_t ERRSTATUS; 346 FWK_RW uint64_t ERRADDR; 347 FWK_RW uint64_t ERRMISC; 348 uint8_t RESERVED5[0x3100 - 0x3028]; 349 FWK_R uint64_t ERRFR_NS; 350 FWK_RW uint64_t ERRCTL_NS; 351 FWK_RW uint64_t ERRSTATUS_NS; 352 FWK_RW uint64_t ERRADDR_NS; 353 FWK_RW uint64_t ERRMISC_NS; 354 }; 355 356 /* 357 * Configuration manager registers 358 */ 359 struct cmn_skeena_cfgm_reg { 360 FWK_R uint64_t NODE_INFO; 361 FWK_RW uint64_t PERIPH_ID[4]; 362 FWK_RW uint64_t COMPONENT_ID[2]; 363 uint8_t RESERVED0[0x80 - 0x38]; 364 FWK_R uint64_t CHILD_INFO; 365 uint8_t RESERVED1[0x100 - 0x88]; 366 FWK_R uint64_t CHILD_POINTER[256]; 367 FWK_R uint64_t INFO_GLOBAL; 368 uint8_t RESERVED2[0x980 - 0x908]; 369 FWK_RW uint64_t SECURE_ACCESS; 370 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 371 uint8_t RESERVED3[0x1000 - 0x990]; 372 FWK_RW uint64_t PPU_INT_MASK; 373 FWK_RW uint64_t PPU_INT_STATUS; 374 uint8_t RESERVED4[0x3000 - 0x1010]; 375 FWK_R uint64_t ERRGSR[8]; 376 uint8_t RESERVED5[0x3100 - 0x3040]; 377 FWK_R uint64_t ERRGSR_NS[8]; 378 uint8_t RESERVED6[0x3FA8 - 0x3140]; 379 FWK_R uint64_t ERRDEVAFF; 380 uint8_t RESERVED7[0x3FB8 - 0x3FB0]; 381 FWK_R uint64_t ERRDEVARCH; 382 uint8_t RESERVED8[0x3FC8 - 0x3FC0]; 383 FWK_R uint64_t ERRIDR; 384 FWK_R uint64_t ERRPIDR45; 385 FWK_R uint64_t ERRPIDR67; 386 FWK_R uint64_t ERRPIDR01; 387 FWK_R uint64_t ERRPIDR23; 388 FWK_R uint64_t ERRCIDR01; 389 FWK_R uint64_t ERRCIDR23; 390 }; 391 392 /* 393 * Crosspoint (XP) registers 394 */ 395 struct cmn_skeena_mxp_reg { 396 FWK_R uint64_t NODE_INFO; 397 FWK_R uint64_t PORT_CONNECT_INFO[2]; 398 FWK_R uint64_t MESH_PORT_CONNECT_INFO_EAST; 399 FWK_R uint64_t MESH_PORT_CONNECT_INFO_NORTH; 400 uint8_t RESERVED0[0x80 - 0x28]; 401 FWK_R uint64_t CHILD_INFO; 402 uint8_t RESERVED1[0x100 - 0x88]; 403 FWK_R uint64_t CHILD_POINTER[16]; 404 uint8_t RESERVED2[0x900 - 0x180]; 405 FWK_R uint64_t P0_INFO; 406 FWK_R uint64_t P1_INFO; 407 uint8_t RESERVED3[0x980 - 0x910]; 408 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 409 uint8_t RESERVED4[0xA00 - 0x988]; 410 FWK_RW uint64_t AUX_CTL; 411 uint8_t RESERVED5[0xA80 - 0xA08]; 412 struct cmn_skeena_qos_reg P_QOS[2]; 413 uint8_t RESERVED6[0x1000 - 0xAC0]; 414 FWK_RW uint64_t P_SYSCOREQ_CTL[2]; 415 FWK_R uint64_t P_SYSCOACK_STATUS[2]; 416 uint8_t RESERVED7[0x2000 - 0x1020]; 417 FWK_RW uint64_t PMU_EVENT_SEL; 418 uint8_t RESERVED8[0x2100 - 0x2008]; 419 FWK_RW uint64_t DTM_CONTROL; 420 uint8_t RESERVED9[0x2118 - 0x2108]; 421 FWK_R uint64_t DTM_FIFO_ENTRY_READY; 422 FWK_R uint64_t DTM_FIFO_ENTRY0[3]; 423 FWK_R uint64_t DTM_FIFO_ENTRY1[3]; 424 FWK_R uint64_t DTM_FIFO_ENTRY2[3]; 425 FWK_R uint64_t DTM_FIFO_ENTRY3[3]; 426 uint8_t RESERVED10[0x21A0 - 0x2180]; 427 FWK_RW uint64_t DTM_WP0_CONFIG; 428 FWK_RW uint64_t DTM_WP0_VAL; 429 FWK_RW uint64_t DTM_WP0_MASK; 430 FWK_RW uint64_t DTM_WP1_CONFIG; 431 FWK_RW uint64_t DTM_WP1_VAL; 432 FWK_RW uint64_t DTM_WP1_MASK; 433 FWK_RW uint64_t DTM_WP2_CONFIG; 434 FWK_RW uint64_t DTM_WP2_VAL; 435 FWK_RW uint64_t DTM_WP2_MASK; 436 FWK_RW uint64_t DTM_WP3_CONFIG; 437 FWK_RW uint64_t DTM_WP3_VAL; 438 FWK_RW uint64_t DTM_WP3_MASK; 439 FWK_RW uint64_t PMSICR; 440 FWK_RW uint64_t PMSIRR; 441 FWK_RW uint64_t DTM_PMU_CONFIG; 442 uint8_t RESERVED11[0x2220 - 0x2218]; 443 FWK_RW uint64_t PMEVCNT[4]; 444 FWK_RW uint64_t PMEVCNTSR[4]; 445 uint8_t RESERVED12[0x3000 - 0x2260]; 446 FWK_R uint64_t ERRFR; 447 FWK_RW uint64_t ERRCTL; 448 FWK_RW uint64_t ERRSTATUS; 449 uint8_t RESERVED13[0x3028 - 0x3018]; 450 FWK_RW uint64_t ERRMISC; 451 FWK_W uint64_t P_BYTE_PAR_ERR_INJ[2]; 452 uint8_t RESERVED14[0x3100 - 0x3040]; 453 FWK_R uint64_t ERRFR_NS; 454 FWK_RW uint64_t ERRCTL_NS; 455 FWK_RW uint64_t ERRSTATUS_NS; 456 uint8_t RESERVED15[0x3128 - 0x3118]; 457 FWK_RW uint64_t ERRMISC_NS; 458 }; 459 460 /* 461 * Request Node I/O (RN-I)registers 462 */ 463 struct cmn_skeena_rni_reg { 464 FWK_R uint64_t NODE_INFO; 465 uint8_t RESERVED0[0x80 - 0x8]; 466 FWK_R uint64_t CHILD_INFO; 467 uint8_t RESERVED1[0x900 - 0x88]; 468 FWK_R uint64_t UNIT_INFO; 469 uint8_t RESERVED2[0x980 - 0x908]; 470 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 471 uint8_t RESERVED3[0xA00 - 0x988]; 472 FWK_RW uint64_t CFG_CTL; 473 FWK_RW uint64_t AUX_CTL; 474 FWK_RW uint64_t S0_PORT_CONTRL; 475 FWK_RW uint64_t S1_PORT_CONTRL; 476 FWK_RW uint64_t S2_PORT_CONTRL; 477 uint8_t RESERVED4[0xA80 - 0xA28]; 478 struct cmn_skeena_qos_reg S_QOS[3]; 479 uint8_t RESERVED5[0x2000 - 0xAE0]; 480 FWK_RW uint64_t PMU_EVENT_SEL; 481 }; 482 483 /* 484 * Home Node I/O (HN-I) registers 485 */ 486 struct cmn_skeena_hni_reg { 487 FWK_R uint64_t NODE_INFO; 488 uint8_t RESERVED0[0x80 - 0x8]; 489 FWK_R uint64_t CHILD_INFO; 490 uint8_t RESERVED1[0x900 - 0x88]; 491 FWK_R uint64_t UNIT_INFO; 492 uint8_t RESERVED2[0x980 - 0x908]; 493 FWK_RW uint64_t SECURE_REGISTER_GROUPS_OVERRIDE; 494 uint8_t RESERVED3[0xA00 - 0x988]; 495 FWK_RW uint64_t CFG_CTL; 496 FWK_RW uint64_t AUX_CTL; 497 uint8_t RESERVED4[0xC00 - 0xA10]; 498 FWK_RW uint64_t SAM_ADDRREGION_CFG[4]; 499 uint8_t RESERVED5[0x2000 - 0xC20]; 500 FWK_RW uint64_t PMU_EVENT_SEL; 501 uint8_t RESERVED6[0x3000 - 0x2008]; 502 FWK_R uint64_t ERRFR; 503 FWK_RW uint64_t ERRCTL; 504 FWK_RW uint64_t ERRSTATUS; 505 FWK_RW uint64_t ERRADDR; 506 FWK_RW uint64_t ERRMISC; 507 uint8_t RESERVED7[0x3100 - 0x3028]; 508 FWK_R uint64_t ERRFR_NS; 509 FWK_RW uint64_t ERRCTL_NS; 510 FWK_RW uint64_t ERRSTATUS_NS; 511 FWK_RW uint64_t ERRADDR_NS; 512 FWK_RW uint64_t ERRMISC_NS; 513 }; 514 515 #define CMN_SKEENA_NODE_INFO_TYPE UINT64_C(0x000000000000FFFF) 516 #define CMN_SKEENA_NODE_INFO_ID UINT64_C(0x00000000FFFF0000) 517 #define CMN_SKEENA_NODE_INFO_ID_POS 16 518 #define CMN_SKEENA_NODE_INFO_LOGICAL_ID UINT64_C(0x0000FFFF00000000) 519 #define CMN_SKEENA_NODE_INFO_LOGICAL_ID_POS 32 520 521 #define CMN_SKEENA_CHILD_INFO_COUNT UINT64_C(0x000000000000FFFF) 522 523 #define CMN_SKEENA_CHILD_POINTER UINT64_C(0x00000000FFFFFFFF) 524 #define CMN_SKEENA_CHILD_POINTER_OFFSET UINT64_C(0x000000000FFFFFFF) 525 #define CMN_SKEENA_CHILD_POINTER_EXT UINT64_C(0x0000000080000000) 526 527 /* External child node */ 528 #define CMN_SKEENA_CHILD_POINTER_EXT_REGISTER_OFFSET \ 529 UINT64_C(0x0000000000003FFF) 530 #define CMN_SKEENA_CHILD_POINTER_EXT_NODE_POINTER UINT64_C(0x0FFFC000) 531 #define CMN_SKEENA_CHILD_POINTER_EXT_NODE_POINTER_POS 14 532 533 /* Used by NON_HASH_MEM_REGIONx and SYS_CACHE_GRP_REGIONx group registers */ 534 #define CMN_SKEENA_RNSAM_REGION_ENTRY_VALID_POS 0 535 #define CMN_SKEENA_RNSAM_REGION_ENTRY_EN_POS \ 536 1 /* Not available for all regions */ 537 #define CMN_SKEENA_RNSAM_REGION_ENTRY_TYPE_POS 2 538 #define CMN_SKEENA_RNSAM_REGION_ENTRY_SIZE_POS 4 539 #define CMN_SKEENA_RNSAM_REGION_ENTRY_BASE_POS 9 540 #define CMN_SKEENA_RNSAM_REGION_ENTRY_BITS_WIDTH 32 541 #define CMN_SKEENA_RNSAM_REGION_ENTRY_VALID UINT64_C(0x00000001) 542 #define CMN_SKEENA_RNSAM_REGION_ENTRY_MASK UINT64_C(0xFFFFFFFF) 543 #define CMN_SKEENA_RNSAM_REGION_ENTRIES_PER_GROUP 2 544 #define CMN_SKEENA_RNSAM_MAX_HASH_MEM_REGION_ENTRIES 4 545 #define CMN_SKEENA_RNSAM_MAX_NON_HASH_MEM_REGION_ENTRIES 20 546 #define CMN_SKEENA_RNSAM_SCG_HNF_CAL_MODE_EN UINT64_C(0x01) 547 #define CMN_SKEENA_RNSAM_SCG_HNF_CAL_MODE_SHIFT 16 548 549 #define CMN_SKEENA_RNSAM_STATUS_UNSTALL UINT64_C(0x0000000000000002) 550 551 #define CMN_SKEENA_HNF_SAM_MEMREGION_SIZE_POS 12 552 #define CMN_SKEENA_HNF_SAM_MEMREGION_BASE_POS 26 553 #define CMN_SKEENA_HNF_SAM_MEMREGION_VALID UINT64_C(0x8000000000000000) 554 555 #define CMN_SKEENA_HNF_CACHE_GROUP_ENTRIES_MAX 32 556 #define CMN_SKEENA_HNF_CACHE_GROUP_ENTRIES_PER_GROUP 4 557 #define CMN_SKEENA_HNF_CACHE_GROUP_ENTRY_BITS_WIDTH 12 558 559 #define CMN_SKEENA_HNI_SAM_REGION_CFG_SER_DEVNE_WR UINT64_C(0x1000000000000000) 560 561 #define CMN_SKEENA_RND_CFG_CTL_PCIE_MSTR_PRESENT UINT64_C(0x0000000000000020) 562 563 #define CMN_SKEENA_RNSAM_NON_HASH_TGT_NODEID_ENTRY_BITS_WIDTH 12 564 #define CMN_SKEENA_RNSAM_NON_HASH_TGT_NODEID_ENTRY_MASK UINT64_C(0xFFF) 565 #define CMN_SKEENA_RNSAM_NON_HASH_TGT_NODEID_ENTRIES_PER_GROUP 4 566 567 #define CMN_SKEENA_PPU_PWPR_POLICY_OFF UINT64_C(0x0000000000000000) 568 #define CMN_SKEENA_PPU_PWPR_POLICY_MEM_RET UINT64_C(0x0000000000000002) 569 #define CMN_SKEENA_PPU_PWPR_POLICY_FUNC_RET UINT64_C(0x000000000000007) 570 #define CMN_SKEENA_PPU_PWPR_POLICY_ON UINT64_C(0x0000000000000008) 571 #define CMN_SKEENA_PPU_PWPR_OPMODE_NOSFSLC UINT64_C(0x0000000000000000) 572 #define CMN_SKEENA_PPU_PWPR_OPMODE_SFONLY UINT64_C(0x0000000000000010) 573 #define CMN_SKEENA_PPU_PWPR_OPMODE_HAM UINT64_C(0x0000000000000020) 574 #define CMN_SKEENA_PPU_PWPR_OPMODE_FAM UINT64_C(0x0000000000000030) 575 #define CMN_SKEENA_PPU_PWPR_DYN_EN UINT64_C(0x0000000000000100) 576 577 /* Mesh and Node ID mapping */ 578 #define CMN_SKEENA_MESH_X_MAX 8 579 #define CMN_SKEENA_MESH_Y_MAX 8 580 581 #define CMN_SKEENA_NODE_ID_PORT_POS 2 582 #define CMN_SKEENA_NODE_ID_PORT_MASK 0x1 583 #define CMN_SKEENA_NODE_ID_Y_POS 3 584 585 #define CMN_SKEENA_MXP_PORT_CONNECT_INFO_DEVICE_TYPE_MASK UINT64_C(0x1F) 586 587 #define CMN_SKEENA_ROOT_NODE_OFFSET_PORT_POS 14 588 #define CMN_SKEENA_ROOT_NODE_OFFSET_Y_POS 20 589 590 /* Peripheral ID Revision Numbers */ 591 #define CMN_SKEENA_PERIPH_ID_2_REV_R1_P0 ((0x00 << 4) + (0x0B)) 592 #define CMN_SKEENA_PERIPH_ID_2_REV_R1_P1 ((0x01 << 4) + (0x0B)) 593 #define CMN_SKEENA_PERIPH_ID_2_REV_R1_P2 ((0x02 << 4) + (0x0B)) 594 #define CMN_SKEENA_PERIPH_ID_2_REV_R1_P3 ((0x03 << 4) + (0x0B)) 595 #define CMN_SKEENA_PERIPH_ID_2_REV_R2_P0 ((0x04 << 4) + (0x0B)) 596 #define CMN_SKEENA_PERIPH_ID_2_REV_R3_P0 ((0x05 << 4) + (0x0B)) 597 #define CMN_SKEENA_PERIPH_ID_2_REV_R3_P1 ((0x06 << 4) + (0x0B)) 598 599 /* Peripheral ID Revision Numbers */ 600 #define CMN_SKEENA_PERIPH_ID_2_MASK UINT64_C(0xFF) 601 602 /* 603 * Retrieve the number of child nodes of a given node 604 * 605 * \param node_base Pointer to the node descriptor 606 * \pre The node pointer must be valid 607 * 608 * \return Number of child nodes 609 */ 610 unsigned int get_node_child_count(void *node_base); 611 612 /* 613 * Retrieve node type identifier 614 * 615 * \param node_base Pointer to the node descriptor 616 * \pre The node pointer must be valid 617 * 618 * \return Node's type identifier 619 */ 620 enum node_type get_node_type(void *node_base); 621 622 /* 623 * Retrieve the physical identifier of a node from its hardware node descriptor. 624 * This identifier encodes the node's position in the mesh. 625 * 626 * Note: Multiple node descriptors can share the same identifier if they are 627 * related to the same device node in the mesh. 628 * 629 * \param node_base Pointer to the node descriptor 630 * \pre The node pointer must be valid 631 * 632 * \return Node's physical identifier 633 */ 634 unsigned int get_node_id(void *node_base); 635 636 /* 637 * Retrieve the logical identifier of a node from its hardware node descriptor. 638 * This is an unique identifier (index) among nodes of the same type in the 639 * system. 640 * 641 * \param node_base Pointer to the node base address 642 * \pre The node pointer must be valid 643 * 644 * \return An integer representing the node's logical identifier 645 */ 646 unsigned int get_node_logical_id(void *node_base); 647 648 /* 649 * Retrieve a child node given a node and child index 650 * 651 * \param node_base Pointer to the node descriptor 652 * \pre The node pointer must be valid 653 * \param child_index Child index 654 * \pre The child index must be valid 655 * 656 * \return Pointer to the child's node descriptor 657 */ 658 void *get_child_node(uintptr_t base, void *node_base, unsigned int child_index); 659 660 /* 661 * Retrieve the physical identifier of a node using its child pointer in the 662 * parent's node hardware descriptor 663 * 664 * This function is used to extract a node's identifier without accessing the 665 * node descriptor. This is specially useful for external nodes that are in an 666 * unavailable power or clock domain. 667 * 668 * \param node_base Pointer to the parent node descriptor 669 * \pre The node pointer must be valid 670 * \param child_index Child index 671 * \pre The child index must be valid 672 * 673 * \return Physical child node identifier 674 */ 675 unsigned int get_child_node_id(void *node_base, unsigned int child_index); 676 677 /* 678 * Retrieve the revision number of CMN-600. 679 * 680 * \param root Pointer to the CMN-600 configuration manager register. 681 * 682 * \return CMN-600 revision as integer value. 683 */ 684 unsigned int get_cmn_skeena_revision(struct cmn_skeena_cfgm_reg *root); 685 686 /* 687 * Verify if a child node (given a parent node base and child index) is an 688 * external node from the CMN_SKEENA instance point of view. 689 * 690 * \param node_base Pointer to the parent node descriptor 691 * \pre The node pointer must be valid 692 * \param child_index Child index 693 * \pre The child index must be valid 694 * 695 * \retval true if the node is external 696 * \retval false if the node is internal 697 */ 698 bool is_child_external(void *node_base, unsigned int child_index); 699 700 /* 701 * Returns the port number from the child node id. 702 * 703 * \param child_node_id Child node id calculated from the child pointer. 704 * 705 * \retval port number (either 0 or 1). 706 */ 707 bool get_port_number(unsigned int child_node_id); 708 709 /* 710 * Returns the device type from the MXP's port connect info register. 711 * 712 * \param mxp_base Pointer to the cross point node descriptor 713 * \pre The cross point node pointer must be valid 714 * \param port Port number 715 * \pre The port number should be either 0 or 1. 716 * 717 * \retval device type (por_mxp_por_mxp_device_port_connect_info_p[port] & 0x1F) 718 */ 719 unsigned int get_device_type(void *mxp_base, bool port); 720 721 /* 722 * Convert a memory region size into a size format used by the CMN_SKEENA 723 * registers The format is the binary logarithm of the memory region size 724 * represented as blocks multiple of the CMN_SKEENA's granularity: n = log2(size 725 * / SAM_GRANULARITY) 726 * 727 * \param size Memory region size to be converted 728 * \pre size must be a multiple of SAM_GRANULARITY 729 * 730 * \return log2(size / SAM_GRANULARITY) 731 */ 732 uint64_t sam_encode_region_size(uint64_t size); 733 734 /* 735 * Configure a memory region 736 * 737 * \param[out] reg Region group descriptor to be configured 738 * \pre Must be a valid pointer 739 * \param bit_offset Bit offset of the memory region in the group descriptor 740 * \param base Region base address 741 * \param size Region size 742 * \param node_type Type of the target node 743 * 744 * \return None 745 */ 746 void configure_region( 747 volatile uint64_t *reg, 748 unsigned int bit_offset, 749 uint64_t base, 750 uint64_t size, 751 enum sam_node_type node_type); 752 753 /* 754 * Retrieve the node type name 755 * 756 * \param node_type Node type 757 * 758 * \return Pointer to the node type name string 759 */ 760 const char *get_node_type_name(enum node_type node_type); 761 762 /* 763 * Retrieve the node's position in the mesh along the X-axis 764 * 765 * \param node_base Pointer to the node descriptor 766 * 767 * \return Zero-indexed position along the X-axis 768 */ 769 unsigned int get_node_pos_x(void *node_base); 770 771 /* 772 * Retrieve the node's position in the mesh along the Y-axis 773 * 774 * \param node_base Pointer to the node descriptor 775 * 776 * \return Zero-indexed position along the Y-axis 777 */ 778 unsigned int get_node_pos_y(void *node_base); 779 780 /* 781 * Get the root node descriptor based on the peripheral base, HN-D node 782 * identifier and mesh size. 783 * 784 * \param base CMN_SKEENA peripheral base address 785 * \param hnd_node_id HN-D node identifier containing the global configuration 786 * \param mesh_size_x Size of the mesh along the x-axis 787 * \param mesh_size_y Size of the mesh along the x-axis 788 * 789 * \return Pointer to the root node descriptor 790 */ 791 struct cmn_skeena_cfgm_reg *get_root_node( 792 uintptr_t base, 793 unsigned int hnd_node_id, 794 unsigned int mesh_size_x, 795 unsigned int mesh_size_y); 796 797 /* 798 * Check if CMN_SKEENA supports CAL mode. CAL mode is supported from CMN_SKEENA 799 * r2p0. 800 * 801 * \param root Pointer to the root node descriptor 802 * 803 * \retval true if the CMN_SKEENA revision is found to be r2p0 or above 804 * \retval false if the CMN_SKEENA revision is found to be r1p3 or below 805 */ 806 bool is_cal_mode_supported(struct cmn_skeena_cfgm_reg *root); 807 808 #endif /* CMN_SKEENA_H */ 809