1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * DMC-500 module. 9 */ 10 11 /* The use of "primary" may not be in sync with older versions of TRM */ 12 13 #ifndef MOD_DMC500_H 14 #define MOD_DMC500_H 15 16 #include <fwk_id.h> 17 #include <fwk_macros.h> 18 #include <fwk_module.h> 19 20 #include <stdint.h> 21 22 /*! 23 * \addtogroup GroupModules Modules 24 * \{ 25 */ 26 27 /*! 28 * \addtogroup GroupDMC DMC-500 Driver 29 * 30 * \details Please consult the Arm CoreLink DMC-500 Dynamic Memory Controller 31 * Technical Reference Manual for details on the specific registers that 32 * are programmed here. 33 * \{ 34 */ 35 36 /*! 37 * \brief DMC-500 register definitions 38 */ 39 struct mod_dmc500_reg { 40 /*! 41 * \cond 42 */ 43 FWK_R uint32_t SI0_SI_STATUS; 44 FWK_R uint32_t SI0_SI_INTERRUPT_STATUS; 45 FWK_R uint32_t SI0_TZ_FAIL_ADDRESS_LOW; 46 FWK_R uint32_t SI0_TZ_FAIL_ADDRESS_HIGH; 47 FWK_R uint32_t SI0_TZ_FAIL_CONTROL; 48 FWK_R uint32_t SI0_TZ_FAIL_ID; 49 FWK_R uint32_t SI0_PMU_REQ_INT_INFO; 50 FWK_RW uint32_t SI0_PMU_REQ_COUNT0; 51 FWK_RW uint32_t SI0_PMU_REQ_COUNT1; 52 FWK_RW uint32_t SI0_PMU_REQ_COUNT2; 53 FWK_RW uint32_t SI0_PMU_REQ_COUNT3; 54 FWK_RW uint32_t SI0_PMU_SCLK_COUNT_COUNT; 55 FWK_RW uint32_t SI0_SI_STATE_CONTROL; 56 FWK_W uint32_t SI0_SI_FLUSH_CONTROL; 57 FWK_RW uint32_t ADDRESS_CONTROL; 58 FWK_RW uint32_t DECODE_CONTROL; 59 FWK_RW uint32_t ADDRESS_MAP; 60 FWK_RW uint32_t RANK_REMAP_CONTROL; 61 FWK_RW uint32_t SI0_SI_INTERRUPT_CONTROL; 62 FWK_W uint32_t SI0_SI_INTERRUPT_CLR; 63 FWK_RW uint32_t TZ_ACTION; 64 FWK_R uint32_t SI0_TZ_REGION_BASE_LOW_0; 65 FWK_R uint32_t SI0_TZ_REGION_BASE_HIGH_0; 66 FWK_RW uint32_t SI0_TZ_REGION_TOP_LOW_0; 67 FWK_RW uint32_t SI0_TZ_REGION_TOP_HIGH_0; 68 FWK_RW uint32_t SI0_TZ_REGION_ATTRIBUTES_0; 69 FWK_RW uint32_t SI0_TZ_REGION_ID_ACCESS_0; 70 FWK_RW uint32_t SI0_TZ_REGION_BASE_LOW_1; 71 FWK_RW uint32_t SI0_TZ_REGION_BASE_HIGH_1; 72 FWK_RW uint32_t SI0_TZ_REGION_TOP_LOW_1; 73 FWK_RW uint32_t SI0_TZ_REGION_TOP_HIGH_1; 74 FWK_RW uint32_t SI0_TZ_REGION_ATTRIBUTES_1; 75 FWK_RW uint32_t SI0_TZ_REGION_ID_ACCESS_1; 76 FWK_RW uint32_t SI0_TZ_REGION_BASE_LOW_2; 77 FWK_RW uint32_t SI0_TZ_REGION_BASE_HIGH_2; 78 FWK_RW uint32_t SI0_TZ_REGION_TOP_LOW_2; 79 FWK_RW uint32_t SI0_TZ_REGION_TOP_HIGH_2; 80 FWK_RW uint32_t SI0_TZ_REGION_ATTRIBUTES_2; 81 FWK_RW uint32_t SI0_TZ_REGION_ID_ACCESS_2; 82 FWK_RW uint32_t SI0_TZ_REGION_BASE_LOW_3; 83 FWK_RW uint32_t SI0_TZ_REGION_BASE_HIGH_3; 84 FWK_RW uint32_t SI0_TZ_REGION_TOP_LOW_3; 85 FWK_RW uint32_t SI0_TZ_REGION_TOP_HIGH_3; 86 FWK_RW uint32_t SI0_TZ_REGION_ATTRIBUTES_3; 87 FWK_RW uint32_t SI0_TZ_REGION_ID_ACCESS_3; 88 FWK_RW uint32_t SI0_TZ_REGION_BASE_LOW_4; 89 FWK_RW uint32_t SI0_TZ_REGION_BASE_HIGH_4; 90 FWK_RW uint32_t SI0_TZ_REGION_TOP_LOW_4; 91 FWK_RW uint32_t SI0_TZ_REGION_TOP_HIGH_4; 92 FWK_RW uint32_t SI0_TZ_REGION_ATTRIBUTES_4; 93 FWK_RW uint32_t SI0_TZ_REGION_ID_ACCESS_4; 94 FWK_RW uint32_t SI0_TZ_REGION_BASE_LOW_5; 95 FWK_RW uint32_t SI0_TZ_REGION_BASE_HIGH_5; 96 FWK_RW uint32_t SI0_TZ_REGION_TOP_LOW_5; 97 FWK_RW uint32_t SI0_TZ_REGION_TOP_HIGH_5; 98 FWK_RW uint32_t SI0_TZ_REGION_ATTRIBUTES_5; 99 FWK_RW uint32_t SI0_TZ_REGION_ID_ACCESS_5; 100 FWK_RW uint32_t SI0_TZ_REGION_BASE_LOW_6; 101 FWK_RW uint32_t SI0_TZ_REGION_BASE_HIGH_6; 102 FWK_RW uint32_t SI0_TZ_REGION_TOP_LOW_6; 103 FWK_RW uint32_t SI0_TZ_REGION_TOP_HIGH_6; 104 FWK_RW uint32_t SI0_TZ_REGION_ATTRIBUTES_6; 105 FWK_RW uint32_t SI0_TZ_REGION_ID_ACCESS_6; 106 FWK_RW uint32_t SI0_TZ_REGION_BASE_LOW_7; 107 FWK_RW uint32_t SI0_TZ_REGION_BASE_HIGH_7; 108 FWK_RW uint32_t SI0_TZ_REGION_TOP_LOW_7; 109 FWK_RW uint32_t SI0_TZ_REGION_TOP_HIGH_7; 110 FWK_RW uint32_t SI0_TZ_REGION_ATTRIBUTES_7; 111 FWK_RW uint32_t SI0_TZ_REGION_ID_ACCESS_7; 112 FWK_RW uint32_t SI0_TZ_REGION_BASE_LOW_8; 113 FWK_RW uint32_t SI0_TZ_REGION_BASE_HIGH_8; 114 FWK_RW uint32_t SI0_TZ_REGION_TOP_LOW_8; 115 FWK_RW uint32_t SI0_TZ_REGION_TOP_HIGH_8; 116 FWK_RW uint32_t SI0_TZ_REGION_ATTRIBUTES_8; 117 FWK_RW uint32_t SI0_TZ_REGION_ID_ACCESS_8; 118 FWK_RW uint32_t SI0_PMU_REQ_CONTROL; 119 FWK_RW uint32_t SI0_PMU_REQ_ATTRIBUTE_MASK_0; 120 FWK_RW uint32_t SI0_PMU_REQ_ATTRIBUTE_MATCH_0; 121 FWK_RW uint32_t SI0_PMU_REQ_ATTRIBUTE_MASK_1; 122 FWK_RW uint32_t SI0_PMU_REQ_ATTRIBUTE_MATCH_1; 123 FWK_RW uint32_t SI0_PMU_REQ_ATTRIBUTE_MASK_2; 124 FWK_RW uint32_t SI0_PMU_REQ_ATTRIBUTE_MATCH_2; 125 FWK_RW uint32_t SI0_PMU_REQ_ATTRIBUTE_MASK_3; 126 FWK_RW uint32_t SI0_PMU_REQ_ATTRIBUTE_MATCH_3; 127 FWK_RW uint32_t SI0_THRESHOLD_CONTROL; 128 uint8_t RESERVED0[0x200 - 0x154]; 129 FWK_R uint32_t SI1_SI_STATUS; 130 FWK_R uint32_t SI1_SI_INTERRUPT_STATUS; 131 FWK_R uint32_t SI1_TZ_FAIL_ADDRESS_LOW; 132 FWK_R uint32_t SI1_TZ_FAIL_ADDRESS_HIGH; 133 FWK_R uint32_t SI1_TZ_FAIL_CONTROL; 134 FWK_R uint32_t SI1_TZ_FAIL_ID; 135 FWK_R uint32_t SI1_PMU_REQ_INT_INFO; 136 FWK_RW uint32_t SI1_PMU_REQ_COUNT0; 137 FWK_RW uint32_t SI1_PMU_REQ_COUNT1; 138 FWK_RW uint32_t SI1_PMU_REQ_COUNT2; 139 FWK_RW uint32_t SI1_PMU_REQ_COUNT3; 140 FWK_RW uint32_t SI1_PMU_SCLK_COUNT_COUNT; 141 FWK_RW uint32_t SI1_SI_STATE_CONTROL; 142 FWK_W uint32_t SI1_SI_FLUSH_CONTROL; 143 uint8_t RESERVED1[0x248 - 0x238]; 144 FWK_RW uint32_t SI1_SI_INTERRUPT_CONTROL; 145 FWK_W uint32_t SI1_SI_INTERRUPT_CLR; 146 uint32_t RESERVED2; 147 FWK_R uint32_t SI1_TZ_REGION_BASE_LOW_0; 148 FWK_R uint32_t SI1_TZ_REGION_BASE_HIGH_0; 149 FWK_RW uint32_t SI1_TZ_REGION_TOP_LOW_0; 150 FWK_RW uint32_t SI1_TZ_REGION_TOP_HIGH_0; 151 FWK_RW uint32_t SI1_TZ_REGION_ATTRIBUTES_0; 152 FWK_RW uint32_t SI1_TZ_REGION_ID_ACCESS_0; 153 FWK_RW uint32_t SI1_TZ_REGION_BASE_LOW_1; 154 FWK_RW uint32_t SI1_TZ_REGION_BASE_HIGH_1; 155 FWK_RW uint32_t SI1_TZ_REGION_TOP_LOW_1; 156 FWK_RW uint32_t SI1_TZ_REGION_TOP_HIGH_1; 157 FWK_RW uint32_t SI1_TZ_REGION_ATTRIBUTES_1; 158 FWK_RW uint32_t SI1_TZ_REGION_ID_ACCESS_1; 159 FWK_RW uint32_t SI1_TZ_REGION_BASE_LOW_2; 160 FWK_RW uint32_t SI1_TZ_REGION_BASE_HIGH_2; 161 FWK_RW uint32_t SI1_TZ_REGION_TOP_LOW_2; 162 FWK_RW uint32_t SI1_TZ_REGION_TOP_HIGH_2; 163 FWK_RW uint32_t SI1_TZ_REGION_ATTRIBUTES_2; 164 FWK_RW uint32_t SI1_TZ_REGION_ID_ACCESS_2; 165 FWK_RW uint32_t SI1_TZ_REGION_BASE_LOW_3; 166 FWK_RW uint32_t SI1_TZ_REGION_BASE_HIGH_3; 167 FWK_RW uint32_t SI1_TZ_REGION_TOP_LOW_3; 168 FWK_RW uint32_t SI1_TZ_REGION_TOP_HIGH_3; 169 FWK_RW uint32_t SI1_TZ_REGION_ATTRIBUTES_3; 170 FWK_RW uint32_t SI1_TZ_REGION_ID_ACCESS_3; 171 FWK_RW uint32_t SI1_TZ_REGION_BASE_LOW_4; 172 FWK_RW uint32_t SI1_TZ_REGION_BASE_HIGH_4; 173 FWK_RW uint32_t SI1_TZ_REGION_TOP_LOW_4; 174 FWK_RW uint32_t SI1_TZ_REGION_TOP_HIGH_4; 175 FWK_RW uint32_t SI1_TZ_REGION_ATTRIBUTES_4; 176 FWK_RW uint32_t SI1_TZ_REGION_ID_ACCESS_4; 177 FWK_RW uint32_t SI1_TZ_REGION_BASE_LOW_5; 178 FWK_RW uint32_t SI1_TZ_REGION_BASE_HIGH_5; 179 FWK_RW uint32_t SI1_TZ_REGION_TOP_LOW_5; 180 FWK_RW uint32_t SI1_TZ_REGION_TOP_HIGH_5; 181 FWK_RW uint32_t SI1_TZ_REGION_ATTRIBUTES_5; 182 FWK_RW uint32_t SI1_TZ_REGION_ID_ACCESS_5; 183 FWK_RW uint32_t SI1_TZ_REGION_BASE_LOW_6; 184 FWK_RW uint32_t SI1_TZ_REGION_BASE_HIGH_6; 185 FWK_RW uint32_t SI1_TZ_REGION_TOP_LOW_6; 186 FWK_RW uint32_t SI1_TZ_REGION_TOP_HIGH_6; 187 FWK_RW uint32_t SI1_TZ_REGION_ATTRIBUTES_6; 188 FWK_RW uint32_t SI1_TZ_REGION_ID_ACCESS_6; 189 FWK_RW uint32_t SI1_TZ_REGION_BASE_LOW_7; 190 FWK_RW uint32_t SI1_TZ_REGION_BASE_HIGH_7; 191 FWK_RW uint32_t SI1_TZ_REGION_TOP_LOW_7; 192 FWK_RW uint32_t SI1_TZ_REGION_TOP_HIGH_7; 193 FWK_RW uint32_t SI1_TZ_REGION_ATTRIBUTES_7; 194 FWK_RW uint32_t SI1_TZ_REGION_ID_ACCESS_7; 195 FWK_RW uint32_t SI1_TZ_REGION_BASE_LOW_8; 196 FWK_RW uint32_t SI1_TZ_REGION_BASE_HIGH_8; 197 FWK_RW uint32_t SI1_TZ_REGION_TOP_LOW_8; 198 FWK_RW uint32_t SI1_TZ_REGION_TOP_HIGH_8; 199 FWK_RW uint32_t SI1_TZ_REGION_ATTRIBUTES_8; 200 FWK_RW uint32_t SI1_TZ_REGION_ID_ACCESS_8; 201 FWK_RW uint32_t SI1_PMU_REQ_CONTROL; 202 FWK_RW uint32_t SI1_PMU_REQ_ATTRIBUTE_MASK_0; 203 FWK_RW uint32_t SI1_PMU_REQ_ATTRIBUTE_MATCH_0; 204 FWK_RW uint32_t SI1_PMU_REQ_ATTRIBUTE_MASK_1; 205 FWK_RW uint32_t SI1_PMU_REQ_ATTRIBUTE_MATCH_1; 206 FWK_RW uint32_t SI1_PMU_REQ_ATTRIBUTE_MASK_2; 207 FWK_RW uint32_t SI1_PMU_REQ_ATTRIBUTE_MATCH_2; 208 FWK_RW uint32_t SI1_PMU_REQ_ATTRIBUTE_MASK_3; 209 FWK_RW uint32_t SI1_PMU_REQ_ATTRIBUTE_MATCH_3; 210 FWK_RW uint32_t SI1_THRESHOLD_CONTROL; 211 uint8_t RESERVED3[0x400 - 0x354]; 212 FWK_R uint32_t DCB_STATUS; 213 FWK_R uint32_t M_INTERRUPT_STATUS; 214 FWK_R uint32_t PMU_DCB_INT_INFO; 215 FWK_W uint32_t DCB_STATE_CONTROL; 216 uint32_t RESERVED4; 217 FWK_RW uint32_t QUEUE_THRESHOLD_CONTROL_31_00; 218 FWK_RW uint32_t QUEUE_THRESHOLD_CONTROL_63_32; 219 uint8_t RESERVED5[0x42C - 0x41C]; 220 FWK_RW uint32_t DCB_INTERRUPT_CONTROL; 221 FWK_W uint32_t DCB_INTERRUPT_CLR; 222 FWK_RW uint32_t PMU_DCB_CONTROL; 223 FWK_RW uint32_t PMU_DATA_CONTROL_BLOCK_ATTRIBUTE_MASK_0; 224 FWK_RW uint32_t PMU_DATA_CONTROL_BLOCK_ATTRIBUTE_MATCH_0; 225 FWK_RW uint32_t PMU_DATA_CONTROL_BLOCK_COUNT_0; 226 FWK_RW uint32_t PMU_DATA_CONTROL_BLOCK_ATTRIBUTE_MASK_1; 227 FWK_RW uint32_t PMU_DATA_CONTROL_BLOCK_ATTRIBUTE_MATCH_1; 228 FWK_RW uint32_t PMU_DATA_CONTROL_BLOCK_COUNT_1; 229 FWK_RW uint32_t PMU_DATA_CONTROL_BLOCK_ATTRIBUTE_MASK_2; 230 FWK_RW uint32_t PMU_DATA_CONTROL_BLOCK_ATTRIBUTE_MATCH_2; 231 FWK_RW uint32_t PMU_DATA_CONTROL_BLOCK_COUNT_2; 232 FWK_RW uint32_t PMU_TAG_ENTRIES_ATTRIBUTE_MASK; 233 FWK_RW uint32_t PMU_TAG_ENTRIES_ATTRIBUTE_MATCH; 234 FWK_RW uint32_t PMU_TAG_ENTRIES_COUNT; 235 FWK_RW uint32_t PMU_MCLK_COUNT_COUNT; 236 uint32_t RESERVED6; 237 FWK_R uint32_t ERR_RAMECC_FR; 238 uint32_t RESERVED7; 239 FWK_RW uint32_t ERR_RAMECC_CTLR; 240 uint32_t RESERVED8; 241 FWK_RW uint32_t ERR_RAMECC_STATUS; 242 uint32_t RESERVED9; 243 FWK_RW uint32_t ERR_RAMECC_ADDR; 244 FWK_RW uint32_t ERR_RAMECC_ADDR2; 245 FWK_RW uint32_t ERR_RAMECC_MISC0; 246 uint32_t RESERVED10[3]; 247 FWK_W uint32_t ERR_RAMECC_INJECT; 248 uint8_t RESERVED11[0x500 - 0x4A4]; 249 FWK_R uint32_t QUEUE_STATUS; 250 uint32_t RESERVED12; 251 FWK_R uint32_t PMU_QE_INT_INFO; 252 FWK_RW uint32_t QUEUE_STATE_CONTROL; 253 FWK_RW uint32_t QE_INTERRUPT_CONTROL; 254 FWK_W uint32_t QE_INTERRUPT_CLR; 255 FWK_RW uint32_t RANK_TURNAROUND_CONTROL; 256 FWK_RW uint32_t HIT_TURNAROUND_CONTROL; 257 FWK_RW uint32_t QOS_CLASS_CONTROL; 258 FWK_RW uint32_t ESCALATION_CONTROL; 259 FWK_RW uint32_t QV_CONTROL_31_00; 260 FWK_RW uint32_t QV_CONTROL_63_32; 261 FWK_RW uint32_t RT_CONTROL_31_00; 262 FWK_RW uint32_t RT_CONTROL_63_32; 263 FWK_RW uint32_t TIMEOUT_CONTROL; 264 FWK_RW uint32_t WRITE_PRIORITY_CONTROL_31_00; 265 FWK_RW uint32_t WRITE_PRIORITY_CONTROL_63_32; 266 uint32_t RESERVED13; 267 FWK_RW uint32_t DIR_TURNAROUND_CONTROL; 268 FWK_RW uint32_t HIT_PREDICTION_CONTROL; 269 FWK_RW uint32_t REFRESH_ENABLE; 270 FWK_R uint32_t REFRESH_STATUS; 271 FWK_R uint32_t REFRESH_STATUS_FG; 272 FWK_RW uint32_t REFRESH_PRIORITY; 273 FWK_RW uint32_t MC_UPDATE_CONTROL; 274 FWK_RW uint32_t PHY_UPDATE_CONTROL; 275 FWK_RW uint32_t PHY_PRIMARY_CONTROL; 276 FWK_RW uint32_t LOW_POWER_CONTROL; 277 FWK_RW uint32_t PMU_QE_CONTROL; 278 FWK_RW uint32_t PMU_QE_MUX; 279 FWK_RW uint32_t PMU_QOS_ENGINE_ATTRIBUTE_MASK_0; 280 FWK_RW uint32_t PMU_QOS_ENGINE_ATTRIBUTE_MATCH_0; 281 FWK_RW uint32_t PMU_QOS_ENGINE_COUNT_0; 282 FWK_RW uint32_t PMU_QOS_ENGINE_ATTRIBUTE_MASK_1; 283 FWK_RW uint32_t PMU_QOS_ENGINE_ATTRIBUTE_MATCH_1; 284 FWK_RW uint32_t PMU_QOS_ENGINE_COUNT_1; 285 FWK_RW uint32_t PMU_QOS_ENGINE_ATTRIBUTE_MASK_2; 286 FWK_RW uint32_t PMU_QOS_ENGINE_ATTRIBUTE_MATCH_2; 287 FWK_RW uint32_t PMU_QOS_ENGINE_COUNT_2; 288 FWK_RW uint32_t PMU_QUEUED_ENTRIES_ATTRIBUTE_MASK; 289 FWK_RW uint32_t PMU_QUEUED_ENTRIES_ATTRIBUTE_MATCH; 290 FWK_RW uint32_t PMU_QUEUED_ENTRIES_COUNT; 291 uint8_t RESERVED14[0x600 - 0x5A8]; 292 FWK_R uint32_t MI_STATUS; 293 FWK_R uint32_t RANKS_READY; 294 FWK_R uint32_t RANKS_RESET; 295 FWK_R uint32_t RANKS_DEEP_POWER_DOWN; 296 FWK_R uint32_t RANKS_SELF_REFRESH; 297 FWK_R uint32_t RANKS_POWERED_DOWN; 298 FWK_R uint32_t RANKS_CLOCK_DISABLED; 299 FWK_R uint32_t PHY_STATUS0; 300 FWK_R uint32_t PHY_STATUS1; 301 uint32_t RESERVED15; 302 FWK_R uint32_t PMU_MI_INT_INFO; 303 uint32_t RESERVED16; 304 FWK_RW uint32_t MI_STATE_CONTROL; 305 FWK_RW uint32_t PHY_CONFIG; 306 FWK_RW uint32_t DIRECT_CMD_SETTINGS; 307 FWK_RW uint32_t DIRECT_CMD; 308 FWK_RW uint32_t DIRECT_CLK_DISABLE; 309 FWK_RW uint32_t DIRECT_ODT; 310 FWK_RW uint32_t DCI_STRB; 311 FWK_RW uint32_t DCI_DATA; 312 FWK_W uint32_t DCI_DATA_CLR; 313 FWK_W uint32_t RANK_STATUS_OVERRIDE; 314 FWK_W uint32_t CLK_STATUS_OVERRIDE; 315 FWK_W uint32_t BANK_STATUS_OVERRIDE; 316 FWK_RW uint32_t MI_INTERRUPT_CONTROL; 317 FWK_W uint32_t MI_INTERRUPT_CLR; 318 FWK_RW uint32_t MEMORY_TYPE; 319 FWK_RW uint32_t FORMAT_CONTROL; 320 FWK_RW uint32_t FEATURE_CONTROL; 321 FWK_RW uint32_t POWER_DOWN_CONTROL; 322 FWK_RW uint32_t REFRESH_CONTROL; 323 FWK_RW uint32_t ODT_WR_CONTROL_31_00; 324 uint32_t RESERVED17; 325 FWK_RW uint32_t ODT_RD_CONTROL_31_00; 326 uint32_t RESERVED18; 327 FWK_RW uint32_t PHY_WRDATA_CS_CONTROL_31_00; 328 uint32_t RESERVED19; 329 FWK_RW uint32_t PHY_RDDATA_CS_CONTROL_31_00; 330 uint32_t RESERVED20; 331 FWK_RW uint32_t PHYUPD_INIT; 332 FWK_RW uint32_t PHY_POWER_CONTROL; 333 uint32_t RESERVED21; 334 FWK_RW uint32_t ODT_TIMING; 335 FWK_RW uint32_t T_REFI; 336 FWK_RW uint32_t T_RFC; 337 FWK_RW uint32_t T_RCD; 338 FWK_RW uint32_t T_RAS; 339 FWK_RW uint32_t T_RP; 340 FWK_RW uint32_t T_RRD; 341 FWK_RW uint32_t T_ACT_WINDOW; 342 FWK_RW uint32_t T_RTR; 343 FWK_RW uint32_t T_RTW; 344 FWK_RW uint32_t T_RTP; 345 FWK_RW uint32_t T_RDPDEN; 346 FWK_RW uint32_t T_WR; 347 FWK_RW uint32_t T_WTR; 348 FWK_RW uint32_t T_WTW; 349 FWK_RW uint32_t T_XTMW; 350 FWK_RW uint32_t T_WRPDEN; 351 FWK_RW uint32_t T_CLOCK_CONTROL; 352 FWK_RW uint32_t T_EP; 353 FWK_RW uint32_t T_XP; 354 FWK_RW uint32_t T_ESR; 355 FWK_RW uint32_t T_XSR; 356 uint32_t RESERVED22; 357 FWK_RW uint32_t T_COMPLETION_CHECKS; 358 FWK_RW uint32_t T_RDDATA_EN; 359 FWK_RW uint32_t T_PHYRDLAT; 360 FWK_RW uint32_t T_PHYWRLAT; 361 FWK_RW uint32_t T_PHY_TRAIN; 362 FWK_R uint32_t ERR_PHY_FR; 363 uint32_t RESERVED23; 364 FWK_RW uint32_t ERR_PHY_CTLR; 365 uint32_t RESERVED24; 366 FWK_RW uint32_t ERR_PHY_STATUS; 367 uint32_t RESERVED25; 368 FWK_RW uint32_t ERR_PHY_ADDR; 369 FWK_RW uint32_t ERR_PHY_ADDR2; 370 FWK_RW uint32_t ERR_PHY_MISC0; 371 uint8_t RESERVED26[0x74C - 0x73C]; 372 FWK_W uint32_t ERR_PHY_INJECT; 373 FWK_RW uint32_t PMU_MI_CONTROL; 374 FWK_RW uint32_t PMU_MEMORY_IF_ATTRIBUTE_MASK_0; 375 FWK_RW uint32_t PMU_MEMORY_IF_ATTRIBUTE_MATCH_0; 376 FWK_RW uint32_t PMU_MEMORY_IF_COUNT_0; 377 FWK_RW uint32_t PMU_MEMORY_IF_ATTRIBUTE_MASK_1; 378 FWK_RW uint32_t PMU_MEMORY_IF_ATTRIBUTE_MATCH_1; 379 FWK_RW uint32_t PMU_MEMORY_IF_COUNT_1; 380 FWK_RW uint32_t PMU_BANK_STATES_ATTRIBUTE_MASK; 381 FWK_RW uint32_t PMU_BANK_STATES_ATTRIBUTE_MATCH; 382 FWK_RW uint32_t PMU_BANK_STATES_COUNT; 383 FWK_RW uint32_t PMU_RANK_STATES_ATTRIBUTE_MASK; 384 FWK_RW uint32_t PMU_RANK_STATES_ATTRIBUTE_MATCH; 385 FWK_RW uint32_t PMU_RANK_STATES_COUNT; 386 uint8_t RESERVED27[0xF00 - 0x784]; 387 FWK_R uint32_t MEMC_CONFIG; 388 uint32_t RESERVED28[3]; 389 FWK_R uint32_t CFG_INTERRUPT_STATUS; 390 FWK_R uint32_t CFG_FAILED_ACCESS_INT_INFO; 391 uint8_t RESERVED29[0xF30 - 0xF18]; 392 FWK_RW uint32_t CFG_INTERRUPT_CONTROL; 393 uint32_t RESERVED30; 394 FWK_W uint32_t CFG_INTERRUPT_CLR; 395 uint8_t RESERVED31[0xFC0 - 0xF3C]; 396 FWK_RW uint32_t INTEGRATION_TEST_CONTROL; 397 FWK_RW uint32_t INTEGRATION_TEST_OUTPUT; 398 uint32_t RESERVED32[2]; 399 FWK_R uint32_t PERIPH_ID_4; 400 uint32_t RESERVED33[3]; 401 FWK_R uint32_t PERIPH_ID_0; 402 FWK_R uint32_t PERIPH_ID_1; 403 FWK_R uint32_t PERIPH_ID_2; 404 FWK_R uint32_t PERIPH_ID_3; 405 FWK_R uint32_t COMPONENT_ID_0; 406 FWK_R uint32_t COMPONENT_ID_1; 407 FWK_R uint32_t COMPONENT_ID_2; 408 FWK_R uint32_t COMPONENT_ID_3; 409 /*! 410 * \endcond 411 */ 412 }; 413 414 /*! 415 * \brief SI_STATE_CONTROL mask used to prevent request stalling. 416 */ 417 #define MOD_DMC500_SI_STATE_CONTROL_GO 0 418 419 /*! 420 * \brief SI_STATE_CONTROL mask used to enable request stalling. 421 */ 422 #define MOD_DMC500_SI_STATE_CONTROL_STALL_REQ (1 << 0) 423 424 /*! 425 * \brief SI_STATUS mask used to confirm that request stalling is active. 426 */ 427 #define MOD_DMC500_SI_STATUS_STALL_ACK (1 << 0) 428 429 /*! 430 * \brief SI_STATUS mask used to read the empty bit. 431 */ 432 #define MOD_DMC500_SI_STATUS_EMPTY (1 << 1) 433 434 /*! 435 * \brief QUEUE_STATE_CONTROL mask used to prevent request stalling. 436 */ 437 #define MOD_DMC500_QUEUE_STATE_CONTROL_GO 0 438 439 /*! 440 * \brief QUEUE_STATE_CONTROL mask used to enable request stalling. 441 */ 442 #define MOD_DMC500_QUEUE_STATE_CONTROL_STALL_REQ (1 << 0) 443 444 /*! 445 * \brief QUEUE_STATUS mask used to confirm that request stalling is active. 446 */ 447 #define MOD_DMC500_QUEUE_STATUS_STALL_ACK (1 << 0) 448 449 /*! 450 * \brief QUEUE_STATUS mask used to read the empty bit. 451 */ 452 #define MOD_DMC500_QUEUE_STATUS_EMPTY (1 << 1) 453 454 /*! 455 * \brief MI_STATUS mask used to read the idle bit. 456 */ 457 #define MOD_DMC500_MI_STATUS_IDLE (1 << 0) 458 459 /*! 460 * \brief MI_STATUS mask used to read the empty bit. 461 */ 462 #define MOD_DMC500_MI_STATUS_EMPTY (1 << 1) 463 464 /*! 465 * \brief Create the ADDRESS_MAP value. 466 * 467 * \param SHUTTER The address shutter. 468 * 469 * \return The ADDRESS_MAP value. 470 */ 471 #define ADDRESS_MAP_VAL(SHUTTER) ((1 << 8) | (SHUTTER)) 472 473 /*! 474 * \brief Create the ADDRESS_CONTROL value. 475 * 476 * \param RANK Number of bits for the rank. 477 * \param BANK Number of bits for the bank. 478 * \param ROW Number of bits for the row. 479 * \param COL Number of bits for the column. 480 * 481 * \return The ADDRESS_CONTROL value. 482 */ 483 #define ADDRESS_CONTROL_VAL(RANK, BANK, ROW, COL) (((RANK) << 24) | \ 484 ((BANK) << 16) | \ 485 ((ROW) << 8) | \ 486 (COL)) 487 488 /*! 489 * \brief Create the MEMORY_TYPE value 490 * 491 * \param BANK_GROUP Bank group. 492 * \param WIDTH Memory device width. 493 * \param TYPE Memory type. 494 * 495 * \return The MEMORY_TYPE value. 496 */ 497 #define MEMORY_TYPE_VAL(BANK_GROUP, WIDTH, TYPE) (((BANK_GROUP) << 16) | \ 498 ((WIDTH) << 8) | \ 499 (TYPE)) 500 501 /*! 502 * \brief Create the FORMAT_CONTROL value. 503 * 504 * \param BURST Memory burst. 505 * 506 * \return The FORMAT_CONTROL value. 507 */ 508 #define FORMAT_CONTROL_VAL(BURST) ((BURST) << 8) 509 510 /*! 511 * \brief Element configuration. 512 */ 513 struct mod_dmc500_element_config { 514 /*! Base address of the DMC-500 device's registers */ 515 uintptr_t dmc; 516 /*! Element identifier of the associated DDR PHY-500 device */ 517 fwk_id_t ddr_phy_id; 518 }; 519 520 /*! 521 * \brief API of the DDR PHY associate to the DMC 522 */ 523 struct mod_dmc_ddr_phy_api { 524 /*! 525 * \brief Configure a DDR PHY500 device 526 * 527 * \param element_id Element identifier corresponding to the device to 528 * configure. 529 * 530 * \retval ::FWK_SUCCESS if the operation succeed. 531 * \return one of the error code otherwise. 532 */ 533 int (*configure)(fwk_id_t element_id); 534 }; 535 536 /*! 537 * \brief DMC-500 module configuration. 538 */ 539 struct mod_dmc500_module_config { 540 /*! 541 * Element identifier of the timer used for delays when programming the 542 * DMC-500 543 */ 544 fwk_id_t timer_id; 545 /*! DDR PHY module ID */ 546 fwk_id_t ddr_phy_module_id; 547 /*! DDR PHY API ID */ 548 fwk_id_t ddr_phy_api_id; 549 /*! Initial value for the dmc registers */ 550 const struct mod_dmc500_reg *reg_val; 551 /*! Pointer to a product-specific function that issues direct commands */ 552 void (*direct_ddr_cmd)(struct mod_dmc500_reg *dmc); 553 }; 554 555 /*! 556 * \brief DMC-500 module description. 557 */ 558 extern const struct fwk_module module_dmc500; 559 560 /*! 561 * \} 562 */ 563 564 /*! 565 * \} 566 */ 567 568 #endif /* MOD_DMC500_H */ 569