1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * PL011 (UART) register definitions 9 */ 10 11 #ifndef PL011_H 12 #define PL011_H 13 14 #include <fwk_macros.h> 15 16 #include <stdint.h> 17 18 struct pl011_reg { 19 FWK_RW uint16_t DR; 20 uint16_t RESERVED0; 21 union { 22 FWK_RW uint8_t RSR; 23 FWK_RW uint8_t ECR; 24 }; 25 uint8_t RESERVED1[0x18 - 0x05]; 26 FWK_R uint16_t FR; 27 uint16_t RESERVED2[3]; 28 FWK_RW uint8_t ILPR; 29 uint8_t RESERVED3[3]; 30 FWK_RW uint16_t IBRD; 31 uint16_t RESERVED4; 32 FWK_RW uint32_t FBRD; 33 FWK_RW uint16_t LCR_H; 34 uint16_t RESERVED5; 35 FWK_RW uint16_t CR; 36 uint16_t RESERVED6; 37 FWK_RW uint16_t IFLS; 38 uint16_t RESERVED7; 39 FWK_RW uint16_t IMSC; 40 uint16_t RESERVED8; 41 FWK_R uint16_t RIS; 42 uint16_t RESERVED9; 43 FWK_R uint16_t MIS; 44 uint16_t RESERVED10; 45 FWK_W uint16_t ICR; 46 uint16_t RESERVED11; 47 FWK_RW uint16_t DMACR; 48 uint8_t RESERVED12[0xFE0 - 0x4C]; 49 FWK_R uint32_t PID0; 50 FWK_R uint32_t PID1; 51 FWK_R uint32_t PID2; 52 FWK_R uint32_t PID3; 53 FWK_R uint32_t CID0; 54 FWK_R uint32_t CID1; 55 FWK_R uint32_t CID2; 56 FWK_R uint32_t CID3; 57 }; 58 59 #define PL011_DR_DATA (uint16_t)0x00FF 60 #define PL011_DR_FE (uint16_t)0x0100 61 #define PL011_DR_PE (uint16_t)0x0200 62 #define PL011_DR_BE (uint16_t)0x0400 63 #define PL011_DR_OE (uint16_t)0x0800 64 65 #define PL011_RSR_FE (uint8_t)0x01 66 #define PL011_RSR_PE (uint8_t)0x02 67 #define PL011_RSR_BE (uint8_t)0x04 68 #define PL011_RSR_OE (uint8_t)0x08 69 #define PL011_ECR_CLR (uint8_t)0xFF 70 71 #define PL011_FR_CTS (uint16_t)0x0001 72 #define PL011_FR_DSR (uint16_t)0x0002 73 #define PL011_FR_DCD (uint16_t)0x0004 74 #define PL011_FR_BUSY (uint16_t)0x0008 75 #define PL011_FR_RXFE (uint16_t)0x0010 76 #define PL011_FR_TXFF (uint16_t)0x0020 77 #define PL011_FR_RXFF (uint16_t)0x0040 78 #define PL011_FR_TXFE (uint16_t)0x0080 79 #define PL011_FR_RI (uint16_t)0x0100 80 81 #define PL011_LCR_H_BRK (uint16_t)0x0001 82 #define PL011_LCR_H_PEN (uint16_t)0x0002 83 #define PL011_LCR_H_EPS (uint16_t)0x0004 84 #define PL011_LCR_H_STP2 (uint16_t)0x0008 85 #define PL011_LCR_H_FEN (uint16_t)0x0010 86 #define PL011_LCR_H_WLEN (uint16_t)0x0060 87 #define PL011_LCR_H_WLEN_5BITS (uint16_t)0x0000 88 #define PL011_LCR_H_WLEN_6BITS (uint16_t)0x0020 89 #define PL011_LCR_H_WLEN_7BITS (uint16_t)0x0040 90 #define PL011_LCR_H_WLEN_8BITS (uint16_t)0x0060 91 #define PL011_LCR_H_SPS (uint16_t)0x0080 92 93 #define PL011_CR_UARTEN (uint16_t)0x0001 94 #define PL011_CR_SIREN (uint16_t)0x0002 95 #define PL011_CR_SIRLP (uint16_t)0x0004 96 #define PL011_CR_LBE (uint16_t)0x0080 97 #define PL011_CR_TXE (uint16_t)0x0100 98 #define PL011_CR_RXE (uint16_t)0x0200 99 #define PL011_CR_DTR (uint16_t)0x0400 100 #define PL011_CR_RTS (uint16_t)0x0800 101 #define PL011_CR_OUT1 (uint16_t)0x1000 102 #define PL011_CR_OUT2 (uint16_t)0x2000 103 #define PL011_CR_RTSEN (uint16_t)0x4000 104 #define PL011_CR_CTSEN (uint16_t)0x8000 105 106 #define PL011_IFLS_TXIFLSEL (uint16_t)0x0007 107 #define PL011_IFLS_RXIFLSEL (uint16_t)0x0038 108 109 #define PL011_IMSC_RIMIM (uint16_t)0x0001 110 #define PL011_IMSC_CTSMIM (uint16_t)0x0002 111 #define PL011_IMSC_DCDMIM (uint16_t)0x0004 112 #define PL011_IMSC_DSRMIM (uint16_t)0x0008 113 #define PL011_IMSC_RXIM (uint16_t)0x0010 114 #define PL011_IMSC_TXIM (uint16_t)0x0020 115 #define PL011_IMSC_RTIM (uint16_t)0x0040 116 #define PL011_IMSC_FEIM (uint16_t)0x0080 117 #define PL011_IMSC_PEIM (uint16_t)0x0100 118 #define PL011_IMSC_BEIM (uint16_t)0x0200 119 #define PL011_IMSC_OEIM (uint16_t)0x0400 120 121 #define PL011_RIS_RIRMIS (uint16_t)0x0001 122 #define PL011_RIS_CTSRMIS (uint16_t)0x0002 123 #define PL011_RIS_DCDRMIS (uint16_t)0x0004 124 #define PL011_RIS_DSRRMIS (uint16_t)0x0008 125 #define PL011_RIS_RXRIS (uint16_t)0x0010 126 #define PL011_RIS_TXRIS (uint16_t)0x0020 127 #define PL011_RIS_RTRIS (uint16_t)0x0040 128 #define PL011_RIS_FERIS (uint16_t)0x0080 129 #define PL011_RIS_PERIS (uint16_t)0x0100 130 #define PL011_RIS_BERIS (uint16_t)0x0200 131 #define PL011_RIS_OERIS (uint16_t)0x0400 132 133 #define PL011_MIS_RIMMIS (uint16_t)0x0001 134 #define PL011_MIS_CTSMMIS (uint16_t)0x0002 135 #define PL011_MIS_DCDMMIS (uint16_t)0x0004 136 #define PL011_MIS_DSRMMIS (uint16_t)0x0008 137 #define PL011_MIS_RXMIS (uint16_t)0x0010 138 #define PL011_MIS_TXMIS (uint16_t)0x0020 139 #define PL011_MIS_RTMIS (uint16_t)0x0040 140 #define PL011_MIS_FEMIS (uint16_t)0x0080 141 #define PL011_MIS_PEMIS (uint16_t)0x0100 142 #define PL011_MIS_BEMIS (uint16_t)0x0200 143 #define PL011_MIS_OEMIS (uint16_t)0x0400 144 145 #define PL011_ICR_RIMIC (uint16_t)0x0001 146 #define PL011_ICR_CTSMIC (uint16_t)0x0002 147 #define PL011_ICR_DCDMIC (uint16_t)0x0004 148 #define PL011_ICR_DSRMIC (uint16_t)0x0008 149 #define PL011_ICR_RXIC (uint16_t)0x0010 150 #define PL011_ICR_TXIC (uint16_t)0x0020 151 #define PL011_ICR_RTIC (uint16_t)0x0040 152 #define PL011_ICR_FEIC (uint16_t)0x0080 153 #define PL011_ICR_PEIC (uint16_t)0x0100 154 #define PL011_ICR_BEIC (uint16_t)0x0200 155 #define PL011_ICR_OEIC (uint16_t)0x0400 156 157 #define PL011_DMACR_RXDMAE (uint16_t)0x0001 158 #define PL011_DMACR_TXDMAE (uint16_t)0x0002 159 #define PL011_DMACR_DMAAONERR (uint16_t)0x0004 160 161 #define PL011_UARTCLK_MIN (1420 * FWK_KHZ) 162 #define PL011_UARTCLK_MAX (542720 * FWK_KHZ) 163 164 #endif /* PL011 */ 165