1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SSC_REG_H 9 #define SSC_REG_H 10 11 #include <fwk_macros.h> 12 13 #include <stdint.h> 14 15 /*! 16 * \brief System Security Control (SSC) register definitions 17 */ 18 struct ssc_reg { 19 uint8_t RESERVED1[0x10 - 0x0]; 20 FWK_R uint32_t SSC_DBGCFG_STAT; 21 FWK_W uint32_t SSC_DBGCFG_SET; 22 FWK_W uint32_t SSC_DBGCFG_CLR; 23 uint8_t RESERVED2[0x28 - 0x1C]; 24 FWK_RW uint32_t SSC_AUXDBGCFG; 25 uint8_t RESERVED3[0x30 - 0x2C]; 26 FWK_RW uint32_t SSC_GPRETN; 27 uint8_t RESERVED4[0x40 - 0x34]; 28 FWK_R uint32_t SSC_VERSION; 29 uint8_t RESERVED5[0x500 - 0x44]; 30 FWK_R uint32_t SSC_CHIPID_ST; 31 uint8_t RESERVED6[0xFD0 - 0x504]; 32 FWK_R uint32_t PID4; 33 uint8_t RESERVED7[0xFE0 - 0xFD4]; 34 FWK_R uint32_t PID0; 35 FWK_R uint32_t PID1; 36 FWK_R uint32_t PID2; 37 FWK_R uint32_t PID3; 38 FWK_R uint32_t COMPID0; 39 FWK_R uint32_t COMPID1; 40 FWK_R uint32_t COMPID2; 41 FWK_R uint32_t COMPID3; 42 }; 43 44 #define SSC_PID0_PART_NUMBER_MASK UINT32_C(0xFF) 45 #define SSC_PID1_PART_NUMBER_MASK UINT32_C(0x0F) 46 #define SSC_PID1_PART_NUMBER_POS 8 47 48 #define SSC_PID2_REVISION_NUMBER_MASK UINT32_C(0xF0) 49 #define SSC_PID2_REVISION_NUMBER_POS 4 50 51 #define SSC_CHIPID_ST_CHIP_ID_MASK UINT32_C(0x3F) 52 #define SSC_CHIPID_ST_MULTI_CHIP_MODE_MASK UINT32_C(0x100) 53 #define SSC_CHIPID_ST_MULTI_CHIP_MODE_POS 8 54 55 #endif /* SSC_REG_H */ 56