1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef CONFIG_CLOCK_H
9 #define CONFIG_CLOCK_H
10 
11 #include <fwk_macros.h>
12 
13 /*
14  * DDR Subsystem clock in MHz
15  */
16 #define DDR_CLOCK_MHZ (4400.0 / 3.0)
17 
18 #define CPU_CLOCK_SUD 2100UL
19 #define CPU_CLOCK_UD  2200UL
20 #define CPU_CLOCK_NOM 2300UL
21 #define CPU_CLOCK_OD  2400UL
22 #define CPU_CLOCK_SOD 2500UL
23 
24 #define CLUS_CLOCK_MHZ 2000UL
25 #define INT_CLOCK_MHZ  1850UL
26 
27 /*
28  * SCC & PIK clock rates.
29  */
30 #define SCC_CLK_RATE_IOFPGA_TMIF2XCLK (150 * FWK_MHZ)
31 #define SCC_CLK_RATE_IOFPGA_TSIF2XCLK (150 * FWK_MHZ)
32 #define SCC_CLK_RATE_SYSAPBCLK (120 * FWK_MHZ)
33 #define SCC_CLK_RATE_SCPNICCLK (300 * FWK_MHZ)
34 #define SCC_CLK_RATE_SCPI2CCLK (100 * FWK_MHZ)
35 #define SCC_CLK_RATE_SCPQSPICLK (50 * FWK_MHZ)
36 #define SCC_CLK_RATE_SENSORCLK  (100 * FWK_MHZ)
37 #define SCC_CLK_RATE_MCPNICCLK  (300 * FWK_MHZ)
38 #define SCC_CLK_RATE_MCPI2CCLK  (100 * FWK_MHZ)
39 #define SCC_CLK_RATE_MCPQSPICLK (50 * FWK_MHZ)
40 #define SCC_CLK_RATE_PCIEAXICLK (1200 * FWK_MHZ)
41 #define SCC_CLK_RATE_CCIXAXICLK (1200 * FWK_MHZ)
42 #define SCC_CLK_RATE_PCIEAPBCLK (200 * FWK_MHZ)
43 #define SCC_CLK_RATE_CCIXAPBCLK (200 * FWK_MHZ)
44 
45 #define PIK_CLK_RATE_CLUS0_CPU (CPU_CLOCK_SOD * FWK_MHZ)
46 #define PIK_CLK_RATE_CLUS1_CPU (CPU_CLOCK_SOD * FWK_MHZ)
47 #define PIK_CLK_RATE_CLUS0 (CLUS_CLOCK_MHZ * FWK_MHZ)
48 #define PIK_CLK_RATE_CLUS1     (CLUS_CLOCK_MHZ * FWK_MHZ)
49 #define PIK_CLK_RATE_CLUS0_PPU (300 * FWK_MHZ)
50 #define PIK_CLK_RATE_CLUS1_PPU (300 * FWK_MHZ)
51 #define PIK_CLK_RATE_CLUS0_PCLK (800 * FWK_MHZ)
52 #define PIK_CLK_RATE_CLUS0_ATCLK (800 * FWK_MHZ)
53 #define PIK_CLK_RATE_CLUS0_GIC (800 * FWK_MHZ)
54 #define PIK_CLK_RATE_CLUS0_AMBACLK (1200 * FWK_MHZ)
55 #define PIK_CLK_RATE_CLUS1_PCLK (800 * FWK_MHZ)
56 #define PIK_CLK_RATE_CLUS1_ATCLK (800 * FWK_MHZ)
57 #define PIK_CLK_RATE_CLUS1_GIC (800 * FWK_MHZ)
58 #define PIK_CLK_RATE_CLUS1_AMBACLK (1200 * FWK_MHZ)
59 
60 #define PIK_CLK_RATE_GPU (650 * FWK_MHZ)
61 #define PIK_CLK_RATE_DPU (350 * FWK_MHZ)
62 
63 #define PIK_CLK_RATE_SCP_CORECLK (300 * FWK_MHZ)
64 #define PIK_CLK_RATE_SCP_AXICLK  (300 * FWK_MHZ)
65 #define PIK_CLK_RATE_SCP_SYNCCLK (150 * FWK_MHZ)
66 
67 #define PIK_CLK_RATE_SYS_PPU (300 * FWK_MHZ)
68 #define PIK_CLK_RATE_INTERCONNECT (INT_CLOCK_MHZ * FWK_MHZ)
69 #define PIK_CLK_RATE_PCLKSCP      (300 * FWK_MHZ)
70 #define PIK_CLK_RATE_SYS_GIC      (800 * FWK_MHZ)
71 #define PIK_CLK_RATE_SYSPCLKDBG   (300 * FWK_MHZ)
72 #define PIK_CLK_RATE_SYSPERCLK    (600 * FWK_MHZ)
73 #define PIK_CLK_RATE_UART         (50 * FWK_MHZ)
74 #define PIK_CLK_RATE_TCU0         (1200 * FWK_MHZ)
75 #define PIK_CLK_RATE_TCU1         (1200 * FWK_MHZ)
76 #define PIK_CLK_RATE_TCU2         (1200 * FWK_MHZ)
77 #define PIK_CLK_RATE_TCU3         (1200 * FWK_MHZ)
78 
79 #define PIK_CLK_RATE_ATCLKDBG (600 * FWK_MHZ)
80 #define PIK_CLK_RATE_PCLKDBG  (300 * FWK_MHZ)
81 #define PIK_CLK_RATE_TRACECLK (300 * FWK_MHZ)
82 #define PIK_CLK_RATE_DMC      (DDR_CLOCK_MHZ * FWK_MHZ)
83 
84 /*
85  * MORELLO PLL clock rates.
86  */
87 #define MORELLO_PLL_RATE_CPU_PLL0         (CPU_CLOCK_SOD * FWK_MHZ)
88 #define MORELLO_PLL_RATE_CPU_PLL1         (CPU_CLOCK_SOD * FWK_MHZ)
89 #define MORELLO_PLL_RATE_CLUSTER_PLL      (CLUS_CLOCK_MHZ * FWK_MHZ)
90 #define MORELLO_PLL_RATE_INTERCONNECT_PLL (INT_CLOCK_MHZ * FWK_MHZ)
91 #define MORELLO_PLL_RATE_SYSTEM_PLL       (2400 * FWK_MHZ)
92 #define MORELLO_PLL_RATE_DMC_PLL          (DDR_CLOCK_MHZ * FWK_MHZ)
93 #define MORELLO_PLL_RATE_GPU_PLL          (650 * FWK_MHZ)
94 #define MORELLO_PLL_RATE_DPU_PLL          (350 * FWK_MHZ)
95 /* 1920x1080 @60Hz */
96 #define MORELLO_PLL_RATE_PIXEL_PLL (148500000UL)
97 
98 /*
99  * CSS clock rates.
100  */
101 #define CSS_CLK_RATE_CPU_GRP0_SUPER_UNDERDRIVE (CPU_CLOCK_SUD * FWK_MHZ)
102 #define CSS_CLK_RATE_CPU_GRP0_UNDERDRIVE       (CPU_CLOCK_UD * FWK_MHZ)
103 #define CSS_CLK_RATE_CPU_GRP0_NOMINAL          (CPU_CLOCK_NOM * FWK_MHZ)
104 #define CSS_CLK_RATE_CPU_GRP0_OVERDRIVE        (CPU_CLOCK_OD * FWK_MHZ)
105 #define CSS_CLK_RATE_CPU_GRP0_SUPER_OVERDRIVE  (CPU_CLOCK_SOD * FWK_MHZ)
106 
107 #define CSS_CLK_RATE_CPU_GRP1_SUPER_UNDERDRIVE (CPU_CLOCK_SUD * FWK_MHZ)
108 #define CSS_CLK_RATE_CPU_GRP1_UNDERDRIVE       (CPU_CLOCK_UD * FWK_MHZ)
109 #define CSS_CLK_RATE_CPU_GRP1_NOMINAL          (CPU_CLOCK_NOM * FWK_MHZ)
110 #define CSS_CLK_RATE_CPU_GRP1_OVERDRIVE        (CPU_CLOCK_OD * FWK_MHZ)
111 #define CSS_CLK_RATE_CPU_GRP1_SUPER_OVERDRIVE  (CPU_CLOCK_SOD * FWK_MHZ)
112 
113 #define CSS_CLK_RATE_GPU_SUPER_UNDERDRIVE (450 * FWK_MHZ)
114 #define CSS_CLK_RATE_GPU_UNDERDRIVE       (500 * FWK_MHZ)
115 #define CSS_CLK_RATE_GPU_NOMINAL          (550 * FWK_MHZ)
116 #define CSS_CLK_RATE_GPU_OVERDRIVE        (600 * FWK_MHZ)
117 #define CSS_CLK_RATE_GPU_SUPER_OVERDRIVE  (650 * FWK_MHZ)
118 
119 #define OSC_FREQ_HZ (24 * FWK_MHZ)
120 /*
121  * Clock indexes.
122  */
123 enum clock_idx {
124     CLOCK_IDX_INTERCONNECT,
125     CLOCK_IDX_CPU_GROUP0,
126     CLOCK_IDX_CPU_GROUP1,
127     CLOCK_IDX_GPU,
128     CLOCK_IDX_DPU,
129     CLOCK_IDX_PIXEL_0,
130     CLOCK_IDX_COUNT
131 };
132 
133 /*
134  * SCC & PIK clock indexes.
135  */
136 enum clock_pik_idx {
137     /* SCC Clocks */
138     CLOCK_SCC_IDX_IOFPGA_TMIF2XCLK,
139     CLOCK_SCC_IDX_IOFPGA_TSIF2XCLK,
140     CLOCK_SCC_IDX_SYSAPBCLK,
141     CLOCK_SCC_IDX_SCPNICCLK,
142     CLOCK_SCC_IDX_SCPI2CCLK,
143     CLOCK_SCC_IDX_SCPQSPICLK,
144     CLOCK_SCC_IDX_SENSORCLK,
145     CLOCK_SCC_IDX_MCPNICCLK,
146     CLOCK_SCC_IDX_MCPI2CCLK,
147     CLOCK_SCC_IDX_MCPQSPICLK,
148     CLOCK_SCC_IDX_PCIEAXICLK,
149     CLOCK_SCC_IDX_CCIXAXICLK,
150     CLOCK_SCC_IDX_PCIEAPBCLK,
151     CLOCK_SCC_IDX_CCIXAPBCLK,
152 
153     /* PIK Clocks */
154 
155     /* CPU element clocks */
156     CLOCK_PIK_IDX_CLUS0_CPU0,
157     CLOCK_PIK_IDX_CLUS0_CPU1,
158     CLOCK_PIK_IDX_CLUS1_CPU0,
159     CLOCK_PIK_IDX_CLUS1_CPU1,
160     CLOCK_PIK_IDX_CLUS0,
161     CLOCK_PIK_IDX_CLUS1,
162     CLOCK_PIK_IDX_CLUS0_PPU,
163     CLOCK_PIK_IDX_CLUS1_PPU,
164     CLOCK_PIK_IDX_CLUS0_PCLK,
165     CLOCK_PIK_IDX_CLUS0_ATCLK,
166     CLOCK_PIK_IDX_CLUS0_GIC,
167     CLOCK_PIK_IDX_CLUS0_AMBACLK,
168     CLOCK_PIK_IDX_CLUS1_PCLK,
169     CLOCK_PIK_IDX_CLUS1_ATCLK,
170     CLOCK_PIK_IDX_CLUS1_GIC,
171     CLOCK_PIK_IDX_CLUS1_AMBACLK,
172     /* Multimedia element clocks */
173     CLOCK_PIK_IDX_GPU,
174     CLOCK_PIK_IDX_DPU,
175     /* SCP element clocks */
176     CLOCK_PIK_IDX_SCP_CORECLK,
177     CLOCK_PIK_IDX_SCP_AXICLK,
178     CLOCK_PIK_IDX_SCP_SYNCCLK,
179     /* Top element clocks */
180     CLOCK_PIK_IDX_SYS_PPU,
181     CLOCK_PIK_IDX_INTERCONNECT,
182     CLOCK_PIK_IDX_PCLKSCP,
183     CLOCK_PIK_IDX_SYS_GIC,
184     CLOCK_PIK_IDX_SYSPCLKDBG,
185     CLOCK_PIK_IDX_SYSPERCLK,
186     CLOCK_PIK_IDX_UART,
187     CLOCK_PIK_IDX_TCU0,
188     CLOCK_PIK_IDX_TCU1,
189     CLOCK_PIK_IDX_TCU2,
190     CLOCK_PIK_IDX_TCU3,
191     /* Debug element clocks */
192     CLOCK_PIK_IDX_ATCLKDBG,
193     CLOCK_PIK_IDX_PCLKDBG,
194     CLOCK_PIK_IDX_TRACECLK,
195     /* DMC element clock */
196     CLOCK_PIK_IDX_DMC,
197     /* Number of generated clocks */
198     CLOCK_PIK_IDX_COUNT
199 };
200 
201 /*
202  * CSS clock indexes.
203  */
204 enum clock_css_idx {
205     CLOCK_CSS_IDX_CPU_GROUP0,
206     CLOCK_CSS_IDX_CPU_GROUP1,
207     CLOCK_CSS_IDX_GPU,
208     CLOCK_CSS_IDX_DPU,
209     CLOCK_CSS_IDX_COUNT
210 };
211 
212 /*
213  * SoC PLL indexes.
214  */
215 enum clock_pll_idx {
216     CLOCK_PLL_IDX_CPU0,
217     CLOCK_PLL_IDX_CPU1,
218     CLOCK_PLL_IDX_CLUS,
219     CLOCK_PLL_IDX_INTERCONNECT,
220     CLOCK_PLL_IDX_SYS,
221     CLOCK_PLL_IDX_DMC,
222     CLOCK_PLL_IDX_GPU,
223     CLOCK_PLL_IDX_DPU,
224     CLOCK_PLL_IDX_PXL,
225     CLOCK_PLL_IDX_COUNT
226 };
227 
228 #endif /* CONFIG_CLOCK_H */
229