1 /*
2 * Renesas SCP/MCP Software
3 * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights
4 * reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <system_clock.h>
10
11 #include <mod_rcar_clock.h>
12
13 #include <fwk_element.h>
14 #include <fwk_id.h>
15 #include <fwk_macros.h>
16 #include <fwk_module.h>
17
18 /*
19 * Rate lookup tables
20 */
21
22 static struct mod_rcar_clock_rate rate_table_cpu_a53[] = {
23 {
24 .rate = 800 * FWK_MHZ,
25 .source = MOD_RCAR_CLOCK_CLUSCLK_SOURCE_PLL2,
26 .divider_reg = MOD_RCAR_CLOCK_A53_DIVIDER_DIV_EXT,
27 .divider = 1, /* Rate adjusted via CPU PLL */
28 },
29 {
30 .rate = 1000 * FWK_MHZ,
31 .source = MOD_RCAR_CLOCK_CLUSCLK_SOURCE_PLL2,
32 .divider_reg = MOD_RCAR_CLOCK_A53_DIVIDER_DIV_EXT,
33 .divider = 1, /* Rate adjusted via CPU PLL */
34 },
35 {
36 .rate = 1200 * FWK_MHZ,
37 .source = MOD_RCAR_CLOCK_CLUSCLK_SOURCE_PLL2,
38 .divider_reg = MOD_RCAR_CLOCK_A53_DIVIDER_DIV_EXT,
39 .divider = 1, /* Rate adjusted via CPU PLL */
40 },
41 };
42
43 static struct mod_rcar_clock_rate rate_table_cpu_a57[] = {
44 {
45 .rate = 500 * FWK_MHZ,
46 .source = MOD_RCAR_CLOCK_CLUSCLK_SOURCE_PLL0,
47 .divider_reg = MOD_RCAR_CLOCK_A57_DIVIDER_DIV_EXT,
48 .divider = 1, /* Rate adjusted via CPU PLL */
49 },
50 {
51 .rate = 1000 * FWK_MHZ,
52 .source = MOD_RCAR_CLOCK_CLUSCLK_SOURCE_PLL0,
53 .divider_reg = MOD_RCAR_CLOCK_A57_DIVIDER_DIV_EXT,
54 .divider = 1, /* Rate adjusted via CPU PLL */
55 },
56 {
57 .rate = 1500 * FWK_MHZ,
58 .source = MOD_RCAR_CLOCK_CLUSCLK_SOURCE_PLL0,
59 .divider_reg = MOD_RCAR_CLOCK_A57_DIVIDER_DIV_EXT,
60 .divider = 1, /* Rate adjusted via CPU PLL */
61 },
62 {
63 .rate = 1600 * FWK_MHZ,
64 .source = MOD_RCAR_CLOCK_CLUSCLK_SOURCE_PLL0,
65 .divider_reg = MOD_RCAR_CLOCK_A57_DIVIDER_DIV_EXT,
66 .divider = 1, /* Rate adjusted via CPU PLL */
67 },
68 {
69 .rate = 1700 * FWK_MHZ,
70 .source = MOD_RCAR_CLOCK_CLUSCLK_SOURCE_PLL0,
71 .divider_reg = MOD_RCAR_CLOCK_A57_DIVIDER_DIV_EXT,
72 .divider = 1, /* Rate adjusted via CPU PLL */
73 },
74 };
75
76 static const struct fwk_element rcar_clock_element_table[] = {
77 /*
78 * A53 CPUS
79 */
80 {
81 .name = "CLUS0_CPU0",
82 .data = &((struct mod_rcar_clock_dev_config){
83 .type = MOD_RCAR_CLOCK_TYPE_CLUSTER,
84 .is_group_member = false,
85 .rate_table = rate_table_cpu_a53,
86 .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_a53),
87 .initial_rate = 1200 * FWK_MHZ,
88 .defer_initialization = false,
89 }),
90 },
91 /*
92 * A57 CPUS
93 */
94 {
95 .name = "CLUS0_CPU4",
96 .data = &((struct mod_rcar_clock_dev_config){
97 .type = MOD_RCAR_CLOCK_TYPE_CLUSTER,
98 .is_group_member = false,
99 .rate_table = rate_table_cpu_a57,
100 .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_a57),
101 .initial_rate = 1500 * FWK_MHZ,
102 .defer_initialization = false,
103 }),
104 },
105 /*
106 * VPU
107 */
108 {
109 .name = "VPU",
110 .data = &((struct mod_rcar_clock_dev_config){
111 .type = MOD_RCAR_CLOCK_TYPE_MULTI_SOURCE,
112 .is_group_member = true,
113 .initial_rate = 600 * FWK_MHZ,
114 .defer_initialization = false,
115 }),
116 },
117 /*
118 * DPU
119 */
120 {
121 .name = "ACLKDP",
122 .data = &((struct mod_rcar_clock_dev_config){
123 .type = MOD_RCAR_CLOCK_TYPE_MULTI_SOURCE,
124 .is_group_member = true,
125 .initial_rate = (CLOCK_RATE_SYSPLLCLK / 3),
126 .defer_initialization = false,
127 }),
128 },
129 {
130 .name = "DPU_M0",
131 .data = &((struct mod_rcar_clock_dev_config){
132 .type = MOD_RCAR_CLOCK_TYPE_MULTI_SOURCE,
133 .is_group_member = true,
134 .initial_rate = 260 * FWK_MHZ,
135 .defer_initialization = false,
136 }),
137 },
138 {}, /* Termination description. */
139 };
140
rcar_clock_get_element_table(fwk_id_t module_id)141 static const struct fwk_element *rcar_clock_get_element_table(
142 fwk_id_t module_id)
143 {
144 return rcar_clock_element_table;
145 }
146
147 struct fwk_module_config config_rcar_clock = {
148 .elements = FWK_MODULE_DYNAMIC_ELEMENTS(rcar_clock_get_element_table),
149 .data = &((struct mod_ext_clock_rate){
150 .ext_clk_rate = PLL_BASE_CLOCK,
151 }),
152 };
153