1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * SCP PIK registers 9 */ 10 11 #ifndef SCP_PIK_H 12 #define SCP_PIK_H 13 14 #include "scp_css_mmap.h" 15 16 #include <fwk_macros.h> 17 18 #include <stdint.h> 19 20 /*! 21 * \brief SCP PIK register definitions 22 */ 23 struct pik_scp_reg { 24 uint8_t RESERVED0[0x10 - 0x0]; 25 FWK_RW uint32_t RESET_SYNDROME; 26 uint8_t RESERVED1[0x20 - 0x14]; 27 FWK_RW uint32_t SURVIVAL_RESET_STATUS; 28 uint8_t RESERVED2[0x34 - 0x24]; 29 FWK_RW uint32_t ADDR_TRANS; 30 FWK_RW uint32_t DBG_ADDR_TRANS; 31 uint8_t RESERVED3[0x40 - 0x3C]; 32 FWK_RW uint32_t WS1_TIMER_MATCH; 33 FWK_RW uint32_t WS1_TIMER_EN; 34 uint8_t RESERVED4[0x200 - 0x48]; 35 FWK_R uint32_t SS_RESET_STATUS; 36 uint8_t RESERVED5[0x810 - 0x204]; 37 FWK_RW uint32_t CORECLK_CTRL; 38 FWK_RW uint32_t CORECLK_DIV1; 39 uint8_t RESERVED6[0x820 - 0x818]; 40 FWK_RW uint32_t ACLK_CTRL; 41 FWK_RW uint32_t ACLK_DIV1; 42 uint8_t RESERVED7[0x850 - 0x828]; 43 FWK_RW uint32_t REFCLK_CTRL; 44 uint8_t RESERVED8[0xA60 - 0x854]; 45 FWK_R uint32_t CONS_MMUTCU_INT_STATUS; 46 FWK_R uint32_t CONS_MMUTCU_INT_CLR; 47 FWK_R uint32_t CONS_MMUTBU_INT_STATUS0; 48 FWK_R uint32_t CONS_MMUTBU_INT_CLR0; 49 FWK_R uint32_t CONS_MMUTBU_INT_STATUS1; 50 FWK_R uint32_t CONS_MMUTBU_INT_CLR1; 51 FWK_RW uint32_t CONS_MMUTBU_INT_STATUS2; 52 FWK_RW uint32_t CONS_MMUTBU_INT_CLR2; 53 FWK_RW uint32_t CONS_MMUTBU_INT_STATUS3; 54 FWK_RW uint32_t CONS_MMUTBU_INT_CLR3; 55 FWK_RW uint32_t CONS_MMUTBU_INT_STATUS4; 56 FWK_RW uint32_t CONS_MMUTBU_INT_CLR4; 57 FWK_RW uint32_t CONS_MMUTBU_INT_STATUS5; 58 FWK_RW uint32_t CONS_MMUTBU_INT_CLR5; 59 uint8_t RESERVED9[0xB20 - 0xA98]; 60 FWK_R uint32_t CPU_PPU_INT_STATUS[4]; 61 uint8_t RESERVED10[0xB40 - 0xB30]; 62 FWK_R uint32_t CLUS_PPU_INT_STATUS[4]; 63 uint8_t RESERVED11[0xB80 - 0xB50]; 64 FWK_R uint32_t CPU_PLL_LOCK_STATUS[4]; 65 uint8_t RESERVED12[0xBC0 - 0xB90]; 66 FWK_R uint32_t CPU_PLL_UNLOCK_STATUS[4]; 67 uint8_t RESERVED13[0xC00 - 0xBD0]; 68 FWK_R uint32_t CONS_CLUS_SCF_INT_STATUSx[4]; 69 uint8_t RESERVED14[0xD00 - 0xC10]; 70 FWK_RW uint32_t TCMECC_ERRSTATUS; 71 FWK_RW uint32_t TCMECC_ERRCTRL; 72 FWK_RW uint32_t TCMECC_ERRCODE; 73 FWK_RW uint32_t TCMECC_ERRADDR; 74 uint8_t RESERVED15[0xFC0-0xD10]; 75 FWK_R uint32_t PWR_CTRL_CONFIG; 76 uint8_t RESERVED16[0xFD0 - 0xFC4]; 77 FWK_R uint32_t PID4; 78 FWK_R uint32_t PID5; 79 FWK_R uint32_t PID6; 80 FWK_R uint32_t PID7; 81 FWK_R uint32_t PID0; 82 FWK_R uint32_t PID1; 83 FWK_R uint32_t PID2; 84 FWK_R uint32_t PID3; 85 FWK_R uint32_t ID0; 86 FWK_R uint32_t ID1; 87 FWK_R uint32_t ID2; 88 FWK_R uint32_t ID3; 89 }; 90 91 #define PLL_STATUS_0_REFCLK UINT32_C(0x00000001) 92 #define PLL_STATUS_0_SYSPLLLOCK UINT32_C(0x00000002) 93 #define PLL_STATUS_0_DDRPLLLOCK UINT32_C(0x00000004) 94 #define PLL_STATUS_0_INTPLLLOCK UINT32_C(0x00000008) 95 96 #define PLL_STATUS_CPUPLLLOCK(CPU) ((uint32_t)(1 << (CPU % 32))) 97 98 /* Pointer to SCP PIK */ 99 #define SCP_PIK_PTR ((struct pik_scp_reg *)SCP_PIK_SCP_BASE) 100 101 #endif /* SCP_PIK_H */ 102