1 /*
2 * Arm SCP/MCP Software
3 * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "clock_soc.h"
9 #include "platform_def.h"
10 #include "scp_css_mmap.h"
11 #include "scp_software_mmap.h"
12
13 #include <mod_pcie_integ_ctrl.h>
14
15 #include <fwk_id.h>
16 #include <fwk_module.h>
17 #include <fwk_module_idx.h>
18
19 #define RD_N2_PCIE_INTEG_START_ADDR(index, base, size) (base + (size * index))
20 #define RD_N2_PCIE_INTEG_END_ADDR(index, base, size) \
21 (base + (size * (index + 1ULL)) - 1ULL)
22
23 #define IO_MACRO_ELEMENT_CONFIG( \
24 idx, pcie_integ_ctrl_reg_base, ecam_size, mmiol_size, mmioh_size) \
25 { \
26 .name = "IO Macro " #idx, \
27 .data = &((struct mod_pcie_integ_ctrl_config) { \
28 .reg_base = pcie_integ_ctrl_reg_base, \
29 .x16_ecam_mmio_mmap = { \
30 .valid = true, \
31 .allow_ns_access = true, \
32 .ecam1_start_addr = RD_N2_PCIE_INTEG_START_ADDR(idx, \
33 AP_PCIE_ECAM_BASE, ecam_size), \
34 .ecam1_end_addr = RD_N2_PCIE_INTEG_END_ADDR(idx, \
35 AP_PCIE_ECAM_BASE, ecam_size), \
36 .mmiol_start_addr = RD_N2_PCIE_INTEG_START_ADDR (idx, \
37 AP_PCIE_MMIOL_BASE, mmiol_size), \
38 .mmiol_end_addr = RD_N2_PCIE_INTEG_END_ADDR(idx, \
39 AP_PCIE_MMIOL_BASE, mmiol_size), \
40 .mmioh_start_addr = RD_N2_PCIE_INTEG_START_ADDR(idx, \
41 AP_PCIE_MMIOH_BASE, mmioh_size), \
42 .mmioh_end_addr = RD_N2_PCIE_INTEG_END_ADDR(idx, \
43 AP_PCIE_MMIOH_BASE, mmioh_size), \
44 }, \
45 .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, \
46 CLOCK_IDX_INTERCONNECT), \
47 }) \
48 }
49
50 #if (PLATFORM_VARIANT == 0 || PLATFORM_VARIANT == 3)
51 # define NON_PCIE_IO_MACRO_REG_BASE PCIE_INTEG_CTRL_REG_BASE(4)
52 #elif (PLATFORM_VARIANT == 1) || (PLATFORM_VARIANT == 2)
53 # define NON_PCIE_IO_MACRO_REG_BASE PCIE_INTEG_CTRL_REG_BASE(1)
54 #endif
55
56 static const struct fwk_element pcie_integ_ctrl_element_table[] = {
57 IO_MACRO_ELEMENT_CONFIG(
58 0,
59 PCIE_INTEG_CTRL_REG_BASE(0),
60 AP_PCIE_ECAM_SIZE_PER_RC,
61 AP_PCIE_MMIOL_SIZE_PER_RC,
62 AP_PCIE_MMIOH_SIZE_PER_RC),
63
64 #if (PLATFORM_VARIANT == 0 || PLATFORM_VARIANT == 3)
65 IO_MACRO_ELEMENT_CONFIG(
66 1,
67 PCIE_INTEG_CTRL_REG_BASE(1),
68 AP_PCIE_ECAM_SIZE_PER_RC,
69 AP_PCIE_MMIOL_SIZE_PER_RC,
70 AP_PCIE_MMIOH_SIZE_PER_RC),
71
72 IO_MACRO_ELEMENT_CONFIG(
73 2,
74 PCIE_INTEG_CTRL_REG_BASE(2),
75 AP_PCIE_ECAM_SIZE_PER_RC,
76 AP_PCIE_MMIOL_SIZE_PER_RC,
77 AP_PCIE_MMIOH_SIZE_PER_RC),
78
79 IO_MACRO_ELEMENT_CONFIG(
80 3,
81 PCIE_INTEG_CTRL_REG_BASE(3),
82 AP_PCIE_ECAM_SIZE_PER_RC,
83 AP_PCIE_MMIOL_SIZE_PER_RC,
84 AP_PCIE_MMIOH_SIZE_PER_RC),
85 #endif
86 {
87 .name = "Non-PCIe IO Macro",
88 .data = &((struct mod_pcie_integ_ctrl_config) {
89 .reg_base = NON_PCIE_IO_MACRO_REG_BASE,
90 /* PL011_UART0 (64 KB) and MEM0 (4 MB) */
91 .x4_0_ecam_mmio_mmap = {
92 .valid = true,
93 .allow_ns_access = true,
94 .mmioh_start_addr = 0x1080000000,
95 .mmioh_end_addr = 0x108040FFFF,
96 },
97 /* PL330_DMA0_NS (64 KB) and PL330_DMA0_S (64 KB) */
98 .x4_1_ecam_mmio_mmap = {
99 .valid = true,
100 .allow_ns_access = true,
101 .mmioh_start_addr = 0x1090000000,
102 .mmioh_end_addr = 0x109001FFFF,
103 },
104 /* PL011_UART1 (64 KB) */
105 .x8_ecam_mmio_mmap = {
106 .valid = true,
107 .allow_ns_access = true,
108 .mmioh_start_addr = 0x10A0000000,
109 .mmioh_end_addr = 0x10A000FFFF,
110 },
111 /* PL330_DMA0_NS (64 KB), PL330_DMA0_S(64 KB) and MEM1 (4 MB) */
112 .x16_ecam_mmio_mmap = {
113 .valid = true,
114 .allow_ns_access = true,
115 .mmioh_start_addr = 0x10B0000000,
116 .mmioh_end_addr = 0x10B041FFFF,
117 },
118 .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
119 CLOCK_IDX_INTERCONNECT),
120 }),
121 },
122
123 { 0 }
124 };
125
pcie_integ_get_element_table(fwk_id_t module_id)126 static const struct fwk_element *pcie_integ_get_element_table(
127 fwk_id_t module_id)
128 {
129 return pcie_integ_ctrl_element_table;
130 }
131
132 struct fwk_module_config config_pcie_integ_ctrl = {
133 .elements = FWK_MODULE_DYNAMIC_ELEMENTS(pcie_integ_get_element_table),
134 };
135