1 /*
2 * Arm SCP/MCP Software
3 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <mod_css_clock.h>
9 #include <mod_pik_clock.h>
10 #include <mod_system_pll.h>
11
12 #include <fwk_element.h>
13 #include <fwk_id.h>
14 #include <fwk_macros.h>
15 #include <fwk_module.h>
16 #include <fwk_module_idx.h>
17
18 #include <stdbool.h>
19 #include <stddef.h>
20
21 static const struct mod_css_clock_rate rate_table_cpu_group_big[] = {
22 {
23 /* Super Underdrive */
24 .rate = 1313 * FWK_MHZ,
25 .pll_rate = 1313 * FWK_MHZ,
26 .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
27 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
28 .clock_div = 1,
29 .clock_mod_numerator = 1,
30 .clock_mod_denominator = 1,
31 },
32 {
33 /* Underdrive */
34 .rate = 1531 * FWK_MHZ,
35 .pll_rate = 1531 * FWK_MHZ,
36 .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
37 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
38 .clock_div = 1,
39 .clock_mod_numerator = 1,
40 .clock_mod_denominator = 1,
41 },
42 {
43 /* Nominal */
44 .rate = 1750 * FWK_MHZ,
45 .pll_rate = 1750 * FWK_MHZ,
46 .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
47 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
48 .clock_div = 1,
49 .clock_mod_numerator = 1,
50 .clock_mod_denominator = 1,
51 },
52 {
53 /* Overdrive */
54 .rate = 2100 * FWK_MHZ,
55 .pll_rate = 2100 * FWK_MHZ,
56 .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
57 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
58 .clock_div = 1,
59 .clock_mod_numerator = 1,
60 .clock_mod_denominator = 1,
61 },
62 {
63 /* Super Overdrive */
64 .rate = 2450 * FWK_MHZ,
65 .pll_rate = 2450 * FWK_MHZ,
66 .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
67 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
68 .clock_div = 1,
69 .clock_mod_numerator = 1,
70 .clock_mod_denominator = 1,
71 },
72 };
73
74 static const struct mod_css_clock_rate rate_table_cpu_group_little[] = {
75 {
76 /* Super Underdrive */
77 .rate = 665 * FWK_MHZ,
78 .pll_rate = 665 * FWK_MHZ,
79 .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
80 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
81 .clock_div = 1,
82 .clock_mod_numerator = 1,
83 .clock_mod_denominator = 1,
84 },
85 {
86 /* Underdrive */
87 .rate = 998 * FWK_MHZ,
88 .pll_rate = 998 * FWK_MHZ,
89 .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
90 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
91 .clock_div = 1,
92 .clock_mod_numerator = 1,
93 .clock_mod_denominator = 1,
94 },
95 {
96 /* Nominal */
97 .rate = 1330 * FWK_MHZ,
98 .pll_rate = 1330 * FWK_MHZ,
99 .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
100 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
101 .clock_div = 1,
102 .clock_mod_numerator = 1,
103 .clock_mod_denominator = 1,
104 },
105 {
106 /* Overdrive */
107 .rate = 1463 * FWK_MHZ,
108 .pll_rate = 1463 * FWK_MHZ,
109 .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
110 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
111 .clock_div = 1,
112 .clock_mod_numerator = 1,
113 .clock_mod_denominator = 1,
114 },
115 {
116 /* Super Overdrive */
117 .rate = 1596 * FWK_MHZ,
118 .pll_rate = 1596 * FWK_MHZ,
119 .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
120 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
121 .clock_div = 1,
122 .clock_mod_numerator = 1,
123 .clock_mod_denominator = 1,
124 },
125 };
126
127 static const struct mod_css_clock_rate rate_table_gpu[] = {
128 {
129 .rate = 450 * FWK_MHZ,
130 .pll_rate = 450 * FWK_MHZ,
131 .clock_source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_PRIVPLLCLK,
132 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
133 .clock_div = 1,
134 },
135 {
136 .rate = 487500 * FWK_KHZ,
137 .pll_rate = 487500 * FWK_KHZ,
138 .clock_source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_PRIVPLLCLK,
139 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
140 .clock_div = 1,
141 },
142 {
143 .rate = 525 * FWK_MHZ,
144 .pll_rate = 525 * FWK_MHZ,
145 .clock_source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_PRIVPLLCLK,
146 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
147 .clock_div = 1,
148 },
149 {
150 .rate = 562500 * FWK_KHZ,
151 .pll_rate = 562500 * FWK_KHZ,
152 .clock_source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_PRIVPLLCLK,
153 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
154 .clock_div = 1,
155 },
156 {
157 /* Nominal */
158 .rate = 600 * FWK_MHZ,
159 .pll_rate = 600 * FWK_MHZ,
160 .clock_source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_PRIVPLLCLK,
161 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
162 .clock_div = 1,
163 },
164 };
165
166 static const struct mod_css_clock_rate rate_table_vpu[] = {
167 {
168 /* Nominal */
169 .rate = 600 * FWK_MHZ,
170 .pll_rate = 600 * FWK_MHZ,
171 .clock_source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_PRIVPLLCLK,
172 .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
173 .clock_div = 1,
174 },
175 };
176
177 static const fwk_id_t member_table_cpu_group_big[] = {
178 FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, 4),
179 FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, 5),
180 FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, 6),
181 FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, 7),
182 };
183
184 static const fwk_id_t member_table_cpu_group_little[] = {
185 FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, 0),
186 FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, 1),
187 FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, 2),
188 FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, 3),
189 };
190
191 static const fwk_id_t member_table_gpu[] = {
192 FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, 8),
193 };
194
195 static const fwk_id_t member_table_vpu[] = {
196 FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, 9),
197 };
198
199 static const fwk_id_t member_table_dpu[] = {
200 FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, 11),
201 };
202
203 static const struct fwk_element css_clock_element_table[] = {
204 {
205 .name = "CPU_GROUP_BIG",
206 .data = &((struct mod_css_clock_dev_config) {
207 .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
208 .rate_table = rate_table_cpu_group_big,
209 .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_big),
210 .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK,
211 .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, 1),
212 .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
213 MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
214 .member_table = member_table_cpu_group_big,
215 .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_big),
216 .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
217 MOD_PIK_CLOCK_API_TYPE_CSS),
218 .initial_rate = 1750 * FWK_MHZ,
219 .modulation_supported = true,
220 }),
221 },
222 {
223 .name = "CPU_GROUP_LITTLE",
224 .data = &((struct mod_css_clock_dev_config) {
225 .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
226 .rate_table = rate_table_cpu_group_little,
227 .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_little),
228 .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK,
229 .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, 0),
230 .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
231 MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
232 .member_table = member_table_cpu_group_little,
233 .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_little),
234 .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
235 MOD_PIK_CLOCK_API_TYPE_CSS),
236 .initial_rate = 1330 * FWK_MHZ,
237 .modulation_supported = true,
238 }),
239 },
240 {
241 .name = "GPU",
242 .data = &((struct mod_css_clock_dev_config) {
243 .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
244 .rate_table = rate_table_gpu,
245 .rate_count = FWK_ARRAY_SIZE(rate_table_gpu),
246 .clock_switching_source = MOD_PIK_CLOCK_GPUCLK_SOURCE_SYSREFCLK,
247 .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, 2),
248 .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
249 MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
250 .member_table = member_table_gpu,
251 .member_count = FWK_ARRAY_SIZE(member_table_gpu),
252 .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
253 MOD_PIK_CLOCK_API_TYPE_CSS),
254 .initial_rate = 600 * FWK_MHZ,
255 .modulation_supported = false,
256 }),
257 },
258 {
259 .name = "VPU",
260 .data = &((struct mod_css_clock_dev_config) {
261 .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
262 .rate_table = rate_table_vpu,
263 .rate_count = FWK_ARRAY_SIZE(rate_table_vpu),
264 .clock_switching_source = MOD_PIK_CLOCK_VPUCLK_SOURCE_SYSREFCLK,
265 .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, 4),
266 .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
267 MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
268 .member_table = member_table_vpu,
269 .member_count = FWK_ARRAY_SIZE(member_table_vpu),
270 .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
271 MOD_PIK_CLOCK_API_TYPE_CSS),
272 .initial_rate = 600 * FWK_MHZ,
273 .modulation_supported = false,
274 }),
275 },
276 {
277 .name = "DPU",
278 .data = &((struct mod_css_clock_dev_config) {
279 .clock_type = MOD_CSS_CLOCK_TYPE_NON_INDEXED,
280 .clock_default_source = MOD_PIK_CLOCK_DPUCLK_SOURCE_DISPLAYPLLCLK,
281 .clock_switching_source = MOD_PIK_CLOCK_DPUCLK_SOURCE_PIXELCLK,
282 .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, 3),
283 .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
284 MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
285 .member_table = member_table_dpu,
286 .member_count = FWK_ARRAY_SIZE(member_table_dpu),
287 .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
288 MOD_PIK_CLOCK_API_TYPE_CSS),
289 .initial_rate = 260 * FWK_MHZ,
290 .modulation_supported = false,
291 }),
292 },
293 { 0 }, /* Termination description. */
294 };
295
css_clock_get_element_table(fwk_id_t module_id)296 static const struct fwk_element *css_clock_get_element_table
297 (fwk_id_t module_id)
298 {
299 return css_clock_element_table;
300 }
301
302 struct fwk_module_config config_css_clock = {
303 .elements = FWK_MODULE_DYNAMIC_ELEMENTS(css_clock_get_element_table),
304 };
305