1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef SCP_MMAP_H
9 #define SCP_MMAP_H
10 
11 /* SCP ROM and RAM base addresses */
12 #define SCP_BOOT_ROM_BASE 0x00000000
13 #define SCP_RAM_BASE      0x10000000
14 
15 /* SCP ROM and RAM firmware size loaded on main memory */
16 #define SCP_BOOT_ROM_SIZE (512 * 1024)
17 #define SCP_RAM_SIZE      (512 * 1024)
18 
19 /* SCP trusted and non-trusted RAM base address */
20 #define SCP_TRUSTED_RAM_BASE    (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x04000000)
21 #define SCP_NONTRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x06000000)
22 
23 /* Secure Shared memory between AP and SCP */
24 #define SCP_AP_SHARED_SECURE_BASE (SCP_TRUSTED_RAM_BASE)
25 #define SCP_AP_SHARED_SECURE_SIZE (4 * FWK_KIB)
26 
27 /* Non-secure Shared memory between AP and SCP */
28 #define SCP_AP_SHARED_NONSECURE_BASE (SCP_NONTRUSTED_RAM_BASE)
29 #define SCP_AP_SHARED_NONSECURE_SIZE (4 * FWK_KIB)
30 
31 #define SCP_SOC_EXPANSION3_BASE                UINT32_C(0x40000000)
32 #define SCP_PERIPHERAL_BASE                    UINT32_C(0x44000000)
33 #define SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE UINT32_C(0x50000000)
34 #define SCP_SYSTEM_ACCESS_PORT0_BASE           UINT32_C(0x60000000)
35 #define SCP_SYSTEM_ACCESS_PORT1_BASE           UINT32_C(0xA0000000)
36 
37 #define SCP_CMN_BOOKER_BASE (SCP_SYSTEM_ACCESS_PORT0_BASE + 0x10000000)
38 #define SCP_UART_BOARD_BASE (SCP_SYSTEM_ACCESS_PORT0_BASE + 0x3FF70000)
39 #define SCP_PIK_SCP_BASE    (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE)
40 
41 #define SCP_REFCLK_CNTCONTROL_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x2A430000)
42 #define SCP_REFCLK_CNTCTL_BASE     (SCP_PERIPHERAL_BASE + 0x0000)
43 #define SCP_REFCLK_CNTBASE0_BASE   (SCP_PERIPHERAL_BASE + 0x1000)
44 
45 #define SCP_PIK_CLUSTER_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x60000)
46 #define SCP_PIK_SYSTEM_BASE  (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x40000)
47 #define SCP_PIK_DPU_BASE     (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0xE0000)
48 
49 #define SCP_UTILITY_BUS_BASE \
50     (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x1000000)
51 #define SCP_PPU_CLUSTER_BASE (SCP_UTILITY_BUS_BASE + 0x30000)
52 #define SCP_PPU_CORE_BASE(n) (SCP_UTILITY_BUS_BASE + 0x80000 + (n * 0x100000))
53 
54 #define SCP_PPU_SYS0_BASE (SCP_PIK_SYSTEM_BASE + 0x1000)
55 
56 #define SCP_MHU_AP_BASE (SCP_PERIPHERAL_BASE)
57 
58 #define SCP_MHU_SCP_AP_RCV_NS_CLUS0 (SCP_MHU_AP_BASE + 0x2000)
59 #define SCP_MHU_SCP_AP_SND_NS_CLUS0 (SCP_MHU_AP_BASE + 0x3000)
60 #define SCP_MHU_SCP_AP_RCV_S_CLUS0  (SCP_MHU_AP_BASE + 0x4000)
61 #define SCP_MHU_SCP_AP_SND_S_CLUS0  (SCP_MHU_AP_BASE + 0x5000)
62 
63 #define SCP_PLL_BASE         (SCP_SOC_EXPANSION3_BASE + 0x03000000)
64 #define SCP_PLL_SYSPLL       (SCP_PLL_BASE + 0x00000000)
65 #define SCP_PLL_DISPLAY      (SCP_PLL_BASE + 0x00000014)
66 #define SCP_PLL_PIX0         (SCP_PLL_BASE + 0x00000018)
67 #define SCP_PLL_PIX1         (SCP_PLL_BASE + 0x0000001C)
68 #define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020)
69 
70 #define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100)
71 #define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104)
72 #define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108)
73 
74 /* AP Context Area */
75 #define SCP_AP_CONTEXT_BASE \
76     (SCP_AP_SHARED_SECURE_BASE + SCP_AP_SHARED_SECURE_SIZE - \
77      SCP_AP_CONTEXT_SIZE)
78 #define SCP_AP_CONTEXT_SIZE (64)
79 
80 /* SDS Memory Region */
81 #define SCP_SDS_MEM_BASE (SCP_AP_SHARED_SECURE_BASE)
82 #define SCP_SDS_MEM_SIZE (3520)
83 
84 /* SCMI Secure Payload Areas */
85 #define SCP_SCMI_PAYLOAD_SIZE       (128)
86 #define SCP_SCMI_PAYLOAD_S_A2P_BASE (SCP_SDS_MEM_BASE + SCP_SDS_MEM_SIZE)
87 #define SCP_SCMI_PAYLOAD_S_P2A_BASE \
88     (SCP_SCMI_PAYLOAD_S_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE)
89 
90 /* SCMI Non-Secure Payload Areas */
91 
92 #define SCP_SCMI_PAYLOAD0_NS_A2P_BASE (SCP_AP_SHARED_NONSECURE_BASE)
93 #define SCP_SCMI_PAYLOAD0_NS_P2A_BASE \
94     (SCP_SCMI_PAYLOAD0_NS_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE)
95 #define SCP_SCMI_PAYLOAD1_NS_A2P_BASE \
96     (SCP_SCMI_PAYLOAD0_NS_P2A_BASE + SCP_SCMI_PAYLOAD_SIZE)
97 #define SCP_SCMI_PAYLOAD1_NS_P2A_BASE \
98     (SCP_SCMI_PAYLOAD1_NS_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE)
99 
100 #endif /* SCP_MMAP_H */
101