1 /*
2 * Arm SCP/MCP Software
3 * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "clock_soc.h"
9 #include "config_power_domain.h"
10 #include "tc1_core.h"
11
12 #include <mod_clock.h>
13 #include <mod_css_clock.h>
14 #include <mod_pik_clock.h>
15 #include <mod_power_domain.h>
16 #include <mod_system_pll.h>
17
18 #include <fwk_element.h>
19 #include <fwk_module.h>
20 #include <fwk_module_idx.h>
21
22 static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = {
23 [CLOCK_IDX_CPU_GROUP_CORTEX_A510] =
24 {
25 .name = "CPU_GROUP_CORTEX_A510",
26 .data = &((struct mod_clock_dev_config){
27 .driver_id = FWK_ID_ELEMENT_INIT(
28 FWK_MODULE_IDX_CSS_CLOCK,
29 CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A510),
30 .api_id = FWK_ID_API_INIT(
31 FWK_MODULE_IDX_CSS_CLOCK,
32 MOD_CSS_CLOCK_API_TYPE_CLOCK),
33 }),
34 },
35 [CLOCK_IDX_CPU_GROUP_CORTEX_A715] =
36 {
37 .name = "CPU_GROUP_CORTEX_A715",
38 .data = &((struct mod_clock_dev_config){
39 .driver_id = FWK_ID_ELEMENT_INIT(
40 FWK_MODULE_IDX_CSS_CLOCK,
41 CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A715),
42 .api_id = FWK_ID_API_INIT(
43 FWK_MODULE_IDX_CSS_CLOCK,
44 MOD_CSS_CLOCK_API_TYPE_CLOCK),
45 }),
46 },
47 [CLOCK_IDX_CPU_GROUP_CORTEX_X3] =
48 {
49 .name = "CPU_GROUP_CORTEX_X3",
50 .data = &((struct mod_clock_dev_config){
51 .driver_id = FWK_ID_ELEMENT_INIT(
52 FWK_MODULE_IDX_CSS_CLOCK,
53 CLOCK_CSS_IDX_CPU_GROUP_CORTEX_X3),
54 .api_id = FWK_ID_API_INIT(
55 FWK_MODULE_IDX_CSS_CLOCK,
56 MOD_CSS_CLOCK_API_TYPE_CLOCK),
57 }),
58 },
59 [CLOCK_IDX_DPU] =
60 {
61 .name = "DPU",
62 .data = &((struct mod_clock_dev_config){
63 .driver_id = FWK_ID_ELEMENT_INIT(
64 FWK_MODULE_IDX_CSS_CLOCK,
65 CLOCK_CSS_IDX_DPU),
66 .api_id = FWK_ID_API_INIT(
67 FWK_MODULE_IDX_CSS_CLOCK,
68 MOD_CSS_CLOCK_API_TYPE_CLOCK),
69 }),
70 },
71 [CLOCK_IDX_PIXEL_0] =
72 {
73 .name = "PIXEL_0",
74 .data = &((struct mod_clock_dev_config){
75 .driver_id = FWK_ID_ELEMENT_INIT(
76 FWK_MODULE_IDX_SYSTEM_PLL,
77 CLOCK_PLL_IDX_PIX0),
78 .api_id = FWK_ID_API_INIT(
79 FWK_MODULE_IDX_SYSTEM_PLL,
80 MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
81 }),
82 },
83 [CLOCK_IDX_PIXEL_1] =
84 {
85 .name = "PIXEL_1",
86 .data = &((struct mod_clock_dev_config){
87 .driver_id = FWK_ID_ELEMENT_INIT(
88 FWK_MODULE_IDX_SYSTEM_PLL,
89 CLOCK_PLL_IDX_PIX1),
90 .api_id = FWK_ID_API_INIT(
91 FWK_MODULE_IDX_SYSTEM_PLL,
92 MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
93 }),
94 },
95 { 0 }, /* Termination description. */
96 };
97
clock_get_dev_desc_table(fwk_id_t module_id)98 static const struct fwk_element *clock_get_dev_desc_table(fwk_id_t module_id)
99 {
100 unsigned int i;
101 struct mod_clock_dev_config *dev_config;
102
103 for (i = 0; i < CLOCK_IDX_COUNT; i++) {
104 dev_config =
105 (struct mod_clock_dev_config *)clock_dev_desc_table[i].data;
106 dev_config->pd_source_id = fwk_id_build_element_id(
107 fwk_module_id_power_domain,
108 tc1_core_get_core_count() + tc1_core_get_cluster_count() +
109 PD_STATIC_DEV_IDX_SYSTOP);
110 }
111
112 return clock_dev_desc_table;
113 }
114
115 const struct fwk_module_config config_clock = {
116 .elements = FWK_MODULE_DYNAMIC_ELEMENTS(clock_get_dev_desc_table),
117 .data = &((struct mod_clock_config){
118 .pd_transition_notification_id = FWK_ID_NOTIFICATION_INIT(
119 FWK_MODULE_IDX_POWER_DOMAIN,
120 MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION),
121 .pd_pre_transition_notification_id = FWK_ID_NOTIFICATION_INIT(
122 FWK_MODULE_IDX_POWER_DOMAIN,
123 MOD_PD_NOTIFICATION_IDX_POWER_STATE_PRE_TRANSITION),
124 }),
125
126 };
127