1 /*
2 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <limits.h>
10 #include <stdint.h>
11 #include <stdio.h>
12
13 #include <arch.h>
14 #include <arch_helpers.h>
15 #include "clk-stm32-core.h"
16 #include <common/debug.h>
17 #include <common/fdt_wrappers.h>
18 #include <drivers/clk.h>
19 #include <drivers/delay_timer.h>
20 #include <drivers/st/stm32mp13_rcc.h>
21 #include <drivers/st/stm32mp1_clk.h>
22 #include <drivers/st/stm32mp_clkfunc.h>
23 #include <dt-bindings/clock/stm32mp13-clksrc.h>
24 #include <lib/mmio.h>
25 #include <lib/spinlock.h>
26 #include <lib/utils_def.h>
27 #include <libfdt.h>
28 #include <plat/common/platform.h>
29
30 #include <platform_def.h>
31
32 struct stm32_osci_dt_cfg {
33 unsigned long freq;
34 bool bypass;
35 bool digbyp;
36 bool css;
37 uint32_t drive;
38 };
39
40 enum pll_mn {
41 PLL_CFG_M,
42 PLL_CFG_N,
43 PLL_DIV_MN_NB
44 };
45
46 enum pll_pqr {
47 PLL_CFG_P,
48 PLL_CFG_Q,
49 PLL_CFG_R,
50 PLL_DIV_PQR_NB
51 };
52
53 enum pll_csg {
54 PLL_CSG_MOD_PER,
55 PLL_CSG_INC_STEP,
56 PLL_CSG_SSCG_MODE,
57 PLL_CSG_NB
58 };
59
60 struct stm32_pll_vco {
61 uint32_t status;
62 uint32_t src;
63 uint32_t div_mn[PLL_DIV_MN_NB];
64 uint32_t frac;
65 bool csg_enabled;
66 uint32_t csg[PLL_CSG_NB];
67 };
68
69 struct stm32_pll_output {
70 uint32_t output[PLL_DIV_PQR_NB];
71 };
72
73 struct stm32_pll_dt_cfg {
74 struct stm32_pll_vco vco;
75 struct stm32_pll_output output;
76 };
77
78 struct stm32_clk_platdata {
79 uint32_t nosci;
80 struct stm32_osci_dt_cfg *osci;
81 uint32_t npll;
82 struct stm32_pll_dt_cfg *pll;
83 uint32_t nclksrc;
84 uint32_t *clksrc;
85 uint32_t nclkdiv;
86 uint32_t *clkdiv;
87 };
88
89 enum stm32_clock {
90 /* ROOT CLOCKS */
91 _CK_OFF,
92 _CK_HSI,
93 _CK_HSE,
94 _CK_CSI,
95 _CK_LSI,
96 _CK_LSE,
97 _I2SCKIN,
98 _CSI_DIV122,
99 _HSE_DIV,
100 _HSE_DIV2,
101 _CK_PLL1,
102 _CK_PLL2,
103 _CK_PLL3,
104 _CK_PLL4,
105 _PLL1P,
106 _PLL1P_DIV,
107 _PLL2P,
108 _PLL2Q,
109 _PLL2R,
110 _PLL3P,
111 _PLL3Q,
112 _PLL3R,
113 _PLL4P,
114 _PLL4Q,
115 _PLL4R,
116 _PCLK1,
117 _PCLK2,
118 _PCLK3,
119 _PCLK4,
120 _PCLK5,
121 _PCLK6,
122 _CKMPU,
123 _CKAXI,
124 _CKMLAHB,
125 _CKPER,
126 _CKTIMG1,
127 _CKTIMG2,
128 _CKTIMG3,
129 _USB_PHY_48,
130 _MCO1_K,
131 _MCO2_K,
132 _TRACECK,
133 /* BUS and KERNEL CLOCKS */
134 _DDRC1,
135 _DDRC1LP,
136 _DDRPHYC,
137 _DDRPHYCLP,
138 _DDRCAPB,
139 _DDRCAPBLP,
140 _AXIDCG,
141 _DDRPHYCAPB,
142 _DDRPHYCAPBLP,
143 _SYSCFG,
144 _DDRPERFM,
145 _IWDG2APB,
146 _USBPHY_K,
147 _USBO_K,
148 _RTCAPB,
149 _TZC,
150 _ETZPC,
151 _IWDG1APB,
152 _BSEC,
153 _STGENC,
154 _USART1_K,
155 _USART2_K,
156 _I2C3_K,
157 _I2C4_K,
158 _I2C5_K,
159 _TIM12,
160 _TIM15,
161 _RTCCK,
162 _GPIOA,
163 _GPIOB,
164 _GPIOC,
165 _GPIOD,
166 _GPIOE,
167 _GPIOF,
168 _GPIOG,
169 _GPIOH,
170 _GPIOI,
171 _PKA,
172 _SAES_K,
173 _CRYP1,
174 _HASH1,
175 _RNG1_K,
176 _BKPSRAM,
177 _SDMMC1_K,
178 _SDMMC2_K,
179 _DBGCK,
180 _USART3_K,
181 _UART4_K,
182 _UART5_K,
183 _UART7_K,
184 _UART8_K,
185 _USART6_K,
186 _MCE,
187 _FMC_K,
188 _QSPI_K,
189 #if defined(IMAGE_BL32)
190 _LTDC,
191 _DMA1,
192 _DMA2,
193 _MDMA,
194 _ETH1MAC,
195 _USBH,
196 _TIM2,
197 _TIM3,
198 _TIM4,
199 _TIM5,
200 _TIM6,
201 _TIM7,
202 _LPTIM1_K,
203 _SPI2_K,
204 _SPI3_K,
205 _SPDIF_K,
206 _TIM1,
207 _TIM8,
208 _SPI1_K,
209 _SAI1_K,
210 _SAI2_K,
211 _DFSDM,
212 _FDCAN_K,
213 _TIM13,
214 _TIM14,
215 _TIM16,
216 _TIM17,
217 _SPI4_K,
218 _SPI5_K,
219 _I2C1_K,
220 _I2C2_K,
221 _ADFSDM,
222 _LPTIM2_K,
223 _LPTIM3_K,
224 _LPTIM4_K,
225 _LPTIM5_K,
226 _VREF,
227 _DTS,
228 _PMBCTRL,
229 _HDP,
230 _STGENRO,
231 _DCMIPP_K,
232 _DMAMUX1,
233 _DMAMUX2,
234 _DMA3,
235 _ADC1_K,
236 _ADC2_K,
237 _TSC,
238 _AXIMC,
239 _ETH1CK,
240 _ETH1TX,
241 _ETH1RX,
242 _CRC1,
243 _ETH2CK,
244 _ETH2TX,
245 _ETH2RX,
246 _ETH2MAC,
247 #endif
248 CK_LAST
249 };
250
251 /* PARENT CONFIG */
252 static const uint16_t RTC_src[] = {
253 _CK_OFF, _CK_LSE, _CK_LSI, _CK_HSE
254 };
255
256 static const uint16_t MCO1_src[] = {
257 _CK_HSI, _CK_HSE, _CK_CSI, _CK_LSI, _CK_LSE
258 };
259
260 static const uint16_t MCO2_src[] = {
261 _CKMPU, _CKAXI, _CKMLAHB, _PLL4P, _CK_HSE, _CK_HSI
262 };
263
264 static const uint16_t PLL12_src[] = {
265 _CK_HSI, _CK_HSE
266 };
267
268 static const uint16_t PLL3_src[] = {
269 _CK_HSI, _CK_HSE, _CK_CSI
270 };
271
272 static const uint16_t PLL4_src[] = {
273 _CK_HSI, _CK_HSE, _CK_CSI, _I2SCKIN
274 };
275
276 static const uint16_t MPU_src[] = {
277 _CK_HSI, _CK_HSE, _PLL1P, _PLL1P_DIV
278 };
279
280 static const uint16_t AXI_src[] = {
281 _CK_HSI, _CK_HSE, _PLL2P
282 };
283
284 static const uint16_t MLAHBS_src[] = {
285 _CK_HSI, _CK_HSE, _CK_CSI, _PLL3P
286 };
287
288 static const uint16_t CKPER_src[] = {
289 _CK_HSI, _CK_CSI, _CK_HSE, _CK_OFF
290 };
291
292 static const uint16_t I2C12_src[] = {
293 _PCLK1, _PLL4R, _CK_HSI, _CK_CSI
294 };
295
296 static const uint16_t I2C3_src[] = {
297 _PCLK6, _PLL4R, _CK_HSI, _CK_CSI
298 };
299
300 static const uint16_t I2C4_src[] = {
301 _PCLK6, _PLL4R, _CK_HSI, _CK_CSI
302 };
303
304 static const uint16_t I2C5_src[] = {
305 _PCLK6, _PLL4R, _CK_HSI, _CK_CSI
306 };
307
308 static const uint16_t SPI1_src[] = {
309 _PLL4P, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R
310 };
311
312 static const uint16_t SPI23_src[] = {
313 _PLL4P, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R
314 };
315
316 static const uint16_t SPI4_src[] = {
317 _PCLK6, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE, _I2SCKIN
318 };
319
320 static const uint16_t SPI5_src[] = {
321 _PCLK6, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE
322 };
323
324 static const uint16_t UART1_src[] = {
325 _PCLK6, _PLL3Q, _CK_HSI, _CK_CSI, _PLL4Q, _CK_HSE
326 };
327
328 static const uint16_t UART2_src[] = {
329 _PCLK6, _PLL3Q, _CK_HSI, _CK_CSI, _PLL4Q, _CK_HSE
330 };
331
332 static const uint16_t UART35_src[] = {
333 _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE
334 };
335
336 static const uint16_t UART4_src[] = {
337 _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE
338 };
339
340 static const uint16_t UART6_src[] = {
341 _PCLK2, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE
342 };
343
344 static const uint16_t UART78_src[] = {
345 _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE
346 };
347
348 static const uint16_t LPTIM1_src[] = {
349 _PCLK1, _PLL4P, _PLL3Q, _CK_LSE, _CK_LSI, _CKPER
350 };
351
352 static const uint16_t LPTIM2_src[] = {
353 _PCLK3, _PLL4Q, _CKPER, _CK_LSE, _CK_LSI
354 };
355
356 static const uint16_t LPTIM3_src[] = {
357 _PCLK3, _PLL4Q, _CKPER, _CK_LSE, _CK_LSI
358 };
359
360 static const uint16_t LPTIM45_src[] = {
361 _PCLK3, _PLL4P, _PLL3Q, _CK_LSE, _CK_LSI, _CKPER
362 };
363
364 static const uint16_t SAI1_src[] = {
365 _PLL4Q, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R
366 };
367
368 static const uint16_t SAI2_src[] = {
369 _PLL4Q, _PLL3Q, _I2SCKIN, _CKPER, _NO_ID, _PLL3R
370 };
371
372 static const uint16_t FDCAN_src[] = {
373 _CK_HSE, _PLL3Q, _PLL4Q, _PLL4R
374 };
375
376 static const uint16_t SPDIF_src[] = {
377 _PLL4P, _PLL3Q, _CK_HSI
378 };
379
380 static const uint16_t ADC1_src[] = {
381 _PLL4R, _CKPER, _PLL3Q
382 };
383
384 static const uint16_t ADC2_src[] = {
385 _PLL4R, _CKPER, _PLL3Q
386 };
387
388 static const uint16_t SDMMC1_src[] = {
389 _CKAXI, _PLL3R, _PLL4P, _CK_HSI
390 };
391
392 static const uint16_t SDMMC2_src[] = {
393 _CKAXI, _PLL3R, _PLL4P, _CK_HSI
394 };
395
396 static const uint16_t ETH1_src[] = {
397 _PLL4P, _PLL3Q
398 };
399
400 static const uint16_t ETH2_src[] = {
401 _PLL4P, _PLL3Q
402 };
403
404 static const uint16_t USBPHY_src[] = {
405 _CK_HSE, _PLL4R, _HSE_DIV2
406 };
407
408 static const uint16_t USBO_src[] = {
409 _PLL4R, _USB_PHY_48
410 };
411
412 static const uint16_t QSPI_src[] = {
413 _CKAXI, _PLL3R, _PLL4P, _CKPER
414 };
415
416 static const uint16_t FMC_src[] = {
417 _CKAXI, _PLL3R, _PLL4P, _CKPER
418 };
419
420 /* Position 2 of RNG1 mux is reserved */
421 static const uint16_t RNG1_src[] = {
422 _CK_CSI, _PLL4R, _CK_OFF, _CK_LSI
423 };
424
425 static const uint16_t STGEN_src[] = {
426 _CK_HSI, _CK_HSE
427 };
428
429 static const uint16_t DCMIPP_src[] = {
430 _CKAXI, _PLL2Q, _PLL4P, _CKPER
431 };
432
433 static const uint16_t SAES_src[] = {
434 _CKAXI, _CKPER, _PLL4R, _CK_LSI
435 };
436
437 #define MUX_CFG(id, src, _offset, _shift, _witdh)[id] = {\
438 .id_parents = src,\
439 .num_parents = ARRAY_SIZE(src),\
440 .mux = &(struct mux_cfg) {\
441 .offset = (_offset),\
442 .shift = (_shift),\
443 .width = (_witdh),\
444 .bitrdy = MUX_NO_BIT_RDY,\
445 },\
446 }
447
448 #define MUX_RDY_CFG(id, src, _offset, _shift, _witdh)[id] = {\
449 .id_parents = src,\
450 .num_parents = ARRAY_SIZE(src),\
451 .mux = &(struct mux_cfg) {\
452 .offset = (_offset),\
453 .shift = (_shift),\
454 .width = (_witdh),\
455 .bitrdy = 31,\
456 },\
457 }
458
459 static const struct parent_cfg parent_mp13[] = {
460 MUX_CFG(MUX_ADC1, ADC1_src, RCC_ADC12CKSELR, 0, 2),
461 MUX_CFG(MUX_ADC2, ADC2_src, RCC_ADC12CKSELR, 2, 2),
462 MUX_RDY_CFG(MUX_AXI, AXI_src, RCC_ASSCKSELR, 0, 3),
463 MUX_CFG(MUX_CKPER, CKPER_src, RCC_CPERCKSELR, 0, 2),
464 MUX_CFG(MUX_DCMIPP, DCMIPP_src, RCC_DCMIPPCKSELR, 0, 2),
465 MUX_CFG(MUX_ETH1, ETH1_src, RCC_ETH12CKSELR, 0, 2),
466 MUX_CFG(MUX_ETH2, ETH2_src, RCC_ETH12CKSELR, 8, 2),
467 MUX_CFG(MUX_FDCAN, FDCAN_src, RCC_FDCANCKSELR, 0, 2),
468 MUX_CFG(MUX_FMC, FMC_src, RCC_FMCCKSELR, 0, 2),
469 MUX_CFG(MUX_I2C12, I2C12_src, RCC_I2C12CKSELR, 0, 3),
470 MUX_CFG(MUX_I2C3, I2C3_src, RCC_I2C345CKSELR, 0, 3),
471 MUX_CFG(MUX_I2C4, I2C4_src, RCC_I2C345CKSELR, 3, 3),
472 MUX_CFG(MUX_I2C5, I2C5_src, RCC_I2C345CKSELR, 6, 3),
473 MUX_CFG(MUX_LPTIM1, LPTIM1_src, RCC_LPTIM1CKSELR, 0, 3),
474 MUX_CFG(MUX_LPTIM2, LPTIM2_src, RCC_LPTIM23CKSELR, 0, 3),
475 MUX_CFG(MUX_LPTIM3, LPTIM3_src, RCC_LPTIM23CKSELR, 3, 3),
476 MUX_CFG(MUX_LPTIM45, LPTIM45_src, RCC_LPTIM45CKSELR, 0, 3),
477 MUX_CFG(MUX_MCO1, MCO1_src, RCC_MCO1CFGR, 0, 3),
478 MUX_CFG(MUX_MCO2, MCO2_src, RCC_MCO2CFGR, 0, 3),
479 MUX_RDY_CFG(MUX_MLAHB, MLAHBS_src, RCC_MSSCKSELR, 0, 2),
480 MUX_RDY_CFG(MUX_MPU, MPU_src, RCC_MPCKSELR, 0, 2),
481 MUX_RDY_CFG(MUX_PLL12, PLL12_src, RCC_RCK12SELR, 0, 2),
482 MUX_RDY_CFG(MUX_PLL3, PLL3_src, RCC_RCK3SELR, 0, 2),
483 MUX_RDY_CFG(MUX_PLL4, PLL4_src, RCC_RCK4SELR, 0, 2),
484 MUX_CFG(MUX_QSPI, QSPI_src, RCC_QSPICKSELR, 0, 2),
485 MUX_CFG(MUX_RNG1, RNG1_src, RCC_RNG1CKSELR, 0, 2),
486 MUX_CFG(MUX_RTC, RTC_src, RCC_BDCR, 16, 2),
487 MUX_CFG(MUX_SAES, SAES_src, RCC_SAESCKSELR, 0, 2),
488 MUX_CFG(MUX_SAI1, SAI1_src, RCC_SAI1CKSELR, 0, 3),
489 MUX_CFG(MUX_SAI2, SAI2_src, RCC_SAI2CKSELR, 0, 3),
490 MUX_CFG(MUX_SDMMC1, SDMMC1_src, RCC_SDMMC12CKSELR, 0, 3),
491 MUX_CFG(MUX_SDMMC2, SDMMC2_src, RCC_SDMMC12CKSELR, 3, 3),
492 MUX_CFG(MUX_SPDIF, SPDIF_src, RCC_SPDIFCKSELR, 0, 2),
493 MUX_CFG(MUX_SPI1, SPI1_src, RCC_SPI2S1CKSELR, 0, 3),
494 MUX_CFG(MUX_SPI23, SPI23_src, RCC_SPI2S23CKSELR, 0, 3),
495 MUX_CFG(MUX_SPI4, SPI4_src, RCC_SPI45CKSELR, 0, 3),
496 MUX_CFG(MUX_SPI5, SPI5_src, RCC_SPI45CKSELR, 3, 3),
497 MUX_CFG(MUX_STGEN, STGEN_src, RCC_STGENCKSELR, 0, 2),
498 MUX_CFG(MUX_UART1, UART1_src, RCC_UART12CKSELR, 0, 3),
499 MUX_CFG(MUX_UART2, UART2_src, RCC_UART12CKSELR, 3, 3),
500 MUX_CFG(MUX_UART35, UART35_src, RCC_UART35CKSELR, 0, 3),
501 MUX_CFG(MUX_UART4, UART4_src, RCC_UART4CKSELR, 0, 3),
502 MUX_CFG(MUX_UART6, UART6_src, RCC_UART6CKSELR, 0, 3),
503 MUX_CFG(MUX_UART78, UART78_src, RCC_UART78CKSELR, 0, 3),
504 MUX_CFG(MUX_USBO, USBO_src, RCC_USBCKSELR, 4, 1),
505 MUX_CFG(MUX_USBPHY, USBPHY_src, RCC_USBCKSELR, 0, 2),
506 };
507
508 /*
509 * GATE CONFIG
510 */
511
512 enum enum_gate_cfg {
513 GATE_ZERO, /* reserved for no gate */
514 GATE_LSE,
515 GATE_RTCCK,
516 GATE_LSI,
517 GATE_HSI,
518 GATE_CSI,
519 GATE_HSE,
520 GATE_LSI_RDY,
521 GATE_CSI_RDY,
522 GATE_LSE_RDY,
523 GATE_HSE_RDY,
524 GATE_HSI_RDY,
525 GATE_MCO1,
526 GATE_MCO2,
527 GATE_DBGCK,
528 GATE_TRACECK,
529 GATE_PLL1,
530 GATE_PLL1_DIVP,
531 GATE_PLL1_DIVQ,
532 GATE_PLL1_DIVR,
533 GATE_PLL2,
534 GATE_PLL2_DIVP,
535 GATE_PLL2_DIVQ,
536 GATE_PLL2_DIVR,
537 GATE_PLL3,
538 GATE_PLL3_DIVP,
539 GATE_PLL3_DIVQ,
540 GATE_PLL3_DIVR,
541 GATE_PLL4,
542 GATE_PLL4_DIVP,
543 GATE_PLL4_DIVQ,
544 GATE_PLL4_DIVR,
545 GATE_DDRC1,
546 GATE_DDRC1LP,
547 GATE_DDRPHYC,
548 GATE_DDRPHYCLP,
549 GATE_DDRCAPB,
550 GATE_DDRCAPBLP,
551 GATE_AXIDCG,
552 GATE_DDRPHYCAPB,
553 GATE_DDRPHYCAPBLP,
554 GATE_TIM2,
555 GATE_TIM3,
556 GATE_TIM4,
557 GATE_TIM5,
558 GATE_TIM6,
559 GATE_TIM7,
560 GATE_LPTIM1,
561 GATE_SPI2,
562 GATE_SPI3,
563 GATE_USART3,
564 GATE_UART4,
565 GATE_UART5,
566 GATE_UART7,
567 GATE_UART8,
568 GATE_I2C1,
569 GATE_I2C2,
570 GATE_SPDIF,
571 GATE_TIM1,
572 GATE_TIM8,
573 GATE_SPI1,
574 GATE_USART6,
575 GATE_SAI1,
576 GATE_SAI2,
577 GATE_DFSDM,
578 GATE_ADFSDM,
579 GATE_FDCAN,
580 GATE_LPTIM2,
581 GATE_LPTIM3,
582 GATE_LPTIM4,
583 GATE_LPTIM5,
584 GATE_VREF,
585 GATE_DTS,
586 GATE_PMBCTRL,
587 GATE_HDP,
588 GATE_SYSCFG,
589 GATE_DCMIPP,
590 GATE_DDRPERFM,
591 GATE_IWDG2APB,
592 GATE_USBPHY,
593 GATE_STGENRO,
594 GATE_LTDC,
595 GATE_RTCAPB,
596 GATE_TZC,
597 GATE_ETZPC,
598 GATE_IWDG1APB,
599 GATE_BSEC,
600 GATE_STGENC,
601 GATE_USART1,
602 GATE_USART2,
603 GATE_SPI4,
604 GATE_SPI5,
605 GATE_I2C3,
606 GATE_I2C4,
607 GATE_I2C5,
608 GATE_TIM12,
609 GATE_TIM13,
610 GATE_TIM14,
611 GATE_TIM15,
612 GATE_TIM16,
613 GATE_TIM17,
614 GATE_DMA1,
615 GATE_DMA2,
616 GATE_DMAMUX1,
617 GATE_DMA3,
618 GATE_DMAMUX2,
619 GATE_ADC1,
620 GATE_ADC2,
621 GATE_USBO,
622 GATE_TSC,
623 GATE_GPIOA,
624 GATE_GPIOB,
625 GATE_GPIOC,
626 GATE_GPIOD,
627 GATE_GPIOE,
628 GATE_GPIOF,
629 GATE_GPIOG,
630 GATE_GPIOH,
631 GATE_GPIOI,
632 GATE_PKA,
633 GATE_SAES,
634 GATE_CRYP1,
635 GATE_HASH1,
636 GATE_RNG1,
637 GATE_BKPSRAM,
638 GATE_AXIMC,
639 GATE_MCE,
640 GATE_ETH1CK,
641 GATE_ETH1TX,
642 GATE_ETH1RX,
643 GATE_ETH1MAC,
644 GATE_FMC,
645 GATE_QSPI,
646 GATE_SDMMC1,
647 GATE_SDMMC2,
648 GATE_CRC1,
649 GATE_USBH,
650 GATE_ETH2CK,
651 GATE_ETH2TX,
652 GATE_ETH2RX,
653 GATE_ETH2MAC,
654 GATE_MDMA,
655
656 LAST_GATE
657 };
658
659 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\
660 .offset = (_offset),\
661 .bit_idx = (_bit_idx),\
662 .set_clr = (_offset_clr),\
663 }
664
665 static const struct gate_cfg gates_mp13[LAST_GATE] = {
666 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0),
667 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0),
668 GATE_CFG(GATE_LSI, RCC_RDLSICR, 0, 0),
669 GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1),
670 GATE_CFG(GATE_CSI, RCC_OCENSETR, 4, 1),
671 GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1),
672 GATE_CFG(GATE_LSI_RDY, RCC_RDLSICR, 1, 0),
673 GATE_CFG(GATE_CSI_RDY, RCC_OCRDYR, 4, 0),
674 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0),
675 GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0),
676 GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0),
677 GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 12, 0),
678 GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 12, 0),
679 GATE_CFG(GATE_DBGCK, RCC_DBGCFGR, 8, 0),
680 GATE_CFG(GATE_TRACECK, RCC_DBGCFGR, 9, 0),
681 GATE_CFG(GATE_PLL1, RCC_PLL1CR, 0, 0),
682 GATE_CFG(GATE_PLL1_DIVP, RCC_PLL1CR, 4, 0),
683 GATE_CFG(GATE_PLL1_DIVQ, RCC_PLL1CR, 5, 0),
684 GATE_CFG(GATE_PLL1_DIVR, RCC_PLL1CR, 6, 0),
685 GATE_CFG(GATE_PLL2, RCC_PLL2CR, 0, 0),
686 GATE_CFG(GATE_PLL2_DIVP, RCC_PLL2CR, 4, 0),
687 GATE_CFG(GATE_PLL2_DIVQ, RCC_PLL2CR, 5, 0),
688 GATE_CFG(GATE_PLL2_DIVR, RCC_PLL2CR, 6, 0),
689 GATE_CFG(GATE_PLL3, RCC_PLL3CR, 0, 0),
690 GATE_CFG(GATE_PLL3_DIVP, RCC_PLL3CR, 4, 0),
691 GATE_CFG(GATE_PLL3_DIVQ, RCC_PLL3CR, 5, 0),
692 GATE_CFG(GATE_PLL3_DIVR, RCC_PLL3CR, 6, 0),
693 GATE_CFG(GATE_PLL4, RCC_PLL4CR, 0, 0),
694 GATE_CFG(GATE_PLL4_DIVP, RCC_PLL4CR, 4, 0),
695 GATE_CFG(GATE_PLL4_DIVQ, RCC_PLL4CR, 5, 0),
696 GATE_CFG(GATE_PLL4_DIVR, RCC_PLL4CR, 6, 0),
697 GATE_CFG(GATE_DDRC1, RCC_DDRITFCR, 0, 0),
698 GATE_CFG(GATE_DDRC1LP, RCC_DDRITFCR, 1, 0),
699 GATE_CFG(GATE_DDRPHYC, RCC_DDRITFCR, 4, 0),
700 GATE_CFG(GATE_DDRPHYCLP, RCC_DDRITFCR, 5, 0),
701 GATE_CFG(GATE_DDRCAPB, RCC_DDRITFCR, 6, 0),
702 GATE_CFG(GATE_DDRCAPBLP, RCC_DDRITFCR, 7, 0),
703 GATE_CFG(GATE_AXIDCG, RCC_DDRITFCR, 8, 0),
704 GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9, 0),
705 GATE_CFG(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10, 0),
706 GATE_CFG(GATE_TIM2, RCC_MP_APB1ENSETR, 0, 1),
707 GATE_CFG(GATE_TIM3, RCC_MP_APB1ENSETR, 1, 1),
708 GATE_CFG(GATE_TIM4, RCC_MP_APB1ENSETR, 2, 1),
709 GATE_CFG(GATE_TIM5, RCC_MP_APB1ENSETR, 3, 1),
710 GATE_CFG(GATE_TIM6, RCC_MP_APB1ENSETR, 4, 1),
711 GATE_CFG(GATE_TIM7, RCC_MP_APB1ENSETR, 5, 1),
712 GATE_CFG(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9, 1),
713 GATE_CFG(GATE_SPI2, RCC_MP_APB1ENSETR, 11, 1),
714 GATE_CFG(GATE_SPI3, RCC_MP_APB1ENSETR, 12, 1),
715 GATE_CFG(GATE_USART3, RCC_MP_APB1ENSETR, 15, 1),
716 GATE_CFG(GATE_UART4, RCC_MP_APB1ENSETR, 16, 1),
717 GATE_CFG(GATE_UART5, RCC_MP_APB1ENSETR, 17, 1),
718 GATE_CFG(GATE_UART7, RCC_MP_APB1ENSETR, 18, 1),
719 GATE_CFG(GATE_UART8, RCC_MP_APB1ENSETR, 19, 1),
720 GATE_CFG(GATE_I2C1, RCC_MP_APB1ENSETR, 21, 1),
721 GATE_CFG(GATE_I2C2, RCC_MP_APB1ENSETR, 22, 1),
722 GATE_CFG(GATE_SPDIF, RCC_MP_APB1ENSETR, 26, 1),
723 GATE_CFG(GATE_TIM1, RCC_MP_APB2ENSETR, 0, 1),
724 GATE_CFG(GATE_TIM8, RCC_MP_APB2ENSETR, 1, 1),
725 GATE_CFG(GATE_SPI1, RCC_MP_APB2ENSETR, 8, 1),
726 GATE_CFG(GATE_USART6, RCC_MP_APB2ENSETR, 13, 1),
727 GATE_CFG(GATE_SAI1, RCC_MP_APB2ENSETR, 16, 1),
728 GATE_CFG(GATE_SAI2, RCC_MP_APB2ENSETR, 17, 1),
729 GATE_CFG(GATE_DFSDM, RCC_MP_APB2ENSETR, 20, 1),
730 GATE_CFG(GATE_ADFSDM, RCC_MP_APB2ENSETR, 21, 1),
731 GATE_CFG(GATE_FDCAN, RCC_MP_APB2ENSETR, 24, 1),
732 GATE_CFG(GATE_LPTIM2, RCC_MP_APB3ENSETR, 0, 1),
733 GATE_CFG(GATE_LPTIM3, RCC_MP_APB3ENSETR, 1, 1),
734 GATE_CFG(GATE_LPTIM4, RCC_MP_APB3ENSETR, 2, 1),
735 GATE_CFG(GATE_LPTIM5, RCC_MP_APB3ENSETR, 3, 1),
736 GATE_CFG(GATE_VREF, RCC_MP_APB3ENSETR, 13, 1),
737 GATE_CFG(GATE_DTS, RCC_MP_APB3ENSETR, 16, 1),
738 GATE_CFG(GATE_PMBCTRL, RCC_MP_APB3ENSETR, 17, 1),
739 GATE_CFG(GATE_HDP, RCC_MP_APB3ENSETR, 20, 1),
740 GATE_CFG(GATE_SYSCFG, RCC_MP_S_APB3ENSETR, 0, 1),
741 GATE_CFG(GATE_DCMIPP, RCC_MP_APB4ENSETR, 1, 1),
742 GATE_CFG(GATE_DDRPERFM, RCC_MP_APB4ENSETR, 8, 1),
743 GATE_CFG(GATE_IWDG2APB, RCC_MP_APB4ENSETR, 15, 1),
744 GATE_CFG(GATE_USBPHY, RCC_MP_APB4ENSETR, 16, 1),
745 GATE_CFG(GATE_STGENRO, RCC_MP_APB4ENSETR, 20, 1),
746 GATE_CFG(GATE_LTDC, RCC_MP_S_APB4ENSETR, 0, 1),
747 GATE_CFG(GATE_RTCAPB, RCC_MP_APB5ENSETR, 8, 1),
748 GATE_CFG(GATE_TZC, RCC_MP_APB5ENSETR, 11, 1),
749 GATE_CFG(GATE_ETZPC, RCC_MP_APB5ENSETR, 13, 1),
750 GATE_CFG(GATE_IWDG1APB, RCC_MP_APB5ENSETR, 15, 1),
751 GATE_CFG(GATE_BSEC, RCC_MP_APB5ENSETR, 16, 1),
752 GATE_CFG(GATE_STGENC, RCC_MP_APB5ENSETR, 20, 1),
753 GATE_CFG(GATE_USART1, RCC_MP_APB6ENSETR, 0, 1),
754 GATE_CFG(GATE_USART2, RCC_MP_APB6ENSETR, 1, 1),
755 GATE_CFG(GATE_SPI4, RCC_MP_APB6ENSETR, 2, 1),
756 GATE_CFG(GATE_SPI5, RCC_MP_APB6ENSETR, 3, 1),
757 GATE_CFG(GATE_I2C3, RCC_MP_APB6ENSETR, 4, 1),
758 GATE_CFG(GATE_I2C4, RCC_MP_APB6ENSETR, 5, 1),
759 GATE_CFG(GATE_I2C5, RCC_MP_APB6ENSETR, 6, 1),
760 GATE_CFG(GATE_TIM12, RCC_MP_APB6ENSETR, 7, 1),
761 GATE_CFG(GATE_TIM13, RCC_MP_APB6ENSETR, 8, 1),
762 GATE_CFG(GATE_TIM14, RCC_MP_APB6ENSETR, 9, 1),
763 GATE_CFG(GATE_TIM15, RCC_MP_APB6ENSETR, 10, 1),
764 GATE_CFG(GATE_TIM16, RCC_MP_APB6ENSETR, 11, 1),
765 GATE_CFG(GATE_TIM17, RCC_MP_APB6ENSETR, 12, 1),
766 GATE_CFG(GATE_DMA1, RCC_MP_AHB2ENSETR, 0, 1),
767 GATE_CFG(GATE_DMA2, RCC_MP_AHB2ENSETR, 1, 1),
768 GATE_CFG(GATE_DMAMUX1, RCC_MP_AHB2ENSETR, 2, 1),
769 GATE_CFG(GATE_DMA3, RCC_MP_AHB2ENSETR, 3, 1),
770 GATE_CFG(GATE_DMAMUX2, RCC_MP_AHB2ENSETR, 4, 1),
771 GATE_CFG(GATE_ADC1, RCC_MP_AHB2ENSETR, 5, 1),
772 GATE_CFG(GATE_ADC2, RCC_MP_AHB2ENSETR, 6, 1),
773 GATE_CFG(GATE_USBO, RCC_MP_AHB2ENSETR, 8, 1),
774 GATE_CFG(GATE_TSC, RCC_MP_AHB4ENSETR, 15, 1),
775
776 GATE_CFG(GATE_GPIOA, RCC_MP_S_AHB4ENSETR, 0, 1),
777 GATE_CFG(GATE_GPIOB, RCC_MP_S_AHB4ENSETR, 1, 1),
778 GATE_CFG(GATE_GPIOC, RCC_MP_S_AHB4ENSETR, 2, 1),
779 GATE_CFG(GATE_GPIOD, RCC_MP_S_AHB4ENSETR, 3, 1),
780 GATE_CFG(GATE_GPIOE, RCC_MP_S_AHB4ENSETR, 4, 1),
781 GATE_CFG(GATE_GPIOF, RCC_MP_S_AHB4ENSETR, 5, 1),
782 GATE_CFG(GATE_GPIOG, RCC_MP_S_AHB4ENSETR, 6, 1),
783 GATE_CFG(GATE_GPIOH, RCC_MP_S_AHB4ENSETR, 7, 1),
784 GATE_CFG(GATE_GPIOI, RCC_MP_S_AHB4ENSETR, 8, 1),
785
786 GATE_CFG(GATE_PKA, RCC_MP_AHB5ENSETR, 2, 1),
787 GATE_CFG(GATE_SAES, RCC_MP_AHB5ENSETR, 3, 1),
788 GATE_CFG(GATE_CRYP1, RCC_MP_AHB5ENSETR, 4, 1),
789 GATE_CFG(GATE_HASH1, RCC_MP_AHB5ENSETR, 5, 1),
790 GATE_CFG(GATE_RNG1, RCC_MP_AHB5ENSETR, 6, 1),
791 GATE_CFG(GATE_BKPSRAM, RCC_MP_AHB5ENSETR, 8, 1),
792 GATE_CFG(GATE_AXIMC, RCC_MP_AHB5ENSETR, 16, 1),
793 GATE_CFG(GATE_MCE, RCC_MP_AHB6ENSETR, 1, 1),
794 GATE_CFG(GATE_ETH1CK, RCC_MP_AHB6ENSETR, 7, 1),
795 GATE_CFG(GATE_ETH1TX, RCC_MP_AHB6ENSETR, 8, 1),
796 GATE_CFG(GATE_ETH1RX, RCC_MP_AHB6ENSETR, 9, 1),
797 GATE_CFG(GATE_ETH1MAC, RCC_MP_AHB6ENSETR, 10, 1),
798 GATE_CFG(GATE_FMC, RCC_MP_AHB6ENSETR, 12, 1),
799 GATE_CFG(GATE_QSPI, RCC_MP_AHB6ENSETR, 14, 1),
800 GATE_CFG(GATE_SDMMC1, RCC_MP_AHB6ENSETR, 16, 1),
801 GATE_CFG(GATE_SDMMC2, RCC_MP_AHB6ENSETR, 17, 1),
802 GATE_CFG(GATE_CRC1, RCC_MP_AHB6ENSETR, 20, 1),
803 GATE_CFG(GATE_USBH, RCC_MP_AHB6ENSETR, 24, 1),
804 GATE_CFG(GATE_ETH2CK, RCC_MP_AHB6ENSETR, 27, 1),
805 GATE_CFG(GATE_ETH2TX, RCC_MP_AHB6ENSETR, 28, 1),
806 GATE_CFG(GATE_ETH2RX, RCC_MP_AHB6ENSETR, 29, 1),
807 GATE_CFG(GATE_ETH2MAC, RCC_MP_AHB6ENSETR, 30, 1),
808 GATE_CFG(GATE_MDMA, RCC_MP_S_AHB6ENSETR, 0, 1),
809 };
810
811 /*
812 * DIV CONFIG
813 */
814
815 static const struct clk_div_table axi_div_table[] = {
816 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
817 { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
818 { 0 },
819 };
820
821 static const struct clk_div_table mlahb_div_table[] = {
822 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
823 { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
824 { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
825 { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
826 { 0 },
827 };
828
829 static const struct clk_div_table apb_div_table[] = {
830 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
831 { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
832 { 0 },
833 };
834
835 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\
836 .offset = _offset,\
837 .shift = _shift,\
838 .width = _width,\
839 .flags = _flags,\
840 .table = _table,\
841 .bitrdy = _bitrdy,\
842 }
843
844 static const struct div_cfg dividers_mp13[] = {
845 DIV_CFG(DIV_PLL1DIVP, RCC_PLL1CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
846 DIV_CFG(DIV_PLL2DIVP, RCC_PLL2CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
847 DIV_CFG(DIV_PLL2DIVQ, RCC_PLL2CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY),
848 DIV_CFG(DIV_PLL2DIVR, RCC_PLL2CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY),
849 DIV_CFG(DIV_PLL3DIVP, RCC_PLL3CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
850 DIV_CFG(DIV_PLL3DIVQ, RCC_PLL3CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY),
851 DIV_CFG(DIV_PLL3DIVR, RCC_PLL3CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY),
852 DIV_CFG(DIV_PLL4DIVP, RCC_PLL4CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
853 DIV_CFG(DIV_PLL4DIVQ, RCC_PLL4CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY),
854 DIV_CFG(DIV_PLL4DIVR, RCC_PLL4CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY),
855 DIV_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 0, NULL, DIV_NO_BIT_RDY),
856 DIV_CFG(DIV_AXI, RCC_AXIDIVR, 0, 3, 0, axi_div_table, 31),
857 DIV_CFG(DIV_MLAHB, RCC_MLAHBDIVR, 0, 4, 0, mlahb_div_table, 31),
858 DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31),
859 DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31),
860 DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31),
861 DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31),
862 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31),
863 DIV_CFG(DIV_APB6, RCC_APB6DIVR, 0, 3, 0, apb_div_table, 31),
864 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_BIT_RDY),
865 DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL, DIV_NO_BIT_RDY),
866 DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL, DIV_NO_BIT_RDY),
867
868 DIV_CFG(DIV_HSI, RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL, DIV_NO_BIT_RDY),
869 DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, CLK_DIVIDER_POWER_OF_TWO, NULL, DIV_NO_BIT_RDY),
870
871 DIV_CFG(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL, DIV_NO_BIT_RDY),
872 DIV_CFG(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL, DIV_NO_BIT_RDY),
873 };
874
875 #define MAX_HSI_HZ 64000000
876 #define USB_PHY_48_MHZ 48000000
877
878 #define TIMEOUT_US_200MS U(200000)
879 #define TIMEOUT_US_1S U(1000000)
880
881 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS
882 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS
883 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS
884 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS
885 #define OSCRDY_TIMEOUT TIMEOUT_US_1S
886
887 enum stm32_osc {
888 OSC_HSI,
889 OSC_HSE,
890 OSC_CSI,
891 OSC_LSI,
892 OSC_LSE,
893 OSC_I2SCKIN,
894 NB_OSCILLATOR
895 };
896
897 enum stm32mp1_pll_id {
898 _PLL1,
899 _PLL2,
900 _PLL3,
901 _PLL4,
902 _PLL_NB
903 };
904
905 enum stm32mp1_plltype {
906 PLL_800,
907 PLL_1600,
908 PLL_2000,
909 PLL_TYPE_NB
910 };
911
912 #define RCC_OFFSET_PLLXCR 0
913 #define RCC_OFFSET_PLLXCFGR1 4
914 #define RCC_OFFSET_PLLXCFGR2 8
915 #define RCC_OFFSET_PLLXFRACR 12
916 #define RCC_OFFSET_PLLXCSGR 16
917
918 struct stm32_clk_pll {
919 enum stm32mp1_plltype plltype;
920 uint16_t clk_id;
921 uint16_t reg_pllxcr;
922 };
923
924 struct stm32mp1_pll {
925 uint8_t refclk_min;
926 uint8_t refclk_max;
927 };
928
929 /* Define characteristic of PLL according type */
930 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
931 [PLL_800] = {
932 .refclk_min = 4,
933 .refclk_max = 16,
934 },
935 [PLL_1600] = {
936 .refclk_min = 8,
937 .refclk_max = 16,
938 },
939 [PLL_2000] = {
940 .refclk_min = 8,
941 .refclk_max = 16,
942 },
943 };
944
945 #if STM32MP_USB_PROGRAMMER
946 static bool pll4_bootrom;
947 #endif
948
949 /* RCC clock device driver private */
950 static unsigned int refcounts_mp13[CK_LAST];
951
952 static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx);
953
954 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
clk_oscillator_check_bypass(struct stm32_clk_priv * priv,int idx,bool digbyp,bool bypass)955 static void clk_oscillator_check_bypass(struct stm32_clk_priv *priv, int idx,
956 bool digbyp, bool bypass)
957 {
958 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, idx);
959 struct stm32_clk_bypass *bypass_data = osc_data->bypass;
960 uintptr_t address;
961
962 if (bypass_data == NULL) {
963 return;
964 }
965
966 address = priv->base + bypass_data->offset;
967 if ((mmio_read_32(address) & RCC_OCENR_HSEBYP) &&
968 (!(digbyp || bypass))) {
969 panic();
970 }
971 }
972 #endif
973
stm32_enable_oscillator_hse(struct stm32_clk_priv * priv)974 static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv)
975 {
976 struct stm32_clk_platdata *pdata = priv->pdata;
977 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE];
978 bool digbyp = osci->digbyp;
979 bool bypass = osci->bypass;
980 bool css = osci->css;
981
982 if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) {
983 return;
984 }
985
986 clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass);
987
988 _clk_stm32_enable(priv, _CK_HSE);
989
990 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
991 clk_oscillator_check_bypass(priv, _CK_HSE, digbyp, bypass);
992 #endif
993
994 clk_oscillator_set_css(priv, _CK_HSE, css);
995 }
996
stm32_enable_oscillator_lse(struct stm32_clk_priv * priv)997 static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv)
998 {
999 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE);
1000 struct stm32_clk_platdata *pdata = priv->pdata;
1001 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE];
1002 bool digbyp = osci->digbyp;
1003 bool bypass = osci->bypass;
1004 uint8_t drive = osci->drive;
1005
1006 if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) {
1007 return;
1008 }
1009
1010 clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass);
1011
1012 clk_oscillator_set_drive(priv, _CK_LSE, drive);
1013
1014 _clk_stm32_gate_enable(priv, osc_data->gate_id);
1015 }
1016
stm32mp1_set_hsidiv(uint8_t hsidiv)1017 static int stm32mp1_set_hsidiv(uint8_t hsidiv)
1018 {
1019 uint64_t timeout;
1020 uintptr_t rcc_base = stm32mp_rcc_base();
1021 uintptr_t address = rcc_base + RCC_OCRDYR;
1022
1023 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR,
1024 RCC_HSICFGR_HSIDIV_MASK,
1025 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv);
1026
1027 timeout = timeout_init_us(HSIDIV_TIMEOUT);
1028 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) {
1029 if (timeout_elapsed(timeout)) {
1030 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n",
1031 address, mmio_read_32(address));
1032 return -ETIMEDOUT;
1033 }
1034 }
1035
1036 return 0;
1037 }
1038
stm32mp1_hsidiv(unsigned long hsifreq)1039 static int stm32mp1_hsidiv(unsigned long hsifreq)
1040 {
1041 uint8_t hsidiv;
1042 uint32_t hsidivfreq = MAX_HSI_HZ;
1043
1044 for (hsidiv = 0; hsidiv < 4U; hsidiv++) {
1045 if (hsidivfreq == hsifreq) {
1046 break;
1047 }
1048
1049 hsidivfreq /= 2U;
1050 }
1051
1052 if (hsidiv == 4U) {
1053 ERROR("Invalid clk-hsi frequency\n");
1054 return -EINVAL;
1055 }
1056
1057 if (hsidiv != 0U) {
1058 return stm32mp1_set_hsidiv(hsidiv);
1059 }
1060
1061 return 0;
1062 }
1063
stm32_clk_oscillators_lse_set_css(struct stm32_clk_priv * priv)1064 static int stm32_clk_oscillators_lse_set_css(struct stm32_clk_priv *priv)
1065 {
1066 struct stm32_clk_platdata *pdata = priv->pdata;
1067 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE];
1068
1069 clk_oscillator_set_css(priv, _CK_LSE, osci->css);
1070
1071 return 0;
1072 }
1073
stm32mp1_come_back_to_hsi(void)1074 static int stm32mp1_come_back_to_hsi(void)
1075 {
1076 int ret;
1077 struct stm32_clk_priv *priv = clk_stm32_get_priv();
1078
1079 /* Come back to HSI */
1080 ret = _clk_stm32_set_parent(priv, _CKMPU, _CK_HSI);
1081 if (ret != 0) {
1082 return ret;
1083 }
1084
1085 ret = _clk_stm32_set_parent(priv, _CKAXI, _CK_HSI);
1086 if (ret != 0) {
1087 return ret;
1088 }
1089
1090 ret = _clk_stm32_set_parent(priv, _CKMLAHB, _CK_HSI);
1091 if (ret != 0) {
1092 return ret;
1093 }
1094
1095 return 0;
1096 }
1097
stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv * priv,uint32_t data)1098 static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data)
1099 {
1100 unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT;
1101
1102 return clk_get_index(priv, binding_id);
1103 }
1104
stm32_clk_configure_clk(struct stm32_clk_priv * priv,uint32_t data)1105 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data)
1106 {
1107 int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT;
1108 int enable = (data & CLK_ON_MASK) >> CLK_ON_SHIFT;
1109 int clk_id;
1110 int ret;
1111
1112 clk_id = stm32_clk_configure_clk_get_binding_id(priv, data);
1113 if (clk_id < 0) {
1114 return clk_id;
1115 }
1116
1117 ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel);
1118 if (ret != 0) {
1119 return ret;
1120 }
1121
1122 if (enable) {
1123 clk_stm32_enable_call_ops(priv, clk_id);
1124 } else {
1125 clk_stm32_disable_call_ops(priv, clk_id);
1126 }
1127
1128 return 0;
1129 }
1130
stm32_clk_configure_mux(struct stm32_clk_priv * priv,uint32_t data)1131 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data)
1132 {
1133 int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT;
1134 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
1135
1136 return clk_mux_set_parent(priv, mux, sel);
1137 }
1138
stm32_clk_dividers_configure(struct stm32_clk_priv * priv)1139 static int stm32_clk_dividers_configure(struct stm32_clk_priv *priv)
1140 {
1141 struct stm32_clk_platdata *pdata = priv->pdata;
1142 uint32_t i;
1143
1144 for (i = 0; i < pdata->nclkdiv; i++) {
1145 int div_id, div_n;
1146 int val;
1147 int ret;
1148
1149 val = pdata->clkdiv[i] & CMD_DATA_MASK;
1150 div_id = (val & DIV_ID_MASK) >> DIV_ID_SHIFT;
1151 div_n = (val & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT;
1152
1153 ret = clk_stm32_set_div(priv, div_id, div_n);
1154 if (ret != 0) {
1155 return ret;
1156 }
1157 }
1158
1159 return 0;
1160 }
1161
stm32_clk_source_configure(struct stm32_clk_priv * priv)1162 static int stm32_clk_source_configure(struct stm32_clk_priv *priv)
1163 {
1164 struct stm32_clk_platdata *pdata = priv->pdata;
1165 bool ckper_disabled = false;
1166 int clk_id;
1167 int ret;
1168 uint32_t i;
1169
1170 for (i = 0; i < pdata->nclksrc; i++) {
1171 uint32_t val = pdata->clksrc[i];
1172 uint32_t cmd, cmd_data;
1173
1174 if (val == (uint32_t)CLK_CKPER_DISABLED) {
1175 ckper_disabled = true;
1176 continue;
1177 }
1178
1179 if (val == (uint32_t)CLK_RTC_DISABLED) {
1180 continue;
1181 }
1182
1183 cmd = (val & CMD_MASK) >> CMD_SHIFT;
1184 cmd_data = val & ~CMD_MASK;
1185
1186 switch (cmd) {
1187 case CMD_MUX:
1188 ret = stm32_clk_configure_mux(priv, cmd_data);
1189 break;
1190
1191 case CMD_CLK:
1192 clk_id = stm32_clk_configure_clk_get_binding_id(priv, cmd_data);
1193
1194 if (clk_id == _RTCCK) {
1195 if ((_clk_stm32_is_enabled(priv, _RTCCK) == true)) {
1196 continue;
1197 }
1198 }
1199
1200 ret = stm32_clk_configure_clk(priv, cmd_data);
1201 break;
1202 default:
1203 ret = -EINVAL;
1204 break;
1205 }
1206
1207 if (ret != 0) {
1208 return ret;
1209 }
1210 }
1211
1212 /*
1213 * CKPER is source for some peripheral clocks
1214 * (FMC-NAND / QPSI-NOR) and switching source is allowed
1215 * only if previous clock is still ON
1216 * => deactivate CKPER only after switching clock
1217 */
1218 if (ckper_disabled) {
1219 ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED & CMD_MASK);
1220 if (ret != 0) {
1221 return ret;
1222 }
1223 }
1224
1225 return 0;
1226 }
1227
stm32_clk_stgen_configure(struct stm32_clk_priv * priv,int id)1228 static int stm32_clk_stgen_configure(struct stm32_clk_priv *priv, int id)
1229 {
1230 unsigned long stgen_freq;
1231
1232 stgen_freq = _clk_stm32_get_rate(priv, id);
1233
1234 stm32mp_stgen_config(stgen_freq);
1235
1236 return 0;
1237 }
1238
1239 #define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\
1240 [(_idx)] = {\
1241 .clk_id = (_clk_id),\
1242 .plltype = (_type),\
1243 .reg_pllxcr = (_reg),\
1244 }
1245
clk_stm32_pll_compute_cfgr1(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll,struct stm32_pll_vco * vco,uint32_t * value)1246 static int clk_stm32_pll_compute_cfgr1(struct stm32_clk_priv *priv,
1247 const struct stm32_clk_pll *pll,
1248 struct stm32_pll_vco *vco,
1249 uint32_t *value)
1250 {
1251 uint32_t divm = vco->div_mn[PLL_CFG_M];
1252 uint32_t divn = vco->div_mn[PLL_CFG_N];
1253 unsigned long prate = 0UL;
1254 unsigned long refclk = 0UL;
1255
1256 prate = _clk_stm32_get_parent_rate(priv, pll->clk_id);
1257 refclk = prate / (divm + 1U);
1258
1259 if ((refclk < (stm32mp1_pll[pll->plltype].refclk_min * 1000000U)) ||
1260 (refclk > (stm32mp1_pll[pll->plltype].refclk_max * 1000000U))) {
1261 return -EINVAL;
1262 }
1263
1264 *value = 0;
1265
1266 if ((pll->plltype == PLL_800) && (refclk >= 8000000U)) {
1267 *value = 1U << RCC_PLLNCFGR1_IFRGE_SHIFT;
1268 }
1269
1270 *value |= (divn << RCC_PLLNCFGR1_DIVN_SHIFT) & RCC_PLLNCFGR1_DIVN_MASK;
1271 *value |= (divm << RCC_PLLNCFGR1_DIVM_SHIFT) & RCC_PLLNCFGR1_DIVM_MASK;
1272
1273 return 0;
1274 }
1275
clk_stm32_pll_compute_cfgr2(struct stm32_pll_output * out)1276 static uint32_t clk_stm32_pll_compute_cfgr2(struct stm32_pll_output *out)
1277 {
1278 uint32_t value = 0;
1279
1280 value |= (out->output[PLL_CFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & RCC_PLLNCFGR2_DIVP_MASK;
1281 value |= (out->output[PLL_CFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & RCC_PLLNCFGR2_DIVQ_MASK;
1282 value |= (out->output[PLL_CFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & RCC_PLLNCFGR2_DIVR_MASK;
1283
1284 return value;
1285 }
1286
clk_stm32_pll_config_vco(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll,struct stm32_pll_vco * vco)1287 static void clk_stm32_pll_config_vco(struct stm32_clk_priv *priv,
1288 const struct stm32_clk_pll *pll,
1289 struct stm32_pll_vco *vco)
1290 {
1291 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1292 uint32_t value = 0;
1293
1294 if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) {
1295 ERROR("Invalid Vref clock !\n");
1296 panic();
1297 }
1298
1299 /* Write N / M / IFREGE fields */
1300 mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR1, value);
1301
1302 /* Fractional configuration */
1303 mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, 0);
1304
1305 /* Frac must be enabled only once its configuration is loaded */
1306 mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, vco->frac << RCC_PLLNFRACR_FRACV_SHIFT);
1307 mmio_setbits_32(pll_base + RCC_OFFSET_PLLXFRACR, RCC_PLLNFRACR_FRACLE);
1308 }
1309
clk_stm32_pll_config_csg(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll,struct stm32_pll_vco * vco)1310 static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv,
1311 const struct stm32_clk_pll *pll,
1312 struct stm32_pll_vco *vco)
1313 {
1314 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1315 uint32_t mod_per = 0;
1316 uint32_t inc_step = 0;
1317 uint32_t sscg_mode = 0;
1318 uint32_t value = 0;
1319
1320 if (!vco->csg_enabled) {
1321 return;
1322 }
1323
1324 mod_per = vco->csg[PLL_CSG_MOD_PER];
1325 inc_step = vco->csg[PLL_CSG_INC_STEP];
1326 sscg_mode = vco->csg[PLL_CSG_SSCG_MODE];
1327
1328 value |= (mod_per << RCC_PLLNCSGR_MOD_PER_SHIFT) & RCC_PLLNCSGR_MOD_PER_MASK;
1329 value |= (inc_step << RCC_PLLNCSGR_INC_STEP_SHIFT) & RCC_PLLNCSGR_INC_STEP_MASK;
1330 value |= (sscg_mode << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & RCC_PLLNCSGR_SSCG_MODE_MASK;
1331
1332 mmio_write_32(pll_base + RCC_OFFSET_PLLXCSGR, value);
1333 mmio_setbits_32(pll_base + RCC_OFFSET_PLLXCR, RCC_PLLNCR_SSCG_CTRL);
1334 }
1335
clk_stm32_pll_config_out(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll,struct stm32_pll_output * out)1336 static void clk_stm32_pll_config_out(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll,
1337 struct stm32_pll_output *out)
1338 {
1339 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1340 uint32_t value = 0;
1341
1342 value = clk_stm32_pll_compute_cfgr2(out);
1343
1344 mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR2, value);
1345 }
1346
clk_stm32_pll_get_pdata(int pll_idx)1347 static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx)
1348 {
1349 struct stm32_clk_priv *priv = clk_stm32_get_priv();
1350 struct stm32_clk_platdata *pdata = priv->pdata;
1351
1352 return &pdata->pll[pll_idx];
1353 }
1354
_clk_stm32_pll_is_enabled(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1355 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1356 {
1357 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1358
1359 return ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLON) != 0U);
1360 }
1361
_clk_stm32_pll_set_on(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1362 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1363 {
1364 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1365
1366 /* Preserve RCC_PLLNCR_SSCG_CTRL value */
1367 mmio_clrsetbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN,
1368 RCC_PLLNCR_PLLON);
1369 }
1370
_clk_stm32_pll_set_off(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1371 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1372 {
1373 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1374
1375 /* Stop all output */
1376 mmio_clrbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1377
1378 /* Stop PLL */
1379 mmio_clrbits_32(pll_base, RCC_PLLNCR_PLLON);
1380 }
1381
_clk_stm32_pll_wait_ready_on(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1382 static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv,
1383 const struct stm32_clk_pll *pll)
1384 {
1385 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1386 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
1387
1388 /* Wait PLL lock */
1389 while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) == 0U) {
1390 if (timeout_elapsed(timeout)) {
1391 ERROR("%d clock start failed @ 0x%x: 0x%x\n",
1392 pll->clk_id, pll->reg_pllxcr, mmio_read_32(pll_base));
1393 return -EINVAL;
1394 }
1395 }
1396
1397 return 0;
1398 }
1399
_clk_stm32_pll_wait_ready_off(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1400 static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv,
1401 const struct stm32_clk_pll *pll)
1402 {
1403 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1404 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
1405
1406 /* Wait PLL lock */
1407 while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) != 0U) {
1408 if (timeout_elapsed(timeout)) {
1409 ERROR("%d clock stop failed @ 0x%x: 0x%x\n",
1410 pll->clk_id, pll->reg_pllxcr, mmio_read_32(pll_base));
1411 return -EINVAL;
1412 }
1413 }
1414
1415 return 0;
1416 }
1417
_clk_stm32_pll_enable(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1418 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1419 {
1420 if (_clk_stm32_pll_is_enabled(priv, pll)) {
1421 return 0;
1422 }
1423
1424 /* Preserve RCC_PLLNCR_SSCG_CTRL value */
1425 _clk_stm32_pll_set_on(priv, pll);
1426
1427 /* Wait PLL lock */
1428 return _clk_stm32_pll_wait_ready_on(priv, pll);
1429 }
1430
_clk_stm32_pll_disable(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1431 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1432 {
1433 if (!_clk_stm32_pll_is_enabled(priv, pll)) {
1434 return;
1435 }
1436
1437 /* Stop all outputs and the PLL */
1438 _clk_stm32_pll_set_off(priv, pll);
1439
1440 /* Wait PLL stopped */
1441 _clk_stm32_pll_wait_ready_off(priv, pll);
1442 }
1443
_clk_stm32_pll_init(struct stm32_clk_priv * priv,int pll_idx,struct stm32_pll_dt_cfg * pll_conf)1444 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx,
1445 struct stm32_pll_dt_cfg *pll_conf)
1446 {
1447 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_idx);
1448 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1449 int ret = 0;
1450
1451 /* Configure PLLs source */
1452 ret = stm32_clk_configure_mux(priv, pll_conf->vco.src);
1453 if (ret) {
1454 return ret;
1455 }
1456
1457 #if STM32MP_USB_PROGRAMMER
1458 if ((pll_idx == _PLL4) && pll4_bootrom) {
1459 clk_stm32_pll_config_out(priv, pll, &pll_conf->output);
1460
1461 mmio_setbits_32(pll_base,
1462 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1463
1464 return 0;
1465 }
1466 #endif
1467 /* Stop the PLL before */
1468 _clk_stm32_pll_disable(priv, pll);
1469
1470 clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco);
1471 clk_stm32_pll_config_out(priv, pll, &pll_conf->output);
1472 clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco);
1473
1474 ret = _clk_stm32_pll_enable(priv, pll);
1475 if (ret != 0) {
1476 return ret;
1477 }
1478
1479 mmio_setbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1480
1481 return 0;
1482 }
1483
clk_stm32_pll_init(struct stm32_clk_priv * priv,int pll_idx)1484 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx)
1485 {
1486 struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx);
1487
1488 if (pll_conf->vco.status) {
1489 return _clk_stm32_pll_init(priv, pll_idx, pll_conf);
1490 }
1491
1492 return 0;
1493 }
1494
stm32_clk_pll_configure(struct stm32_clk_priv * priv)1495 static int stm32_clk_pll_configure(struct stm32_clk_priv *priv)
1496 {
1497 int err = 0;
1498
1499 err = clk_stm32_pll_init(priv, _PLL1);
1500 if (err) {
1501 return err;
1502 }
1503
1504 err = clk_stm32_pll_init(priv, _PLL2);
1505 if (err) {
1506 return err;
1507 }
1508
1509 err = clk_stm32_pll_init(priv, _PLL3);
1510 if (err) {
1511 return err;
1512 }
1513
1514 err = clk_stm32_pll_init(priv, _PLL4);
1515 if (err) {
1516 return err;
1517 }
1518
1519 return 0;
1520 }
1521
stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv * priv)1522 static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv)
1523 {
1524 int ret = 0;
1525
1526 if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) {
1527 ret = clk_oscillator_wait_ready_on(priv, _CK_LSE);
1528 }
1529
1530 return ret;
1531 }
1532
stm32_clk_oscillators_enable(struct stm32_clk_priv * priv)1533 static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv)
1534 {
1535 stm32_enable_oscillator_hse(priv);
1536 stm32_enable_oscillator_lse(priv);
1537 _clk_stm32_enable(priv, _CK_LSI);
1538 _clk_stm32_enable(priv, _CK_CSI);
1539 }
1540
stm32_clk_hsidiv_configure(struct stm32_clk_priv * priv)1541 static int stm32_clk_hsidiv_configure(struct stm32_clk_priv *priv)
1542 {
1543 return stm32mp1_hsidiv(_clk_stm32_get_rate(priv, _CK_HSI));
1544 }
1545
1546 #if STM32MP_USB_PROGRAMMER
stm32mp1_clk_is_pll4_used_by_bootrom(struct stm32_clk_priv * priv,int usbphy_p)1547 static bool stm32mp1_clk_is_pll4_used_by_bootrom(struct stm32_clk_priv *priv, int usbphy_p)
1548 {
1549 /* Don't initialize PLL4, when used by BOOTROM */
1550 if ((stm32mp_get_boot_itf_selected() ==
1551 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) &&
1552 (usbphy_p == _PLL4R)) {
1553 return true;
1554 }
1555
1556 return false;
1557 }
1558
stm32mp1_clk_check_usb_conflict(struct stm32_clk_priv * priv,int usbphy_p,int usbo_p)1559 static int stm32mp1_clk_check_usb_conflict(struct stm32_clk_priv *priv, int usbphy_p, int usbo_p)
1560 {
1561 int _usbo_p;
1562 int _usbphy_p;
1563
1564 if (!pll4_bootrom) {
1565 return 0;
1566 }
1567
1568 _usbo_p = _clk_stm32_get_parent(priv, _USBO_K);
1569 _usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K);
1570
1571 if ((_usbo_p != usbo_p) || (_usbphy_p != usbphy_p)) {
1572 return -FDT_ERR_BADVALUE;
1573 }
1574
1575 return 0;
1576 }
1577 #endif
1578
1579 static struct clk_oscillator_data stm32mp13_osc_data[NB_OSCILLATOR] = {
1580 OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY,
1581 NULL, NULL, NULL),
1582
1583 OSCILLATOR(OSC_LSI, _CK_LSI, "clk-lsi", GATE_LSI, GATE_LSI_RDY,
1584 NULL, NULL, NULL),
1585
1586 OSCILLATOR(OSC_CSI, _CK_CSI, "clk-csi", GATE_CSI, GATE_CSI_RDY,
1587 NULL, NULL, NULL),
1588
1589 OSCILLATOR(OSC_LSE, _CK_LSE, "clk-lse", GATE_LSE, GATE_LSE_RDY,
1590 BYPASS(RCC_BDCR, 1, 3),
1591 CSS(RCC_BDCR, 8),
1592 DRIVE(RCC_BDCR, 4, 2, 2)),
1593
1594 OSCILLATOR(OSC_HSE, _CK_HSE, "clk-hse", GATE_HSE, GATE_HSE_RDY,
1595 BYPASS(RCC_OCENSETR, 10, 7),
1596 CSS(RCC_OCENSETR, 11),
1597 NULL),
1598
1599 OSCILLATOR(OSC_I2SCKIN, _I2SCKIN, "i2s_ckin", NO_GATE, NO_GATE,
1600 NULL, NULL, NULL),
1601 };
1602
clk_stm32_get_oscillator_name(enum stm32_osc id)1603 static const char *clk_stm32_get_oscillator_name(enum stm32_osc id)
1604 {
1605 if (id < NB_OSCILLATOR) {
1606 return stm32mp13_osc_data[id].name;
1607 }
1608
1609 return NULL;
1610 }
1611
1612 #define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\
1613 [(_idx)] = {\
1614 .clk_id = (_clk_id),\
1615 .plltype = (_type),\
1616 .reg_pllxcr = (_reg),\
1617 }
1618
1619 static const struct stm32_clk_pll stm32_mp13_clk_pll[_PLL_NB] = {
1620 CLK_PLL_CFG(_PLL1, _CK_PLL1, PLL_2000, RCC_PLL1CR),
1621 CLK_PLL_CFG(_PLL2, _CK_PLL2, PLL_1600, RCC_PLL2CR),
1622 CLK_PLL_CFG(_PLL3, _CK_PLL3, PLL_800, RCC_PLL3CR),
1623 CLK_PLL_CFG(_PLL4, _CK_PLL4, PLL_800, RCC_PLL4CR),
1624 };
1625
clk_st32_pll_data(unsigned int idx)1626 static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx)
1627 {
1628 return &stm32_mp13_clk_pll[idx];
1629 }
1630
1631 struct stm32_pll_cfg {
1632 int pll_id;
1633 };
1634
clk_stm32_pll_recalc_rate(struct stm32_clk_priv * priv,int id,unsigned long prate)1635 static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id,
1636 unsigned long prate)
1637 {
1638 const struct clk_stm32 *clk = _clk_get(priv, id);
1639 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
1640 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);
1641 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1642 uint32_t cfgr1, fracr, divm, divn;
1643 unsigned long fvco;
1644
1645 cfgr1 = mmio_read_32(pll_base + RCC_OFFSET_PLLXCFGR1);
1646 fracr = mmio_read_32(pll_base + RCC_OFFSET_PLLXFRACR);
1647
1648 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
1649 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
1650
1651 /*
1652 * With FRACV :
1653 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
1654 * Without FRACV
1655 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
1656 */
1657 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) {
1658 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >>
1659 RCC_PLLNFRACR_FRACV_SHIFT;
1660 unsigned long long numerator, denominator;
1661
1662 numerator = (((unsigned long long)divn + 1U) << 13) + fracv;
1663 numerator = prate * numerator;
1664 denominator = ((unsigned long long)divm + 1U) << 13;
1665 fvco = (unsigned long)(numerator / denominator);
1666 } else {
1667 fvco = (unsigned long)(prate * (divn + 1U) / (divm + 1U));
1668 }
1669
1670 return fvco;
1671 };
1672
clk_stm32_pll_is_enabled(struct stm32_clk_priv * priv,int id)1673 static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id)
1674 {
1675 const struct clk_stm32 *clk = _clk_get(priv, id);
1676 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
1677 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);
1678
1679 return _clk_stm32_pll_is_enabled(priv, pll);
1680 }
1681
clk_stm32_pll_enable(struct stm32_clk_priv * priv,int id)1682 static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id)
1683 {
1684 const struct clk_stm32 *clk = _clk_get(priv, id);
1685 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
1686 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);
1687
1688 return _clk_stm32_pll_enable(priv, pll);
1689 }
1690
clk_stm32_pll_disable(struct stm32_clk_priv * priv,int id)1691 static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id)
1692 {
1693 const struct clk_stm32 *clk = _clk_get(priv, id);
1694 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
1695 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);
1696
1697 _clk_stm32_pll_disable(priv, pll);
1698 }
1699
1700 static const struct stm32_clk_ops clk_stm32_pll_ops = {
1701 .recalc_rate = clk_stm32_pll_recalc_rate,
1702 .enable = clk_stm32_pll_enable,
1703 .disable = clk_stm32_pll_disable,
1704 .is_enabled = clk_stm32_pll_is_enabled,
1705 };
1706
1707 #define CLK_PLL(idx, _idx, _parent, _gate, _pll_id, _flags)[idx] = {\
1708 .binding = _idx,\
1709 .parent = _parent,\
1710 .flags = (_flags),\
1711 .clock_cfg = &(struct stm32_pll_cfg) {\
1712 .pll_id = _pll_id,\
1713 },\
1714 .ops = &clk_stm32_pll_ops,\
1715 }
1716
1717 struct clk_stm32_composite_cfg {
1718 int gate_id;
1719 int div_id;
1720 };
1721
clk_stm32_composite_recalc_rate(struct stm32_clk_priv * priv,int idx,unsigned long prate)1722 static unsigned long clk_stm32_composite_recalc_rate(struct stm32_clk_priv *priv,
1723 int idx, unsigned long prate)
1724 {
1725 const struct clk_stm32 *clk = _clk_get(priv, idx);
1726 struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg;
1727
1728 return _clk_stm32_divider_recalc(priv, composite_cfg->div_id, prate);
1729 };
1730
clk_stm32_composite_gate_is_enabled(struct stm32_clk_priv * priv,int idx)1731 static bool clk_stm32_composite_gate_is_enabled(struct stm32_clk_priv *priv, int idx)
1732 {
1733 const struct clk_stm32 *clk = _clk_get(priv, idx);
1734 struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg;
1735
1736 return _clk_stm32_gate_is_enabled(priv, composite_cfg->gate_id);
1737 }
1738
clk_stm32_composite_gate_enable(struct stm32_clk_priv * priv,int idx)1739 static int clk_stm32_composite_gate_enable(struct stm32_clk_priv *priv, int idx)
1740 {
1741 const struct clk_stm32 *clk = _clk_get(priv, idx);
1742 struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg;
1743
1744 return _clk_stm32_gate_enable(priv, composite_cfg->gate_id);
1745 }
1746
clk_stm32_composite_gate_disable(struct stm32_clk_priv * priv,int idx)1747 static void clk_stm32_composite_gate_disable(struct stm32_clk_priv *priv, int idx)
1748 {
1749 const struct clk_stm32 *clk = _clk_get(priv, idx);
1750 struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg;
1751
1752 _clk_stm32_gate_disable(priv, composite_cfg->gate_id);
1753 }
1754
1755 static const struct stm32_clk_ops clk_stm32_composite_ops = {
1756 .recalc_rate = clk_stm32_composite_recalc_rate,
1757 .is_enabled = clk_stm32_composite_gate_is_enabled,
1758 .enable = clk_stm32_composite_gate_enable,
1759 .disable = clk_stm32_composite_gate_disable,
1760 };
1761
1762 #define STM32_COMPOSITE(idx, _binding, _parent, _flags, _gate_id,\
1763 _div_id)[idx] = {\
1764 .binding = (_binding),\
1765 .parent = (_parent),\
1766 .flags = (_flags),\
1767 .clock_cfg = &(struct clk_stm32_composite_cfg) {\
1768 .gate_id = (_gate_id),\
1769 .div_id = (_div_id),\
1770 },\
1771 .ops = &clk_stm32_composite_ops,\
1772 }
1773
1774 static const struct clk_stm32 stm32mp13_clk[CK_LAST] = {
1775 /* ROOT CLOCKS */
1776 CLK_FIXED_RATE(_CK_OFF, _NO_ID, 0),
1777 CLK_OSC(_CK_HSE, CK_HSE, CLK_IS_ROOT, OSC_HSE),
1778 CLK_OSC(_CK_HSI, CK_HSI, CLK_IS_ROOT, OSC_HSI),
1779 CLK_OSC(_CK_CSI, CK_CSI, CLK_IS_ROOT, OSC_CSI),
1780 CLK_OSC(_CK_LSI, CK_LSI, CLK_IS_ROOT, OSC_LSI),
1781 CLK_OSC(_CK_LSE, CK_LSE, CLK_IS_ROOT, OSC_LSE),
1782
1783 CLK_OSC_FIXED(_I2SCKIN, _NO_ID, CLK_IS_ROOT, OSC_I2SCKIN),
1784
1785 CLK_FIXED_RATE(_USB_PHY_48, _NO_ID, USB_PHY_48_MHZ),
1786
1787 STM32_DIV(_HSE_DIV, _NO_ID, _CK_HSE, 0, DIV_RTC),
1788
1789 FIXED_FACTOR(_HSE_DIV2, CK_HSE_DIV2, _CK_HSE, 1, 2),
1790 FIXED_FACTOR(_CSI_DIV122, _NO_ID, _CK_CSI, 1, 122),
1791
1792 CLK_PLL(_CK_PLL1, PLL1, MUX(MUX_PLL12), GATE_PLL1, _PLL1, 0),
1793 CLK_PLL(_CK_PLL2, PLL2, MUX(MUX_PLL12), GATE_PLL2, _PLL2, 0),
1794 CLK_PLL(_CK_PLL3, PLL3, MUX(MUX_PLL3), GATE_PLL3, _PLL3, 0),
1795 CLK_PLL(_CK_PLL4, PLL4, MUX(MUX_PLL4), GATE_PLL4, _PLL4, 0),
1796
1797 STM32_COMPOSITE(_PLL1P, PLL1_P, _CK_PLL1, CLK_IS_CRITICAL, GATE_PLL1_DIVP, DIV_PLL1DIVP),
1798 STM32_DIV(_PLL1P_DIV, _NO_ID, _CK_PLL1, 0, DIV_MPU),
1799
1800 STM32_COMPOSITE(_PLL2P, PLL2_P, _CK_PLL2, CLK_IS_CRITICAL, GATE_PLL2_DIVP, DIV_PLL2DIVP),
1801 STM32_COMPOSITE(_PLL2Q, PLL2_Q, _CK_PLL2, 0, GATE_PLL2_DIVQ, DIV_PLL2DIVQ),
1802 STM32_COMPOSITE(_PLL2R, PLL2_R, _CK_PLL2, CLK_IS_CRITICAL, GATE_PLL2_DIVR, DIV_PLL2DIVR),
1803
1804 STM32_COMPOSITE(_PLL3P, PLL3_P, _CK_PLL3, 0, GATE_PLL3_DIVP, DIV_PLL3DIVP),
1805 STM32_COMPOSITE(_PLL3Q, PLL3_Q, _CK_PLL3, 0, GATE_PLL3_DIVQ, DIV_PLL3DIVQ),
1806 STM32_COMPOSITE(_PLL3R, PLL3_R, _CK_PLL3, 0, GATE_PLL3_DIVR, DIV_PLL3DIVR),
1807
1808 STM32_COMPOSITE(_PLL4P, PLL4_P, _CK_PLL4, 0, GATE_PLL4_DIVP, DIV_PLL4DIVP),
1809 STM32_COMPOSITE(_PLL4Q, PLL4_Q, _CK_PLL4, 0, GATE_PLL4_DIVQ, DIV_PLL4DIVQ),
1810 STM32_COMPOSITE(_PLL4R, PLL4_R, _CK_PLL4, 0, GATE_PLL4_DIVR, DIV_PLL4DIVR),
1811
1812 STM32_MUX(_CKMPU, CK_MPU, MUX_MPU, 0),
1813 STM32_DIV(_CKAXI, CK_AXI, MUX(MUX_AXI), 0, DIV_AXI),
1814 STM32_DIV(_CKMLAHB, CK_MLAHB, MUX(MUX_MLAHB), CLK_IS_CRITICAL, DIV_MLAHB),
1815 STM32_MUX(_CKPER, CK_PER, MUX(MUX_CKPER), 0),
1816
1817 STM32_DIV(_PCLK1, PCLK1, _CKMLAHB, 0, DIV_APB1),
1818 STM32_DIV(_PCLK2, PCLK2, _CKMLAHB, 0, DIV_APB2),
1819 STM32_DIV(_PCLK3, PCLK3, _CKMLAHB, 0, DIV_APB3),
1820 STM32_DIV(_PCLK4, PCLK4, _CKAXI, 0, DIV_APB4),
1821 STM32_DIV(_PCLK5, PCLK5, _CKAXI, 0, DIV_APB5),
1822 STM32_DIV(_PCLK6, PCLK6, _CKMLAHB, 0, DIV_APB6),
1823
1824 CK_TIMER(_CKTIMG1, CK_TIMG1, _PCLK1, 0, RCC_APB1DIVR, RCC_TIMG1PRER),
1825 CK_TIMER(_CKTIMG2, CK_TIMG2, _PCLK2, 0, RCC_APB2DIVR, RCC_TIMG2PRER),
1826 CK_TIMER(_CKTIMG3, CK_TIMG3, _PCLK6, 0, RCC_APB6DIVR, RCC_TIMG3PRER),
1827
1828 /* END ROOT CLOCKS */
1829
1830 STM32_GATE(_DDRC1, DDRC1, _CKAXI, CLK_IS_CRITICAL, GATE_DDRC1),
1831 STM32_GATE(_DDRC1LP, DDRC1LP, _CKAXI, CLK_IS_CRITICAL, GATE_DDRC1LP),
1832 STM32_GATE(_DDRPHYC, DDRPHYC, _PLL2R, CLK_IS_CRITICAL, GATE_DDRPHYC),
1833 STM32_GATE(_DDRPHYCLP, DDRPHYCLP, _PLL2R, CLK_IS_CRITICAL, GATE_DDRPHYCLP),
1834 STM32_GATE(_DDRCAPB, DDRCAPB, _PCLK4, CLK_IS_CRITICAL, GATE_DDRCAPB),
1835 STM32_GATE(_DDRCAPBLP, DDRCAPBLP, _PCLK4, CLK_IS_CRITICAL, GATE_DDRCAPBLP),
1836 STM32_GATE(_AXIDCG, AXIDCG, _CKAXI, CLK_IS_CRITICAL, GATE_AXIDCG),
1837 STM32_GATE(_DDRPHYCAPB, DDRPHYCAPB, _PCLK4, CLK_IS_CRITICAL, GATE_DDRPHYCAPB),
1838 STM32_GATE(_DDRPHYCAPBLP, DDRPHYCAPBLP, _PCLK4, CLK_IS_CRITICAL, GATE_DDRPHYCAPBLP),
1839
1840 STM32_GATE(_SYSCFG, SYSCFG, _PCLK3, 0, GATE_SYSCFG),
1841 STM32_GATE(_DDRPERFM, DDRPERFM, _PCLK4, 0, GATE_DDRPERFM),
1842 STM32_GATE(_IWDG2APB, IWDG2, _PCLK4, 0, GATE_IWDG2APB),
1843 STM32_GATE(_USBPHY_K, USBPHY_K, MUX(MUX_USBPHY), 0, GATE_USBPHY),
1844 STM32_GATE(_USBO_K, USBO_K, MUX(MUX_USBO), 0, GATE_USBO),
1845
1846 STM32_GATE(_RTCAPB, RTCAPB, _PCLK5, CLK_IS_CRITICAL, GATE_RTCAPB),
1847 STM32_GATE(_TZC, TZC, _PCLK5, CLK_IS_CRITICAL, GATE_TZC),
1848 STM32_GATE(_ETZPC, TZPC, _PCLK5, CLK_IS_CRITICAL, GATE_ETZPC),
1849 STM32_GATE(_IWDG1APB, IWDG1, _PCLK5, 0, GATE_IWDG1APB),
1850 STM32_GATE(_BSEC, BSEC, _PCLK5, CLK_IS_CRITICAL, GATE_BSEC),
1851 STM32_GATE(_STGENC, STGEN_K, MUX(MUX_STGEN), CLK_IS_CRITICAL, GATE_STGENC),
1852
1853 STM32_GATE(_USART1_K, USART1_K, MUX(MUX_UART1), 0, GATE_USART1),
1854 STM32_GATE(_USART2_K, USART2_K, MUX(MUX_UART2), 0, GATE_USART2),
1855 STM32_GATE(_I2C3_K, I2C3_K, MUX(MUX_I2C3), 0, GATE_I2C3),
1856 STM32_GATE(_I2C4_K, I2C4_K, MUX(MUX_I2C4), 0, GATE_I2C4),
1857 STM32_GATE(_I2C5_K, I2C5_K, MUX(MUX_I2C5), 0, GATE_I2C5),
1858 STM32_GATE(_TIM12, TIM12_K, _CKTIMG3, 0, GATE_TIM12),
1859 STM32_GATE(_TIM15, TIM15_K, _CKTIMG3, 0, GATE_TIM15),
1860
1861 STM32_GATE(_RTCCK, RTC, MUX(MUX_RTC), 0, GATE_RTCCK),
1862
1863 STM32_GATE(_GPIOA, GPIOA, _CKMLAHB, 0, GATE_GPIOA),
1864 STM32_GATE(_GPIOB, GPIOB, _CKMLAHB, 0, GATE_GPIOB),
1865 STM32_GATE(_GPIOC, GPIOC, _CKMLAHB, 0, GATE_GPIOC),
1866 STM32_GATE(_GPIOD, GPIOD, _CKMLAHB, 0, GATE_GPIOD),
1867 STM32_GATE(_GPIOE, GPIOE, _CKMLAHB, 0, GATE_GPIOE),
1868 STM32_GATE(_GPIOF, GPIOF, _CKMLAHB, 0, GATE_GPIOF),
1869 STM32_GATE(_GPIOG, GPIOG, _CKMLAHB, 0, GATE_GPIOG),
1870 STM32_GATE(_GPIOH, GPIOH, _CKMLAHB, 0, GATE_GPIOH),
1871 STM32_GATE(_GPIOI, GPIOI, _CKMLAHB, 0, GATE_GPIOI),
1872
1873 STM32_GATE(_PKA, PKA, _CKAXI, 0, GATE_PKA),
1874 STM32_GATE(_SAES_K, SAES_K, MUX(MUX_SAES), 0, GATE_SAES),
1875 STM32_GATE(_CRYP1, CRYP1, _PCLK5, 0, GATE_CRYP1),
1876 STM32_GATE(_HASH1, HASH1, _PCLK5, 0, GATE_HASH1),
1877
1878 STM32_GATE(_RNG1_K, RNG1_K, MUX(MUX_RNG1), 0, GATE_RNG1),
1879 STM32_GATE(_BKPSRAM, BKPSRAM, _PCLK5, CLK_IS_CRITICAL, GATE_BKPSRAM),
1880
1881 STM32_GATE(_SDMMC1_K, SDMMC1_K, MUX(MUX_SDMMC1), 0, GATE_SDMMC1),
1882 STM32_GATE(_SDMMC2_K, SDMMC2_K, MUX(MUX_SDMMC2), 0, GATE_SDMMC2),
1883 STM32_GATE(_DBGCK, CK_DBG, _CKAXI, 0, GATE_DBGCK),
1884
1885 /* TODO: CHECK CLOCK FOR BL2/BL32 AND IF ONLY FOR TEST OR NOT */
1886 STM32_GATE(_USART3_K, USART3_K, MUX(MUX_UART35), 0, GATE_USART3),
1887 STM32_GATE(_UART4_K, UART4_K, MUX(MUX_UART4), 0, GATE_UART4),
1888 STM32_GATE(_UART5_K, UART5_K, MUX(MUX_UART35), 0, GATE_UART5),
1889 STM32_GATE(_UART7_K, UART7_K, MUX(MUX_UART78), 0, GATE_UART7),
1890 STM32_GATE(_UART8_K, UART8_K, MUX(MUX_UART78), 0, GATE_UART8),
1891 STM32_GATE(_USART6_K, USART6_K, MUX(MUX_UART6), 0, GATE_USART6),
1892 STM32_GATE(_MCE, MCE, _CKAXI, CLK_IS_CRITICAL, GATE_MCE),
1893 STM32_GATE(_FMC_K, FMC_K, MUX(MUX_FMC), 0, GATE_FMC),
1894 STM32_GATE(_QSPI_K, QSPI_K, MUX(MUX_QSPI), 0, GATE_QSPI),
1895
1896 STM32_COMPOSITE(_MCO1_K, CK_MCO1, MUX(MUX_MCO1), 0, GATE_MCO1, DIV_MCO1),
1897 STM32_COMPOSITE(_MCO2_K, CK_MCO2, MUX(MUX_MCO2), 0, GATE_MCO2, DIV_MCO2),
1898 STM32_COMPOSITE(_TRACECK, CK_TRACE, _CKAXI, 0, GATE_TRACECK, DIV_TRACE),
1899
1900 #if defined(IMAGE_BL32)
1901 STM32_GATE(_TIM2, TIM2_K, _CKTIMG1, 0, GATE_TIM2),
1902 STM32_GATE(_TIM3, TIM3_K, _CKTIMG1, 0, GATE_TIM3),
1903 STM32_GATE(_TIM4, TIM4_K, _CKTIMG1, 0, GATE_TIM4),
1904 STM32_GATE(_TIM5, TIM5_K, _CKTIMG1, 0, GATE_TIM5),
1905 STM32_GATE(_TIM6, TIM6_K, _CKTIMG1, 0, GATE_TIM6),
1906 STM32_GATE(_TIM7, TIM7_K, _CKTIMG1, 0, GATE_TIM7),
1907 STM32_GATE(_TIM13, TIM13_K, _CKTIMG3, 0, GATE_TIM13),
1908 STM32_GATE(_TIM14, TIM14_K, _CKTIMG3, 0, GATE_TIM14),
1909 STM32_GATE(_LPTIM1_K, LPTIM1_K, MUX(MUX_LPTIM1), 0, GATE_LPTIM1),
1910 STM32_GATE(_SPI2_K, SPI2_K, MUX(MUX_SPI23), 0, GATE_SPI2),
1911 STM32_GATE(_SPI3_K, SPI3_K, MUX(MUX_SPI23), 0, GATE_SPI3),
1912 STM32_GATE(_SPDIF_K, SPDIF_K, MUX(MUX_SPDIF), 0, GATE_SPDIF),
1913 STM32_GATE(_TIM1, TIM1_K, _CKTIMG2, 0, GATE_TIM1),
1914 STM32_GATE(_TIM8, TIM8_K, _CKTIMG2, 0, GATE_TIM8),
1915 STM32_GATE(_TIM16, TIM16_K, _CKTIMG3, 0, GATE_TIM16),
1916 STM32_GATE(_TIM17, TIM17_K, _CKTIMG3, 0, GATE_TIM17),
1917 STM32_GATE(_SPI1_K, SPI1_K, MUX(MUX_SPI1), 0, GATE_SPI1),
1918 STM32_GATE(_SPI4_K, SPI4_K, MUX(MUX_SPI4), 0, GATE_SPI4),
1919 STM32_GATE(_SPI5_K, SPI5_K, MUX(MUX_SPI5), 0, GATE_SPI5),
1920 STM32_GATE(_SAI1_K, SAI1_K, MUX(MUX_SAI1), 0, GATE_SAI1),
1921 STM32_GATE(_SAI2_K, SAI2_K, MUX(MUX_SAI2), 0, GATE_SAI2),
1922 STM32_GATE(_DFSDM, DFSDM_K, MUX(MUX_SAI1), 0, GATE_DFSDM),
1923 STM32_GATE(_FDCAN_K, FDCAN_K, MUX(MUX_FDCAN), 0, GATE_FDCAN),
1924 STM32_GATE(_USBH, USBH, _CKAXI, 0, GATE_USBH),
1925 STM32_GATE(_I2C1_K, I2C1_K, MUX(MUX_I2C12), 0, GATE_I2C1),
1926 STM32_GATE(_I2C2_K, I2C2_K, MUX(MUX_I2C12), 0, GATE_I2C2),
1927 STM32_GATE(_ADFSDM, ADFSDM_K, MUX(MUX_SAI1), 0, GATE_ADFSDM),
1928 STM32_GATE(_LPTIM2_K, LPTIM2_K, MUX(MUX_LPTIM2), 0, GATE_LPTIM2),
1929 STM32_GATE(_LPTIM3_K, LPTIM3_K, MUX(MUX_LPTIM3), 0, GATE_LPTIM3),
1930 STM32_GATE(_LPTIM4_K, LPTIM4_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM4),
1931 STM32_GATE(_LPTIM5_K, LPTIM5_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM5),
1932 STM32_GATE(_VREF, VREF, _PCLK3, 0, GATE_VREF),
1933 STM32_GATE(_DTS, TMPSENS, _PCLK3, 0, GATE_DTS),
1934 STM32_GATE(_PMBCTRL, PMBCTRL, _PCLK3, 0, GATE_HDP),
1935 STM32_GATE(_HDP, HDP, _PCLK3, 0, GATE_PMBCTRL),
1936 STM32_GATE(_STGENRO, STGENRO, _PCLK4, 0, GATE_DCMIPP),
1937 STM32_GATE(_DCMIPP_K, DCMIPP_K, MUX(MUX_DCMIPP), 0, GATE_DCMIPP),
1938 STM32_GATE(_DMAMUX1, DMAMUX1, _CKAXI, 0, GATE_DMAMUX1),
1939 STM32_GATE(_DMAMUX2, DMAMUX2, _CKAXI, 0, GATE_DMAMUX2),
1940 STM32_GATE(_DMA3, DMA3, _CKAXI, 0, GATE_DMAMUX2),
1941 STM32_GATE(_ADC1_K, ADC1_K, MUX(MUX_ADC1), 0, GATE_ADC1),
1942 STM32_GATE(_ADC2_K, ADC2_K, MUX(MUX_ADC2), 0, GATE_ADC2),
1943 STM32_GATE(_TSC, TSC, _CKAXI, 0, GATE_TSC),
1944 STM32_GATE(_AXIMC, AXIMC, _CKAXI, 0, GATE_AXIMC),
1945 STM32_GATE(_CRC1, CRC1, _CKAXI, 0, GATE_ETH1TX),
1946 STM32_GATE(_ETH1CK, ETH1CK_K, MUX(MUX_ETH1), 0, GATE_ETH1CK),
1947 STM32_GATE(_ETH1TX, ETH1TX, _CKAXI, 0, GATE_ETH1TX),
1948 STM32_GATE(_ETH1RX, ETH1RX, _CKAXI, 0, GATE_ETH1RX),
1949 STM32_GATE(_ETH2CK, ETH2CK_K, MUX(MUX_ETH2), 0, GATE_ETH2CK),
1950 STM32_GATE(_ETH2TX, ETH2TX, _CKAXI, 0, GATE_ETH2TX),
1951 STM32_GATE(_ETH2RX, ETH2RX, _CKAXI, 0, GATE_ETH2RX),
1952 STM32_GATE(_ETH2MAC, ETH2MAC, _CKAXI, 0, GATE_ETH2MAC),
1953 #endif
1954 };
1955
1956 static struct stm32_pll_dt_cfg mp13_pll[_PLL_NB];
1957
1958 static struct stm32_osci_dt_cfg mp13_osci[NB_OSCILLATOR];
1959
1960 static uint32_t mp13_clksrc[MUX_MAX];
1961
1962 static uint32_t mp13_clkdiv[DIV_MAX];
1963
1964 static struct stm32_clk_platdata stm32mp13_clock_pdata = {
1965 .osci = mp13_osci,
1966 .nosci = NB_OSCILLATOR,
1967 .pll = mp13_pll,
1968 .npll = _PLL_NB,
1969 .clksrc = mp13_clksrc,
1970 .nclksrc = MUX_MAX,
1971 .clkdiv = mp13_clkdiv,
1972 .nclkdiv = DIV_MAX,
1973 };
1974
1975 static struct stm32_clk_priv stm32mp13_clock_data = {
1976 .base = RCC_BASE,
1977 .num = ARRAY_SIZE(stm32mp13_clk),
1978 .clks = stm32mp13_clk,
1979 .parents = parent_mp13,
1980 .nb_parents = ARRAY_SIZE(parent_mp13),
1981 .gates = gates_mp13,
1982 .nb_gates = ARRAY_SIZE(gates_mp13),
1983 .div = dividers_mp13,
1984 .nb_div = ARRAY_SIZE(dividers_mp13),
1985 .osci_data = stm32mp13_osc_data,
1986 .nb_osci_data = ARRAY_SIZE(stm32mp13_osc_data),
1987 .gate_refcounts = refcounts_mp13,
1988 .pdata = &stm32mp13_clock_pdata,
1989 };
1990
stm32mp1_init_clock_tree(void)1991 static int stm32mp1_init_clock_tree(void)
1992 {
1993 struct stm32_clk_priv *priv = clk_stm32_get_priv();
1994 int ret;
1995
1996 #if STM32MP_USB_PROGRAMMER
1997 int usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K);
1998 int usbo_p = _clk_stm32_get_parent(priv, _USBO_K);
1999
2000 /* Don't initialize PLL4, when used by BOOTROM */
2001 pll4_bootrom = stm32mp1_clk_is_pll4_used_by_bootrom(priv, usbphy_p);
2002 #endif
2003
2004 /*
2005 * Switch ON oscillators found in device-tree.
2006 * Note: HSI already ON after BootROM stage.
2007 */
2008 stm32_clk_oscillators_enable(priv);
2009
2010 /* Come back to HSI */
2011 ret = stm32mp1_come_back_to_hsi();
2012 if (ret != 0) {
2013 return ret;
2014 }
2015
2016 ret = stm32_clk_hsidiv_configure(priv);
2017 if (ret != 0) {
2018 return ret;
2019 }
2020
2021 ret = stm32_clk_stgen_configure(priv, _STGENC);
2022 if (ret != 0) {
2023 panic();
2024 }
2025
2026 ret = stm32_clk_dividers_configure(priv);
2027 if (ret != 0) {
2028 panic();
2029 }
2030
2031 ret = stm32_clk_pll_configure(priv);
2032 if (ret != 0) {
2033 panic();
2034 }
2035
2036 /* Wait LSE ready before to use it */
2037 ret = stm32_clk_oscillators_wait_lse_ready(priv);
2038 if (ret != 0) {
2039 panic();
2040 }
2041
2042 /* Configure with expected clock source */
2043 ret = stm32_clk_source_configure(priv);
2044 if (ret != 0) {
2045 panic();
2046 }
2047
2048 /* Configure LSE css after RTC source configuration */
2049 ret = stm32_clk_oscillators_lse_set_css(priv);
2050 if (ret != 0) {
2051 panic();
2052 }
2053
2054 #if STM32MP_USB_PROGRAMMER
2055 ret = stm32mp1_clk_check_usb_conflict(priv, usbphy_p, usbo_p);
2056 if (ret != 0) {
2057 return ret;
2058 }
2059 #endif
2060 /* reconfigure STGEN with DT config */
2061 ret = stm32_clk_stgen_configure(priv, _STGENC);
2062 if (ret != 0) {
2063 panic();
2064 }
2065
2066 /* Software Self-Refresh mode (SSR) during DDR initilialization */
2067 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR,
2068 RCC_DDRITFCR_DDRCKMOD_MASK,
2069 RCC_DDRITFCR_DDRCKMOD_SSR <<
2070 RCC_DDRITFCR_DDRCKMOD_SHIFT);
2071
2072 return 0;
2073 }
2074
2075 #define LSEDRV_MEDIUM_HIGH 2
2076
clk_stm32_parse_oscillator_fdt(void * fdt,int node,const char * name,struct stm32_osci_dt_cfg * osci)2077 static int clk_stm32_parse_oscillator_fdt(void *fdt, int node, const char *name,
2078 struct stm32_osci_dt_cfg *osci)
2079 {
2080 int subnode = 0;
2081
2082 /* default value oscillator not found, freq=0 */
2083 osci->freq = 0;
2084
2085 fdt_for_each_subnode(subnode, fdt, node) {
2086 const char *cchar = NULL;
2087 const fdt32_t *cuint = NULL;
2088 int ret = 0;
2089
2090 cchar = fdt_get_name(fdt, subnode, &ret);
2091 if (cchar == NULL) {
2092 return ret;
2093 }
2094
2095 if (strncmp(cchar, name, (size_t)ret) ||
2096 fdt_get_status(subnode) == DT_DISABLED) {
2097 continue;
2098 }
2099
2100 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret);
2101 if (cuint == NULL) {
2102 return ret;
2103 }
2104
2105 osci->freq = fdt32_to_cpu(*cuint);
2106
2107 if (fdt_getprop(fdt, subnode, "st,bypass", NULL) != NULL) {
2108 osci->bypass = true;
2109 }
2110
2111 if (fdt_getprop(fdt, subnode, "st,digbypass", NULL) != NULL) {
2112 osci->digbyp = true;
2113 }
2114
2115 if (fdt_getprop(fdt, subnode, "st,css", NULL) != NULL) {
2116 osci->css = true;
2117 }
2118
2119 osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", LSEDRV_MEDIUM_HIGH);
2120
2121 return 0;
2122 }
2123
2124 return 0;
2125 }
2126
stm32_clk_parse_fdt_all_oscillator(void * fdt,struct stm32_clk_platdata * pdata)2127 static int stm32_clk_parse_fdt_all_oscillator(void *fdt, struct stm32_clk_platdata *pdata)
2128 {
2129 int fdt_err = 0;
2130 uint32_t i = 0;
2131 int node = 0;
2132
2133 node = fdt_path_offset(fdt, "/clocks");
2134 if (node < 0) {
2135 return -FDT_ERR_NOTFOUND;
2136 }
2137
2138 for (i = 0; i < pdata->nosci; i++) {
2139 const char *name = NULL;
2140
2141 name = clk_stm32_get_oscillator_name((enum stm32_osc)i);
2142 if (name == NULL) {
2143 continue;
2144 }
2145
2146 fdt_err = clk_stm32_parse_oscillator_fdt(fdt, node, name, &pdata->osci[i]);
2147 if (fdt_err < 0) {
2148 panic();
2149 }
2150 }
2151
2152 return 0;
2153 }
2154
2155 #define RCC_PLL_NAME_SIZE 12
2156
clk_stm32_load_vco_config(void * fdt,int subnode,struct stm32_pll_vco * vco)2157 static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_vco *vco)
2158 {
2159 int err = 0;
2160
2161 err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, vco->div_mn);
2162 if (err != 0) {
2163 return err;
2164 }
2165
2166 err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLL_CSG_NB, vco->csg);
2167
2168 vco->csg_enabled = (err == 0);
2169
2170 if (err == -FDT_ERR_NOTFOUND) {
2171 err = 0;
2172 }
2173
2174 if (err != 0) {
2175 return err;
2176 }
2177
2178 vco->status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN | RCC_PLLNCR_PLLON;
2179
2180 vco->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0);
2181
2182 vco->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX);
2183
2184 return 0;
2185 }
2186
clk_stm32_load_output_config(void * fdt,int subnode,struct stm32_pll_output * output)2187 static int clk_stm32_load_output_config(void *fdt, int subnode, struct stm32_pll_output *output)
2188 {
2189 int err = 0;
2190
2191 err = fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr", (int)PLL_DIV_PQR_NB,
2192 output->output);
2193 if (err != 0) {
2194 return err;
2195 }
2196
2197 return 0;
2198 }
2199
clk_stm32_parse_pll_fdt(void * fdt,int subnode,struct stm32_pll_dt_cfg * pll)2200 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)
2201 {
2202 const fdt32_t *cuint = NULL;
2203 int subnode_pll = 0;
2204 int subnode_vco = 0;
2205 int err = 0;
2206
2207 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);
2208 if (!cuint) {
2209 return -FDT_ERR_NOTFOUND;
2210 }
2211
2212 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
2213 if (subnode_pll < 0) {
2214 return -FDT_ERR_NOTFOUND;
2215 }
2216
2217 cuint = fdt_getprop(fdt, subnode_pll, "st,pll_vco", NULL);
2218 if (!cuint) {
2219 return -FDT_ERR_NOTFOUND;
2220 }
2221
2222 subnode_vco = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
2223 if (subnode_vco < 0) {
2224 return -FDT_ERR_NOTFOUND;
2225 }
2226
2227 err = clk_stm32_load_vco_config(fdt, subnode_vco, &pll->vco);
2228 if (err != 0) {
2229 return err;
2230 }
2231
2232 err = clk_stm32_load_output_config(fdt, subnode_pll, &pll->output);
2233 if (err != 0) {
2234 return err;
2235 }
2236
2237 return 0;
2238 }
2239
stm32_clk_parse_fdt_all_pll(void * fdt,int node,struct stm32_clk_platdata * pdata)2240 static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata)
2241 {
2242 size_t i = 0U;
2243
2244 for (i = _PLL1; i < pdata->npll; i++) {
2245 struct stm32_pll_dt_cfg *pll = pdata->pll + i;
2246 char name[RCC_PLL_NAME_SIZE];
2247 int subnode = 0;
2248 int err = 0;
2249
2250 snprintf(name, sizeof(name), "st,pll@%u", i);
2251
2252 subnode = fdt_subnode_offset(fdt, node, name);
2253 if (!fdt_check_node(subnode)) {
2254 continue;
2255 }
2256
2257 err = clk_stm32_parse_pll_fdt(fdt, subnode, pll);
2258 if (err != 0) {
2259 panic();
2260 }
2261 }
2262
2263 return 0;
2264 }
2265
stm32_clk_parse_fdt(struct stm32_clk_platdata * pdata)2266 static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata)
2267 {
2268 void *fdt = NULL;
2269 int node;
2270 uint32_t err;
2271
2272 if (fdt_get_address(&fdt) == 0) {
2273 return -ENOENT;
2274 }
2275
2276 node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
2277 if (node < 0) {
2278 panic();
2279 }
2280
2281 err = stm32_clk_parse_fdt_all_oscillator(fdt, pdata);
2282 if (err != 0) {
2283 return err;
2284 }
2285
2286 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata);
2287 if (err != 0) {
2288 return err;
2289 }
2290
2291 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clkdiv", pdata->clkdiv, &pdata->nclkdiv);
2292 if (err != 0) {
2293 return err;
2294 }
2295
2296 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clksrc", pdata->clksrc, &pdata->nclksrc);
2297 if (err != 0) {
2298 return err;
2299 }
2300
2301 return 0;
2302 }
2303
stm32mp1_clk_init(void)2304 int stm32mp1_clk_init(void)
2305 {
2306 return 0;
2307 }
2308
stm32mp1_clk_probe(void)2309 int stm32mp1_clk_probe(void)
2310 {
2311 uintptr_t base = RCC_BASE;
2312 int ret;
2313
2314 ret = stm32_clk_parse_fdt(&stm32mp13_clock_pdata);
2315 if (ret != 0) {
2316 return ret;
2317 }
2318
2319 ret = clk_stm32_init(&stm32mp13_clock_data, base);
2320 if (ret != 0) {
2321 return ret;
2322 }
2323
2324 ret = stm32mp1_init_clock_tree();
2325 if (ret != 0) {
2326 return ret;
2327 }
2328
2329 clk_stm32_enable_critical_clocks();
2330
2331 return 0;
2332 }
2333