1 /*
2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <endian.h>
9 #include <errno.h>
10 #include <stdint.h>
11 #include <string.h>
12
13 #include <platform_def.h>
14
15 #include <arch_helpers.h>
16 #include <common/debug.h>
17 #include <drivers/delay_timer.h>
18 #include <drivers/ufs.h>
19 #include <lib/mmio.h>
20
21 #define CDB_ADDR_MASK 127
22 #define ALIGN_CDB(x) (((x) + CDB_ADDR_MASK) & ~CDB_ADDR_MASK)
23 #define ALIGN_8(x) (((x) + 7) & ~7)
24
25 #define UFS_DESC_SIZE 0x400
26 #define MAX_UFS_DESC_SIZE 0x8000 /* 32 descriptors */
27
28 #define MAX_PRDT_SIZE 0x40000 /* 256KB */
29
30 static ufs_params_t ufs_params;
31 static int nutrs; /* Number of UTP Transfer Request Slots */
32
ufshc_send_uic_cmd(uintptr_t base,uic_cmd_t * cmd)33 int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd)
34 {
35 unsigned int data;
36
37 if (base == 0 || cmd == NULL)
38 return -EINVAL;
39
40 data = mmio_read_32(base + HCS);
41 if ((data & HCS_UCRDY) == 0)
42 return -EBUSY;
43 mmio_write_32(base + IS, ~0);
44 mmio_write_32(base + UCMDARG1, cmd->arg1);
45 mmio_write_32(base + UCMDARG2, cmd->arg2);
46 mmio_write_32(base + UCMDARG3, cmd->arg3);
47 mmio_write_32(base + UICCMD, cmd->op);
48
49 do {
50 data = mmio_read_32(base + IS);
51 } while ((data & UFS_INT_UCCS) == 0);
52 mmio_write_32(base + IS, UFS_INT_UCCS);
53 return mmio_read_32(base + UCMDARG2) & CONFIG_RESULT_CODE_MASK;
54 }
55
ufshc_dme_get(unsigned int attr,unsigned int idx,unsigned int * val)56 int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val)
57 {
58 uintptr_t base;
59 unsigned int data;
60 int result, retries;
61 uic_cmd_t cmd;
62
63 assert(ufs_params.reg_base != 0);
64
65 if (val == NULL)
66 return -EINVAL;
67
68 base = ufs_params.reg_base;
69 for (retries = 0; retries < 100; retries++) {
70 data = mmio_read_32(base + HCS);
71 if ((data & HCS_UCRDY) != 0)
72 break;
73 mdelay(1);
74 }
75 if (retries >= 100)
76 return -EBUSY;
77
78 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx);
79 cmd.arg2 = 0;
80 cmd.arg3 = 0;
81 cmd.op = DME_GET;
82 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) {
83 result = ufshc_send_uic_cmd(base, &cmd);
84 if (result == 0)
85 break;
86 data = mmio_read_32(base + IS);
87 if (data & UFS_INT_UE)
88 return -EINVAL;
89 }
90 if (retries >= UFS_UIC_COMMAND_RETRIES)
91 return -EIO;
92
93 *val = mmio_read_32(base + UCMDARG3);
94 return 0;
95 }
96
ufshc_dme_set(unsigned int attr,unsigned int idx,unsigned int val)97 int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val)
98 {
99 uintptr_t base;
100 unsigned int data;
101 int result, retries;
102 uic_cmd_t cmd;
103
104 assert((ufs_params.reg_base != 0));
105
106 base = ufs_params.reg_base;
107 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx);
108 cmd.arg2 = 0;
109 cmd.arg3 = val;
110 cmd.op = DME_SET;
111
112 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) {
113 result = ufshc_send_uic_cmd(base, &cmd);
114 if (result == 0)
115 break;
116 data = mmio_read_32(base + IS);
117 if (data & UFS_INT_UE)
118 return -EINVAL;
119 }
120 if (retries >= UFS_UIC_COMMAND_RETRIES)
121 return -EIO;
122
123 return 0;
124 }
125
ufshc_hce_enable(uintptr_t base)126 static int ufshc_hce_enable(uintptr_t base)
127 {
128 unsigned int data;
129 int retries;
130
131 /* Enable Host Controller */
132 mmio_write_32(base + HCE, HCE_ENABLE);
133
134 /* Wait until basic initialization sequence completed */
135 for (retries = 0; retries < HCE_ENABLE_INNER_RETRIES; ++retries) {
136 data = mmio_read_32(base + HCE);
137 if (data & HCE_ENABLE) {
138 break;
139 }
140 udelay(HCE_ENABLE_TIMEOUT_US);
141 }
142 if (retries >= HCE_ENABLE_INNER_RETRIES) {
143 return -ETIMEDOUT;
144 }
145
146 return 0;
147 }
148
ufshc_hce_disable(uintptr_t base)149 static int ufshc_hce_disable(uintptr_t base)
150 {
151 unsigned int data;
152 int timeout;
153
154 /* Disable Host Controller */
155 mmio_write_32(base + HCE, HCE_DISABLE);
156 timeout = HCE_DISABLE_TIMEOUT_US;
157 do {
158 data = mmio_read_32(base + HCE);
159 if ((data & HCE_ENABLE) == HCE_DISABLE) {
160 break;
161 }
162 udelay(1);
163 } while (--timeout > 0);
164
165 if (timeout <= 0) {
166 return -ETIMEDOUT;
167 }
168
169 return 0;
170 }
171
172
ufshc_reset(uintptr_t base)173 static int ufshc_reset(uintptr_t base)
174 {
175 unsigned int data;
176 int retries, result;
177
178 /* disable controller if enabled */
179 if (mmio_read_32(base + HCE) & HCE_ENABLE) {
180 result = ufshc_hce_disable(base);
181 if (result != 0) {
182 return -EIO;
183 }
184 }
185
186 for (retries = 0; retries < HCE_ENABLE_OUTER_RETRIES; ++retries) {
187 result = ufshc_hce_enable(base);
188 if (result == 0) {
189 break;
190 }
191 }
192 if (retries >= HCE_ENABLE_OUTER_RETRIES) {
193 return -EIO;
194 }
195
196 /* Enable Interrupts */
197 data = UFS_INT_UCCS | UFS_INT_ULSS | UFS_INT_UE | UFS_INT_UTPES |
198 UFS_INT_DFES | UFS_INT_HCFES | UFS_INT_SBFES;
199 mmio_write_32(base + IE, data);
200
201 return 0;
202 }
203
ufshc_dme_link_startup(uintptr_t base)204 static int ufshc_dme_link_startup(uintptr_t base)
205 {
206 uic_cmd_t cmd;
207
208 memset(&cmd, 0, sizeof(cmd));
209 cmd.op = DME_LINKSTARTUP;
210 return ufshc_send_uic_cmd(base, &cmd);
211 }
212
ufshc_link_startup(uintptr_t base)213 static int ufshc_link_startup(uintptr_t base)
214 {
215 int data, result;
216 int retries;
217
218 for (retries = DME_LINKSTARTUP_RETRIES; retries > 0; retries--) {
219 result = ufshc_dme_link_startup(base);
220 if (result != 0) {
221 /* Reset controller before trying again */
222 result = ufshc_reset(base);
223 if (result != 0) {
224 return result;
225 }
226 continue;
227 }
228 assert((mmio_read_32(base + HCS) & HCS_DP) == 0);
229 data = mmio_read_32(base + IS);
230 if (data & UFS_INT_ULSS)
231 mmio_write_32(base + IS, UFS_INT_ULSS);
232 return 0;
233 }
234 return -EIO;
235 }
236
237 /* Check Door Bell register to get an empty slot */
get_empty_slot(int * slot)238 static int get_empty_slot(int *slot)
239 {
240 unsigned int data;
241 int i;
242
243 data = mmio_read_32(ufs_params.reg_base + UTRLDBR);
244 for (i = 0; i < nutrs; i++) {
245 if ((data & 1) == 0)
246 break;
247 data = data >> 1;
248 }
249 if (i >= nutrs)
250 return -EBUSY;
251 *slot = i;
252 return 0;
253 }
254
get_utrd(utp_utrd_t * utrd)255 static void get_utrd(utp_utrd_t *utrd)
256 {
257 uintptr_t base;
258 int slot = 0, result;
259 utrd_header_t *hd;
260
261 assert(utrd != NULL);
262 result = get_empty_slot(&slot);
263 assert(result == 0);
264
265 /* clear utrd */
266 memset((void *)utrd, 0, sizeof(utp_utrd_t));
267 base = ufs_params.desc_base + (slot * sizeof(utrd_header_t));
268 /* clear the descriptor */
269 memset((void *)base, 0, UFS_DESC_SIZE);
270
271 utrd->header = base;
272 utrd->task_tag = slot + 1;
273 /* CDB address should be aligned with 128 bytes */
274 utrd->upiu = ALIGN_CDB(utrd->header + sizeof(utrd_header_t));
275 utrd->resp_upiu = ALIGN_8(utrd->upiu + sizeof(cmd_upiu_t));
276 utrd->size_upiu = utrd->resp_upiu - utrd->upiu;
277 utrd->size_resp_upiu = ALIGN_8(sizeof(resp_upiu_t));
278 utrd->prdt = utrd->resp_upiu + utrd->size_resp_upiu;
279
280 hd = (utrd_header_t *)utrd->header;
281 hd->ucdba = utrd->upiu & UINT32_MAX;
282 hd->ucdbau = (utrd->upiu >> 32) & UINT32_MAX;
283 /* Both RUL and RUO is based on DWORD */
284 hd->rul = utrd->size_resp_upiu >> 2;
285 hd->ruo = utrd->size_upiu >> 2;
286 (void)result;
287 }
288
289 /*
290 * Prepare UTRD, Command UPIU, Response UPIU.
291 */
ufs_prepare_cmd(utp_utrd_t * utrd,uint8_t op,uint8_t lun,int lba,uintptr_t buf,size_t length)292 static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun,
293 int lba, uintptr_t buf, size_t length)
294 {
295 utrd_header_t *hd;
296 cmd_upiu_t *upiu;
297 prdt_t *prdt;
298 unsigned int ulba;
299 unsigned int lba_cnt;
300 int prdt_size;
301
302 hd = (utrd_header_t *)utrd->header;
303 upiu = (cmd_upiu_t *)utrd->upiu;
304
305 hd->i = 1;
306 hd->ct = CT_UFS_STORAGE;
307 hd->ocs = OCS_MASK;
308
309 upiu->trans_type = CMD_UPIU;
310 upiu->task_tag = utrd->task_tag;
311 upiu->cdb[0] = op;
312 ulba = (unsigned int)lba;
313 lba_cnt = (unsigned int)(length >> UFS_BLOCK_SHIFT);
314 switch (op) {
315 case CDBCMD_TEST_UNIT_READY:
316 break;
317 case CDBCMD_READ_CAPACITY_10:
318 hd->dd = DD_OUT;
319 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S;
320 upiu->lun = lun;
321 break;
322 case CDBCMD_READ_10:
323 hd->dd = DD_OUT;
324 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S;
325 upiu->lun = lun;
326 upiu->cdb[1] = RW_WITHOUT_CACHE;
327 /* set logical block address */
328 upiu->cdb[2] = (ulba >> 24) & 0xff;
329 upiu->cdb[3] = (ulba >> 16) & 0xff;
330 upiu->cdb[4] = (ulba >> 8) & 0xff;
331 upiu->cdb[5] = ulba & 0xff;
332 /* set transfer length */
333 upiu->cdb[7] = (lba_cnt >> 8) & 0xff;
334 upiu->cdb[8] = lba_cnt & 0xff;
335 break;
336 case CDBCMD_WRITE_10:
337 hd->dd = DD_IN;
338 upiu->flags = UPIU_FLAGS_W | UPIU_FLAGS_ATTR_S;
339 upiu->lun = lun;
340 upiu->cdb[1] = RW_WITHOUT_CACHE;
341 /* set logical block address */
342 upiu->cdb[2] = (ulba >> 24) & 0xff;
343 upiu->cdb[3] = (ulba >> 16) & 0xff;
344 upiu->cdb[4] = (ulba >> 8) & 0xff;
345 upiu->cdb[5] = ulba & 0xff;
346 /* set transfer length */
347 upiu->cdb[7] = (lba_cnt >> 8) & 0xff;
348 upiu->cdb[8] = lba_cnt & 0xff;
349 break;
350 default:
351 assert(0);
352 break;
353 }
354 if (hd->dd == DD_IN)
355 flush_dcache_range(buf, length);
356 else if (hd->dd == DD_OUT)
357 inv_dcache_range(buf, length);
358 if (length) {
359 upiu->exp_data_trans_len = htobe32(length);
360 assert(lba_cnt <= UINT16_MAX);
361 prdt = (prdt_t *)utrd->prdt;
362
363 prdt_size = 0;
364 while (length > 0) {
365 prdt->dba = (unsigned int)(buf & UINT32_MAX);
366 prdt->dbau = (unsigned int)((buf >> 32) & UINT32_MAX);
367 /* prdt->dbc counts from 0 */
368 if (length > MAX_PRDT_SIZE) {
369 prdt->dbc = MAX_PRDT_SIZE - 1;
370 length = length - MAX_PRDT_SIZE;
371 } else {
372 prdt->dbc = length - 1;
373 length = 0;
374 }
375 buf += MAX_PRDT_SIZE;
376 prdt++;
377 prdt_size += sizeof(prdt_t);
378 }
379 utrd->size_prdt = ALIGN_8(prdt_size);
380 hd->prdtl = utrd->size_prdt >> 2;
381 hd->prdto = (utrd->size_upiu + utrd->size_resp_upiu) >> 2;
382 }
383
384 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
385 return 0;
386 }
387
ufs_prepare_query(utp_utrd_t * utrd,uint8_t op,uint8_t idn,uint8_t index,uint8_t sel,uintptr_t buf,size_t length)388 static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn,
389 uint8_t index, uint8_t sel,
390 uintptr_t buf, size_t length)
391 {
392 utrd_header_t *hd;
393 query_upiu_t *query_upiu;
394
395
396 hd = (utrd_header_t *)utrd->header;
397 query_upiu = (query_upiu_t *)utrd->upiu;
398
399 hd->i = 1;
400 hd->ct = CT_UFS_STORAGE;
401 hd->ocs = OCS_MASK;
402
403 query_upiu->trans_type = QUERY_REQUEST_UPIU;
404 query_upiu->task_tag = utrd->task_tag;
405 query_upiu->ts.desc.opcode = op;
406 query_upiu->ts.desc.idn = idn;
407 query_upiu->ts.desc.index = index;
408 query_upiu->ts.desc.selector = sel;
409 switch (op) {
410 case QUERY_READ_DESC:
411 query_upiu->query_func = QUERY_FUNC_STD_READ;
412 query_upiu->ts.desc.length = htobe16(length);
413 break;
414 case QUERY_WRITE_DESC:
415 query_upiu->query_func = QUERY_FUNC_STD_WRITE;
416 query_upiu->ts.desc.length = htobe16(length);
417 memcpy((void *)(utrd->upiu + sizeof(query_upiu_t)),
418 (void *)buf, length);
419 break;
420 case QUERY_READ_ATTR:
421 case QUERY_READ_FLAG:
422 query_upiu->query_func = QUERY_FUNC_STD_READ;
423 break;
424 case QUERY_CLEAR_FLAG:
425 case QUERY_SET_FLAG:
426 query_upiu->query_func = QUERY_FUNC_STD_WRITE;
427 break;
428 case QUERY_WRITE_ATTR:
429 query_upiu->query_func = QUERY_FUNC_STD_WRITE;
430 query_upiu->ts.attr.value = htobe32(*((uint32_t *)buf));
431 break;
432 default:
433 assert(0);
434 break;
435 }
436 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
437 return 0;
438 }
439
ufs_prepare_nop_out(utp_utrd_t * utrd)440 static void ufs_prepare_nop_out(utp_utrd_t *utrd)
441 {
442 utrd_header_t *hd;
443 nop_out_upiu_t *nop_out;
444
445 hd = (utrd_header_t *)utrd->header;
446 nop_out = (nop_out_upiu_t *)utrd->upiu;
447
448 hd->i = 1;
449 hd->ct = CT_UFS_STORAGE;
450 hd->ocs = OCS_MASK;
451
452 nop_out->trans_type = 0;
453 nop_out->task_tag = utrd->task_tag;
454 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
455 }
456
ufs_send_request(int task_tag)457 static void ufs_send_request(int task_tag)
458 {
459 unsigned int data;
460 int slot;
461
462 slot = task_tag - 1;
463 /* clear all interrupts */
464 mmio_write_32(ufs_params.reg_base + IS, ~0);
465
466 mmio_write_32(ufs_params.reg_base + UTRLRSR, 1);
467 assert(mmio_read_32(ufs_params.reg_base + UTRLRSR) == 1);
468
469 data = UTRIACR_IAEN | UTRIACR_CTR | UTRIACR_IACTH(0x1F) |
470 UTRIACR_IATOVAL(0xFF);
471 mmio_write_32(ufs_params.reg_base + UTRIACR, data);
472 /* send request */
473 mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot);
474 }
475
ufs_check_resp(utp_utrd_t * utrd,int trans_type)476 static int ufs_check_resp(utp_utrd_t *utrd, int trans_type)
477 {
478 utrd_header_t *hd;
479 resp_upiu_t *resp;
480 sense_data_t *sense;
481 unsigned int data;
482 int slot;
483
484 hd = (utrd_header_t *)utrd->header;
485 resp = (resp_upiu_t *)utrd->resp_upiu;
486 do {
487 data = mmio_read_32(ufs_params.reg_base + IS);
488 if ((data & ~(UFS_INT_UCCS | UFS_INT_UTRCS)) != 0)
489 return -EIO;
490 } while ((data & UFS_INT_UTRCS) == 0);
491 slot = utrd->task_tag - 1;
492
493 data = mmio_read_32(ufs_params.reg_base + UTRLDBR);
494 assert((data & (1 << slot)) == 0);
495 /*
496 * Invalidate the header after DMA read operation has
497 * completed to avoid cpu referring to the prefetched
498 * data brought in before DMA completion.
499 */
500 inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE);
501 assert(hd->ocs == OCS_SUCCESS);
502 assert((resp->trans_type & TRANS_TYPE_CODE_MASK) == trans_type);
503
504 sense = &resp->sd.sense;
505 if (sense->resp_code == SENSE_DATA_VALID &&
506 sense->sense_key == SENSE_KEY_UNIT_ATTENTION && sense->asc == 0x29 &&
507 sense->ascq == 0) {
508 WARN("Unit Attention Condition\n");
509 return -EAGAIN;
510 }
511
512 (void)resp;
513 (void)slot;
514 return 0;
515 }
516
ufs_send_cmd(utp_utrd_t * utrd,uint8_t cmd_op,uint8_t lun,int lba,uintptr_t buf,size_t length)517 static void ufs_send_cmd(utp_utrd_t *utrd, uint8_t cmd_op, uint8_t lun, int lba, uintptr_t buf,
518 size_t length)
519 {
520 int result, i;
521
522 for (i = 0; i < UFS_CMD_RETRIES; ++i) {
523 get_utrd(utrd);
524 result = ufs_prepare_cmd(utrd, cmd_op, lun, lba, buf, length);
525 assert(result == 0);
526 ufs_send_request(utrd->task_tag);
527 result = ufs_check_resp(utrd, RESPONSE_UPIU);
528 if (result == 0 || result == -EIO) {
529 break;
530 }
531 }
532 assert(result == 0);
533 (void)result;
534 }
535
536 #ifdef UFS_RESP_DEBUG
dump_upiu(utp_utrd_t * utrd)537 static void dump_upiu(utp_utrd_t *utrd)
538 {
539 utrd_header_t *hd;
540 int i;
541
542 hd = (utrd_header_t *)utrd->header;
543 INFO("utrd:0x%x, ruo:0x%x, rul:0x%x, ocs:0x%x, UTRLDBR:0x%x\n",
544 (unsigned int)(uintptr_t)utrd, hd->ruo, hd->rul, hd->ocs,
545 mmio_read_32(ufs_params.reg_base + UTRLDBR));
546 for (i = 0; i < sizeof(utrd_header_t); i += 4) {
547 INFO("[%lx]:0x%x\n",
548 (uintptr_t)utrd->header + i,
549 *(unsigned int *)((uintptr_t)utrd->header + i));
550 }
551
552 for (i = 0; i < sizeof(cmd_upiu_t); i += 4) {
553 INFO("cmd[%lx]:0x%x\n",
554 utrd->upiu + i,
555 *(unsigned int *)(utrd->upiu + i));
556 }
557 for (i = 0; i < sizeof(resp_upiu_t); i += 4) {
558 INFO("resp[%lx]:0x%x\n",
559 utrd->resp_upiu + i,
560 *(unsigned int *)(utrd->resp_upiu + i));
561 }
562 for (i = 0; i < sizeof(prdt_t); i += 4) {
563 INFO("prdt[%lx]:0x%x\n",
564 utrd->prdt + i,
565 *(unsigned int *)(utrd->prdt + i));
566 }
567 }
568 #endif
569
ufs_verify_init(void)570 static void ufs_verify_init(void)
571 {
572 utp_utrd_t utrd;
573 int result;
574
575 get_utrd(&utrd);
576 ufs_prepare_nop_out(&utrd);
577 ufs_send_request(utrd.task_tag);
578 result = ufs_check_resp(&utrd, NOP_IN_UPIU);
579 assert(result == 0);
580 (void)result;
581 }
582
ufs_verify_ready(void)583 static void ufs_verify_ready(void)
584 {
585 utp_utrd_t utrd;
586 ufs_send_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0);
587 }
588
ufs_query(uint8_t op,uint8_t idn,uint8_t index,uint8_t sel,uintptr_t buf,size_t size)589 static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel,
590 uintptr_t buf, size_t size)
591 {
592 utp_utrd_t utrd;
593 query_resp_upiu_t *resp;
594 int result;
595
596 switch (op) {
597 case QUERY_READ_FLAG:
598 case QUERY_READ_ATTR:
599 case QUERY_READ_DESC:
600 case QUERY_WRITE_DESC:
601 case QUERY_WRITE_ATTR:
602 assert(((buf & 3) == 0) && (size != 0));
603 break;
604 default:
605 /* Do nothing in default case */
606 break;
607 }
608 get_utrd(&utrd);
609 ufs_prepare_query(&utrd, op, idn, index, sel, buf, size);
610 ufs_send_request(utrd.task_tag);
611 result = ufs_check_resp(&utrd, QUERY_RESPONSE_UPIU);
612 assert(result == 0);
613 resp = (query_resp_upiu_t *)utrd.resp_upiu;
614 #ifdef UFS_RESP_DEBUG
615 dump_upiu(&utrd);
616 #endif
617 assert(resp->query_resp == QUERY_RESP_SUCCESS);
618
619 switch (op) {
620 case QUERY_READ_FLAG:
621 *(uint32_t *)buf = (uint32_t)resp->ts.flag.value;
622 break;
623 case QUERY_READ_DESC:
624 memcpy((void *)buf,
625 (void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)),
626 size);
627 break;
628 case QUERY_READ_ATTR:
629 *(uint32_t *)buf = htobe32(resp->ts.attr.value);
630 break;
631 default:
632 /* Do nothing in default case */
633 break;
634 }
635 (void)result;
636 }
637
ufs_read_attr(int idn)638 unsigned int ufs_read_attr(int idn)
639 {
640 unsigned int value;
641
642 ufs_query(QUERY_READ_ATTR, idn, 0, 0,
643 (uintptr_t)&value, sizeof(value));
644 return value;
645 }
646
ufs_write_attr(int idn,unsigned int value)647 void ufs_write_attr(int idn, unsigned int value)
648 {
649 ufs_query(QUERY_WRITE_ATTR, idn, 0, 0,
650 (uintptr_t)&value, sizeof(value));
651 }
652
ufs_read_flag(int idn)653 unsigned int ufs_read_flag(int idn)
654 {
655 unsigned int value;
656
657 ufs_query(QUERY_READ_FLAG, idn, 0, 0,
658 (uintptr_t)&value, sizeof(value));
659 return value;
660 }
661
ufs_set_flag(int idn)662 void ufs_set_flag(int idn)
663 {
664 ufs_query(QUERY_SET_FLAG, idn, 0, 0, 0, 0);
665 }
666
ufs_clear_flag(int idn)667 void ufs_clear_flag(int idn)
668 {
669 ufs_query(QUERY_CLEAR_FLAG, idn, 0, 0, 0, 0);
670 }
671
ufs_read_desc(int idn,int index,uintptr_t buf,size_t size)672 void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size)
673 {
674 ufs_query(QUERY_READ_DESC, idn, index, 0, buf, size);
675 }
676
ufs_write_desc(int idn,int index,uintptr_t buf,size_t size)677 void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size)
678 {
679 ufs_query(QUERY_WRITE_DESC, idn, index, 0, buf, size);
680 }
681
ufs_read_capacity(int lun,unsigned int * num,unsigned int * size)682 static int ufs_read_capacity(int lun, unsigned int *num, unsigned int *size)
683 {
684 utp_utrd_t utrd;
685 resp_upiu_t *resp;
686 sense_data_t *sense;
687 unsigned char data[CACHE_WRITEBACK_GRANULE << 1];
688 uintptr_t buf;
689 int retries = UFS_READ_CAPACITY_RETRIES;
690
691 assert((ufs_params.reg_base != 0) &&
692 (ufs_params.desc_base != 0) &&
693 (ufs_params.desc_size >= UFS_DESC_SIZE) &&
694 (num != NULL) && (size != NULL));
695
696 /* align buf address */
697 buf = (uintptr_t)data;
698 buf = (buf + CACHE_WRITEBACK_GRANULE - 1) &
699 ~(CACHE_WRITEBACK_GRANULE - 1);
700 do {
701 ufs_send_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0,
702 buf, READ_CAPACITY_LENGTH);
703 #ifdef UFS_RESP_DEBUG
704 dump_upiu(&utrd);
705 #endif
706 resp = (resp_upiu_t *)utrd.resp_upiu;
707 sense = &resp->sd.sense;
708 if (!((sense->resp_code == SENSE_DATA_VALID) &&
709 (sense->sense_key == SENSE_KEY_UNIT_ATTENTION) &&
710 (sense->asc == 0x29) && (sense->ascq == 0))) {
711 inv_dcache_range(buf, CACHE_WRITEBACK_GRANULE);
712 /* last logical block address */
713 *num = be32toh(*(unsigned int *)buf);
714 if (*num)
715 *num += 1;
716 /* logical block length in bytes */
717 *size = be32toh(*(unsigned int *)(buf + 4));
718
719 return 0;
720 }
721
722 } while (retries-- > 0);
723
724 return -ETIMEDOUT;
725 }
726
ufs_read_blocks(int lun,int lba,uintptr_t buf,size_t size)727 size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size)
728 {
729 utp_utrd_t utrd;
730 resp_upiu_t *resp;
731
732 assert((ufs_params.reg_base != 0) &&
733 (ufs_params.desc_base != 0) &&
734 (ufs_params.desc_size >= UFS_DESC_SIZE));
735
736 ufs_send_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size);
737 #ifdef UFS_RESP_DEBUG
738 dump_upiu(&utrd);
739 #endif
740 /*
741 * Invalidate prefetched cache contents before cpu
742 * accesses the buf.
743 */
744 inv_dcache_range(buf, size);
745 resp = (resp_upiu_t *)utrd.resp_upiu;
746 return size - resp->res_trans_cnt;
747 }
748
ufs_write_blocks(int lun,int lba,const uintptr_t buf,size_t size)749 size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size)
750 {
751 utp_utrd_t utrd;
752 resp_upiu_t *resp;
753
754 assert((ufs_params.reg_base != 0) &&
755 (ufs_params.desc_base != 0) &&
756 (ufs_params.desc_size >= UFS_DESC_SIZE));
757
758 ufs_send_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size);
759 #ifdef UFS_RESP_DEBUG
760 dump_upiu(&utrd);
761 #endif
762 resp = (resp_upiu_t *)utrd.resp_upiu;
763 return size - resp->res_trans_cnt;
764 }
765
ufs_set_fdevice_init(void)766 static int ufs_set_fdevice_init(void)
767 {
768 unsigned int result;
769 int timeout;
770
771 ufs_set_flag(FLAG_DEVICE_INIT);
772
773 timeout = FDEVICEINIT_TIMEOUT_MS;
774 do {
775 result = ufs_read_flag(FLAG_DEVICE_INIT);
776 if (!result) {
777 break;
778 }
779 mdelay(5);
780 timeout -= 5;
781 } while (timeout > 0);
782
783 if (result != 0U) {
784 return -ETIMEDOUT;
785 }
786
787 return 0;
788 }
789
ufs_enum(void)790 static void ufs_enum(void)
791 {
792 unsigned int blk_num, blk_size;
793 int i, result;
794
795 mmio_write_32(ufs_params.reg_base + UTRLBA,
796 ufs_params.desc_base & UINT32_MAX);
797 mmio_write_32(ufs_params.reg_base + UTRLBAU,
798 (ufs_params.desc_base >> 32) & UINT32_MAX);
799
800 ufs_verify_init();
801 ufs_verify_ready();
802
803 result = ufs_set_fdevice_init();
804 assert(result == 0);
805
806 blk_num = 0;
807 blk_size = 0;
808
809 /* dump available LUNs */
810 for (i = 0; i < UFS_MAX_LUNS; i++) {
811 result = ufs_read_capacity(i, &blk_num, &blk_size);
812 if (result != 0) {
813 WARN("UFS LUN%d dump failed\n", i);
814 }
815 if (blk_num && blk_size) {
816 INFO("UFS LUN%d contains %d blocks with %d-byte size\n",
817 i, blk_num, blk_size);
818 }
819 }
820
821 (void)result;
822 }
823
ufs_get_device_info(struct ufs_dev_desc * card_data)824 static void ufs_get_device_info(struct ufs_dev_desc *card_data)
825 {
826 uint8_t desc_buf[DESC_DEVICE_MAX_SIZE];
827
828 ufs_query(QUERY_READ_DESC, DESC_TYPE_DEVICE, 0, 0,
829 (uintptr_t)desc_buf, DESC_DEVICE_MAX_SIZE);
830
831 /*
832 * getting vendor (manufacturerID) and Bank Index in big endian
833 * format
834 */
835 card_data->wmanufacturerid = (uint16_t)((desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8) |
836 (desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]));
837 }
838
ufs_init(const ufs_ops_t * ops,ufs_params_t * params)839 int ufs_init(const ufs_ops_t *ops, ufs_params_t *params)
840 {
841 int result;
842 unsigned int data;
843 uic_cmd_t cmd;
844 struct ufs_dev_desc card = {0};
845
846 assert((params != NULL) &&
847 (params->reg_base != 0) &&
848 (params->desc_base != 0) &&
849 (params->desc_size >= UFS_DESC_SIZE));
850
851 memcpy(&ufs_params, params, sizeof(ufs_params_t));
852
853 /* 0 means 1 slot */
854 nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1;
855 if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE)) {
856 nutrs = ufs_params.desc_size / UFS_DESC_SIZE;
857 }
858
859
860 if (ufs_params.flags & UFS_FLAGS_SKIPINIT) {
861 mmio_write_32(ufs_params.reg_base + UTRLBA,
862 ufs_params.desc_base & UINT32_MAX);
863 mmio_write_32(ufs_params.reg_base + UTRLBAU,
864 (ufs_params.desc_base >> 32) & UINT32_MAX);
865
866 result = ufshc_dme_get(0x1571, 0, &data);
867 assert(result == 0);
868 result = ufshc_dme_get(0x41, 0, &data);
869 assert(result == 0);
870 if (data == 1) {
871 /* prepare to exit hibernate mode */
872 memset(&cmd, 0, sizeof(uic_cmd_t));
873 cmd.op = DME_HIBERNATE_EXIT;
874 result = ufshc_send_uic_cmd(ufs_params.reg_base,
875 &cmd);
876 assert(result == 0);
877 data = mmio_read_32(ufs_params.reg_base + UCMDARG2);
878 assert(data == 0);
879 do {
880 data = mmio_read_32(ufs_params.reg_base + IS);
881 } while ((data & UFS_INT_UHXS) == 0);
882 mmio_write_32(ufs_params.reg_base + IS, UFS_INT_UHXS);
883 data = mmio_read_32(ufs_params.reg_base + HCS);
884 assert((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL);
885 }
886 result = ufshc_dme_get(0x1568, 0, &data);
887 assert(result == 0);
888 assert((data > 0) && (data <= 3));
889 } else {
890 assert((ops != NULL) && (ops->phy_init != NULL) &&
891 (ops->phy_set_pwr_mode != NULL));
892
893 result = ufshc_reset(ufs_params.reg_base);
894 assert(result == 0);
895 ops->phy_init(&ufs_params);
896 result = ufshc_link_startup(ufs_params.reg_base);
897 assert(result == 0);
898
899 ufs_enum();
900
901 ufs_get_device_info(&card);
902 if (card.wmanufacturerid == UFS_VENDOR_SKHYNIX) {
903 ufs_params.flags |= UFS_FLAGS_VENDOR_SKHYNIX;
904 }
905
906 ops->phy_set_pwr_mode(&ufs_params);
907 }
908
909 (void)result;
910 return 0;
911 }
912