1/*
2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_a78c.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* --------------------------------------------------
21 * Errata Workaround for Cortex A78C Erratum 2376749.
22 * This applies to revision r0p1 and r0p2 of the A78C
23 * and is currently open. It is a Cat B erratum.
24 * Inputs:
25 * x0: variant[4:7] and revision[0:3] of current cpu.
26 * Shall clobber: x0-x4, x17
27 * --------------------------------------------------
28 */
29func errata_a78c_2376749_wa
30	/* Check revision */
31	mov	x17, x30
32	bl	check_errata_2376749
33	cbz	x0, 1f
34	/* Set CPUACTLR2_EL1[0] to 1. */
35	mrs	x1, CORTEX_A78C_CPUACTLR2_EL1
36	orr	x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0
37	msr	CORTEX_A78C_CPUACTLR2_EL1, x1
381:
39	ret	x17
40endfunc errata_a78c_2376749_wa
41
42func check_errata_2376749
43	/* Applies to r0p1 and r0p2*/
44	mov	x1, #0x01
45	mov	x2, #0x02
46	b	cpu_rev_var_range
47endfunc check_errata_2376749
48
49/* --------------------------------------------------
50 * Errata Workaround for Cortex A78C Erratum 2395411.
51 * This applies to revision r0p1 and r0p2 of the A78C
52 * and is currently open. It is a Cat B erratum.
53 * Inputs:
54 * x0: variant[4:7] and revision[0:3] of current cpu.
55 * Shall clobber: x0-x4, x17
56 * --------------------------------------------------
57 */
58func errata_a78c_2395411_wa
59	/* Check revision. */
60	mov 	x17, x30
61	bl 	check_errata_2395411
62	cbz 	x0, 1f
63
64	/* Set CPUACTRL2_EL1[40] to 1. */
65	mrs 	x1, CORTEX_A78C_CPUACTLR2_EL1
66	orr 	x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40
67	msr 	CORTEX_A78C_CPUACTLR2_EL1, x1
681:
69	ret 	x17
70endfunc errata_a78c_2395411_wa
71
72func check_errata_2395411
73	/* Applies to r0p1 and r0p2 */
74	mov 	x1, #0x01
75	mov 	x2, #0x02
76	b 	cpu_rev_var_range
77endfunc check_errata_2395411
78
79#if WORKAROUND_CVE_2022_23960
80	wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
81#endif /* WORKAROUND_CVE_2022_23960 */
82
83/* --------------------------------------------------
84 * Errata Workaround for A78C Erratum 2132064.
85 * This applies to revisions r0p1 and r0p2 of A78C
86 * and is still open.
87 * Inputs:
88 * x0: variant[4:7] and revision[0:3] of current cpu.
89 * Shall clobber: x0-x17
90 * --------------------------------------------------
91 */
92func errata_a78c_2132064_wa
93	/* Compare x0 against revisions r0p0 - r0p1 */
94	mov	x17, x30
95	bl	check_errata_2132064
96	cbz	x0, 1f
97
98	/* --------------------------------------------------------
99	 * Place the data prefetcher in the most conservative mode
100	 * to reduce prefetches by writing the following bits to
101	 * the value indicated: ecltr[7:6], PF_MODE = 2'b11
102	 * --------------------------------------------------------
103	 */
104	mrs	x0, CORTEX_A78C_CPUECTLR_EL1
105	orr	x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6
106	orr	x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7
107	msr	CORTEX_A78C_CPUECTLR_EL1, x0
108	isb
1091:
110	ret	x17
111endfunc errata_a78c_2132064_wa
112
113func check_errata_2132064
114	/* Applies to revisions r0p1 and r0p2. */
115	mov	x1, #CPU_REV(0, 1)
116	mov	x2, #CPU_REV(0, 2)
117	b	cpu_rev_var_range
118endfunc check_errata_2132064
119
120/* --------------------------------------------------------------------
121 * Errata Workaround for A78C Erratum 2242638.
122 * This applies to revisions r0p1 and r0p2 of the Cortex A78C
123 * processor and is still open.
124 * x0: variant[4:7] and revision[0:3] of current cpu.
125 * Shall clobber: x0-x17
126 * --------------------------------------------------------------------
127 */
128func errata_a78c_2242638_wa
129	/* Compare x0 against revisions r0p1 - r0p2 */
130	mov	x17, x30
131	bl	check_errata_2242638
132	cbz	x0, 1f
133
134	ldr	x0, =0x5
135	msr	CORTEX_A78C_IMP_CPUPSELR_EL3, x0
136	ldr	x0, =0x10F600E000
137	msr	CORTEX_A78C_IMP_CPUPOR_EL3, x0
138	ldr	x0, =0x10FF80E000
139	msr	CORTEX_A78C_IMP_CPUPMR_EL3, x0
140	ldr	x0, =0x80000000003FF
141	msr	CORTEX_A78C_IMP_CPUPCR_EL3, x0
142
143	isb
1441:
145	ret	x17
146endfunc errata_a78c_2242638_wa
147
148func check_errata_2242638
149	/* Applies to revisions r0p1-r0p2. */
150	mov	x1, #CPU_REV(0, 1)
151	mov	x2, #CPU_REV(0, 2)
152	b	cpu_rev_var_range
153endfunc check_errata_2242638
154
155func check_errata_cve_2022_23960
156#if WORKAROUND_CVE_2022_23960
157	mov	x0, #ERRATA_APPLIES
158#else
159	mov	x0, #ERRATA_MISSING
160#endif
161	ret
162endfunc check_errata_cve_2022_23960
163
164	/* -------------------------------------------------
165	 * The CPU Ops reset function for Cortex-A78C
166	 * -------------------------------------------------
167	 */
168func cortex_a78c_reset_func
169	mov	x19, x30
170	bl	cpu_get_rev_var
171	mov	x18, x0
172
173#if ERRATA_A78C_2132064
174	mov	x0, x18
175	bl	errata_a78c_2132064_wa
176#endif
177
178#if ERRATA_A78C_2242638
179	mov	x0, x18
180	bl	errata_a78c_2242638_wa
181#endif
182
183#if ERRATA_A78C_2376749
184	mov	x0, x18
185	bl	errata_a78c_2376749_wa
186#endif
187
188#if ERRATA_A78C_2395411
189	mov 	x0, x18
190	bl	errata_a78c_2395411_wa
191#endif
192
193#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
194	/*
195	 * The Cortex-A78c generic vectors are overridden to apply errata
196	 * mitigation on exception entry from lower ELs.
197	 */
198	adr	x0, wa_cve_vbar_cortex_a78c
199	msr	vbar_el3, x0
200#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
201
202	isb
203	ret	x19
204endfunc cortex_a78c_reset_func
205
206	/* ----------------------------------------------------
207	 * HW will do the cache maintenance while powering down
208	 * ----------------------------------------------------
209	 */
210func cortex_a78c_core_pwr_dwn
211	/* ---------------------------------------------------
212	 * Enable CPU power down bit in power control register
213	 * ---------------------------------------------------
214	 */
215	mrs	x0, CORTEX_A78C_CPUPWRCTLR_EL1
216	orr	x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
217	msr	CORTEX_A78C_CPUPWRCTLR_EL1, x0
218	isb
219	ret
220endfunc cortex_a78c_core_pwr_dwn
221
222#if REPORT_ERRATA
223/*
224 * Errata printing function for Cortex A78C. Must follow AAPCS.
225 */
226func cortex_a78c_errata_report
227	stp	x8, x30, [sp, #-16]!
228
229	bl	cpu_get_rev_var
230	mov	x8, x0
231
232	/*
233	 * Report all errata. The revision-variant information is passed to
234	 * checking functions of each errata.
235	 */
236	report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064
237	report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
238	report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
239	report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
240	report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
241
242	ldp	x8, x30, [sp], #16
243        ret
244endfunc cortex_a78c_errata_report
245#endif
246
247	/* ---------------------------------------------
248	 * This function provides cortex_a78c specific
249	 * register information for crash reporting.
250	 * It needs to return with x6 pointing to
251	 * a list of register names in ascii and
252	 * x8 - x15 having values of registers to be
253	 * reported.
254	 * ---------------------------------------------
255	 */
256.section .rodata.cortex_a78c_regs, "aS"
257cortex_a78c_regs:  /* The ascii list of register names to be reported */
258	.asciz	"cpuectlr_el1", ""
259
260func cortex_a78c_cpu_reg_dump
261	adr	x6, cortex_a78c_regs
262	mrs	x8, CORTEX_A78C_CPUECTLR_EL1
263	ret
264endfunc cortex_a78c_cpu_reg_dump
265
266declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \
267	cortex_a78c_reset_func, \
268	cortex_a78c_core_pwr_dwn
269