1 /*
2 * Copyright 2020-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <lib/mmio.h>
8
9 #include <imx8m_csu.h>
10
imx_csu_init(const struct imx_csu_cfg * csu_cfg)11 void imx_csu_init(const struct imx_csu_cfg *csu_cfg)
12 {
13 const struct imx_csu_cfg *csu = csu_cfg;
14 uint32_t val;
15
16 while (csu->type != CSU_INVALID) {
17 switch (csu->type) {
18 case CSU_CSL:
19 val = mmio_read_32(CSLx_REG(csu->idx));
20 if (val & CSLx_LOCK(csu->idx)) {
21 break;
22 }
23 mmio_clrsetbits_32(CSLx_REG(csu->idx), CSLx_CFG(0xff, csu->idx),
24 CSLx_CFG(csu->csl_level | (csu->lock << 8), csu->idx));
25 break;
26 case CSU_HP:
27 val = mmio_read_32(CSU_HP_REG(csu->idx));
28 if (val & CSU_HP_LOCK(csu->idx)) {
29 break;
30 }
31 mmio_clrsetbits_32(CSU_HP_REG(csu->idx), CSU_HP_CFG(0x1, csu->idx),
32 CSU_HP_CFG(csu->hp | (csu->lock << 0x1), csu->idx));
33 break;
34 case CSU_SA:
35 val = mmio_read_32(CSU_SA_REG(csu->idx));
36 if (val & CSU_SA_LOCK(csu->idx)) {
37 break;
38 }
39 mmio_clrsetbits_32(CSU_SA_REG(csu->idx), CSU_SA_CFG(0x1, csu->idx),
40 CSU_SA_CFG(csu->sa | (csu->lock << 0x1), csu->idx));
41 break;
42 case CSU_HPCONTROL:
43 val = mmio_read_32(CSU_HPCONTROL_REG(csu->idx));
44 if (val & CSU_HPCONTROL_LOCK(csu->idx)) {
45 break;
46 }
47 mmio_clrsetbits_32(CSU_HPCONTROL_REG(csu->idx), CSU_HPCONTROL_CFG(0x1, csu->idx),
48 CSU_HPCONTROL_CFG(csu->hpctrl | (csu->lock << 0x1), csu->idx));
49 break;
50 default:
51 break;
52 }
53
54 csu++;
55 }
56 }
57