1 /*
2 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9
10 #include <platform_def.h>
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <context.h>
16 #include <drivers/arm/tzc380.h>
17 #include <drivers/console.h>
18 #include <drivers/generic_delay_timer.h>
19 #include <lib/el3_runtime/context_mgmt.h>
20 #include <lib/mmio.h>
21 #include <lib/xlat_tables/xlat_tables_v2.h>
22 #include <plat/common/platform.h>
23
24 #include <dram.h>
25 #include <gpc.h>
26 #include <imx_aipstz.h>
27 #include <imx_uart.h>
28 #include <imx_rdc.h>
29 #include <imx8m_caam.h>
30 #include <imx8m_csu.h>
31 #include <plat_imx8.h>
32
33 #define TRUSTY_PARAMS_LEN_BYTES (4096*2)
34
35 /*
36 * Note: DRAM region is mapped with entire size available and uses MT_RW
37 * attributes.
38 * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section
39 * for explanation of this mapping scheme.
40 */
41 static const mmap_region_t imx_mmap[] = {
42 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW),
43 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
44 MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */
45 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */
46 MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */
47 MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */
48 MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */
49 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM code */
50 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), /* DRAM */
51 {0},
52 };
53
54 static const struct aipstz_cfg aipstz[] = {
55 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
56 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
57 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
58 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
59 {0},
60 };
61
62 static const struct imx_rdc_cfg rdc[] = {
63 /* Master domain assignment */
64 RDC_MDAn(RDC_MDA_M4, DID1),
65
66 /* peripherals domain permission */
67 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
68 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
69
70 /* memory region */
71
72 /* Sentinel */
73 {0},
74 };
75
76 static const struct imx_csu_cfg csu_cfg[] = {
77 /* peripherals csl setting */
78 CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED),
79
80 /* master HP0~1 */
81
82 /* SA setting */
83
84 /* HP control setting */
85
86 /* Sentinel */
87 {0}
88 };
89
90 static entry_point_info_t bl32_image_ep_info;
91 static entry_point_info_t bl33_image_ep_info;
92
93 /* get SPSR for BL33 entry */
get_spsr_for_bl33_entry(void)94 static uint32_t get_spsr_for_bl33_entry(void)
95 {
96 unsigned long el_status;
97 unsigned long mode;
98 uint32_t spsr;
99
100 /* figure out what mode we enter the non-secure world */
101 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
102 el_status &= ID_AA64PFR0_ELX_MASK;
103
104 mode = (el_status) ? MODE_EL2 : MODE_EL1;
105
106 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
107 return spsr;
108 }
109
bl31_tzc380_setup(void)110 void bl31_tzc380_setup(void)
111 {
112 unsigned int val;
113
114 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
115 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
116 return;
117
118 tzc380_init(IMX_TZASC_BASE);
119
120 /*
121 * Need to substact offset 0x40000000 from CPU address when
122 * programming tzasc region for i.mx8mm.
123 */
124
125 /* Enable 1G-5G S/NS RW */
126 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
127 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
128 }
129
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)130 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
131 u_register_t arg2, u_register_t arg3)
132 {
133 static console_t console;
134 int i;
135
136 /* Enable CSU NS access permission */
137 for (i = 0; i < 64; i++) {
138 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
139 }
140
141 imx_aipstz_init(aipstz);
142
143 imx_rdc_init(rdc);
144
145 imx_csu_init(csu_cfg);
146
147 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
148 IMX_CONSOLE_BAUDRATE, &console);
149 /* This console is only used for boot stage */
150 console_set_scope(&console, CONSOLE_FLAG_BOOT);
151
152 imx8m_caam_init();
153
154 /*
155 * tell BL3-1 where the non-secure software image is located
156 * and the entry state information.
157 */
158 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
159 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
160 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
161
162 #if defined(SPD_opteed) || defined(SPD_trusty)
163 /* Populate entry point information for BL32 */
164 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
165 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
166 bl32_image_ep_info.pc = BL32_BASE;
167 bl32_image_ep_info.spsr = 0;
168
169 /* Pass TEE base and size to bl33 */
170 bl33_image_ep_info.args.arg1 = BL32_BASE;
171 bl33_image_ep_info.args.arg2 = BL32_SIZE;
172
173 #ifdef SPD_trusty
174 bl32_image_ep_info.args.arg0 = BL32_SIZE;
175 bl32_image_ep_info.args.arg1 = BL32_BASE;
176 #else
177 /* Make sure memory is clean */
178 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
179 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
180 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
181 #endif
182 #endif
183
184 bl31_tzc380_setup();
185 }
186
187 #define MAP_BL31_TOTAL \
188 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE)
189 #define MAP_BL31_RO \
190 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE)
191 #define MAP_COHERENT_MEM \
192 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
193 MT_DEVICE | MT_RW | MT_SECURE)
194 #define MAP_BL32_TOTAL \
195 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW)
196
bl31_plat_arch_setup(void)197 void bl31_plat_arch_setup(void)
198 {
199 const mmap_region_t bl_regions[] = {
200 MAP_BL31_TOTAL,
201 MAP_BL31_RO,
202 #if USE_COHERENT_MEM
203 MAP_COHERENT_MEM,
204 #endif
205 /* Map TEE memory */
206 MAP_BL32_TOTAL,
207 {0}
208 };
209
210 setup_page_tables(bl_regions, imx_mmap);
211 enable_mmu_el3(0);
212 }
213
bl31_platform_setup(void)214 void bl31_platform_setup(void)
215 {
216 generic_delay_timer_init();
217
218 /* select the CKIL source to 32K OSC */
219 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
220
221 /* Init the dram info */
222 dram_info_init(SAVED_DRAM_TIMING_BASE);
223
224 plat_gic_driver_init();
225 plat_gic_init();
226
227 imx_gpc_init();
228 }
229
bl31_plat_get_next_image_ep_info(unsigned int type)230 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
231 {
232 if (type == NON_SECURE)
233 return &bl33_image_ep_info;
234 if (type == SECURE)
235 return &bl32_image_ep_info;
236
237 return NULL;
238 }
239
plat_get_syscnt_freq2(void)240 unsigned int plat_get_syscnt_freq2(void)
241 {
242 return COUNTER_FREQUENCY;
243 }
244
245 #ifdef SPD_trusty
plat_trusty_set_boot_args(aapcs64_params_t * args)246 void plat_trusty_set_boot_args(aapcs64_params_t *args)
247 {
248 args->arg0 = BL32_SIZE;
249 args->arg1 = BL32_BASE;
250 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
251 }
252 #endif
253