1 /*
2 * Copyright 2020-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9
10 #include <arch_helpers.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <context.h>
14 #include <drivers/arm/tzc380.h>
15 #include <drivers/console.h>
16 #include <drivers/generic_delay_timer.h>
17 #include <lib/el3_runtime/context_mgmt.h>
18 #include <lib/mmio.h>
19 #include <lib/xlat_tables/xlat_tables_v2.h>
20 #include <plat/common/platform.h>
21
22 #include <dram.h>
23 #include <gpc.h>
24 #include <imx_aipstz.h>
25 #include <imx_uart.h>
26 #include <imx_rdc.h>
27 #include <imx8m_caam.h>
28 #include <imx8m_csu.h>
29 #include <platform_def.h>
30 #include <plat_imx8.h>
31
32 #define TRUSTY_PARAMS_LEN_BYTES (4096*2)
33
34 static const mmap_region_t imx_mmap[] = {
35 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP,
36 NOC_MAP, CAAM_RAM_MAP, NS_OCRAM_MAP,
37 ROM_MAP, DRAM_MAP,
38 {0},
39 };
40
41 static const struct aipstz_cfg aipstz[] = {
42 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
43 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
44 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
45 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
46 {0},
47 };
48
49 static const struct imx_rdc_cfg rdc[] = {
50 /* Master domain assignment */
51 RDC_MDAn(RDC_MDA_M7, DID1),
52
53 /* peripherals domain permission */
54 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
55
56 /* memory region */
57
58 /* Sentinel */
59 {0},
60 };
61
62 static const struct imx_csu_cfg csu_cfg[] = {
63 /* peripherals csl setting */
64 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED),
65 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED),
66
67 /* master HP0~1 */
68
69 /* SA setting */
70
71 /* HP control setting */
72
73 /* Sentinel */
74 {0}
75 };
76
77 static entry_point_info_t bl32_image_ep_info;
78 static entry_point_info_t bl33_image_ep_info;
79
80 /* get SPSR for BL33 entry */
get_spsr_for_bl33_entry(void)81 static uint32_t get_spsr_for_bl33_entry(void)
82 {
83 unsigned long el_status;
84 unsigned long mode;
85 uint32_t spsr;
86
87 /* figure out what mode we enter the non-secure world */
88 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
89 el_status &= ID_AA64PFR0_ELX_MASK;
90
91 mode = (el_status) ? MODE_EL2 : MODE_EL1;
92
93 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
94 return spsr;
95 }
96
bl31_tzc380_setup(void)97 static void bl31_tzc380_setup(void)
98 {
99 unsigned int val;
100
101 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
102 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
103 return;
104
105 tzc380_init(IMX_TZASC_BASE);
106
107 /*
108 * Need to substact offset 0x40000000 from CPU address when
109 * programming tzasc region for i.mx8mp.
110 */
111
112 /* Enable 1G-5G S/NS RW */
113 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
114 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
115 }
116
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)117 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
118 u_register_t arg2, u_register_t arg3)
119 {
120 static console_t console;
121 unsigned int val;
122 unsigned int i;
123
124 /* Enable CSU NS access permission */
125 for (i = 0; i < 64; i++) {
126 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
127 }
128
129 imx_aipstz_init(aipstz);
130
131 imx_rdc_init(rdc);
132
133 imx_csu_init(csu_cfg);
134
135 /* config the ocram memory range for secure access */
136 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1);
137 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
138 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
139
140 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
141 IMX_CONSOLE_BAUDRATE, &console);
142 /* This console is only used for boot stage */
143 console_set_scope(&console, CONSOLE_FLAG_BOOT);
144
145 imx8m_caam_init();
146
147 /*
148 * tell BL3-1 where the non-secure software image is located
149 * and the entry state information.
150 */
151 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
152 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
153 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
154
155 #if defined(SPD_opteed) || defined(SPD_trusty)
156 /* Populate entry point information for BL32 */
157 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
158 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
159 bl32_image_ep_info.pc = BL32_BASE;
160 bl32_image_ep_info.spsr = 0;
161
162 /* Pass TEE base and size to bl33 */
163 bl33_image_ep_info.args.arg1 = BL32_BASE;
164 bl33_image_ep_info.args.arg2 = BL32_SIZE;
165
166 #ifdef SPD_trusty
167 bl32_image_ep_info.args.arg0 = BL32_SIZE;
168 bl32_image_ep_info.args.arg1 = BL32_BASE;
169 #else
170 /* Make sure memory is clean */
171 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
172 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
173 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
174 #endif
175 #endif
176
177 bl31_tzc380_setup();
178 }
179
180 #define MAP_BL31_TOTAL \
181 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE)
182 #define MAP_BL31_RO \
183 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE)
184 #define MAP_COHERENT_MEM \
185 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
186 MT_DEVICE | MT_RW | MT_SECURE)
187 #define MAP_BL32_TOTAL \
188 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW)
189
bl31_plat_arch_setup(void)190 void bl31_plat_arch_setup(void)
191 {
192 const mmap_region_t bl_regions[] = {
193 MAP_BL31_TOTAL,
194 MAP_BL31_RO,
195 #if USE_COHERENT_MEM
196 MAP_COHERENT_MEM,
197 #endif
198 /* Map TEE memory */
199 MAP_BL32_TOTAL,
200 {0}
201 };
202
203 setup_page_tables(bl_regions, imx_mmap);
204 enable_mmu_el3(0);
205 }
206
bl31_platform_setup(void)207 void bl31_platform_setup(void)
208 {
209 generic_delay_timer_init();
210
211 /* select the CKIL source to 32K OSC */
212 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
213
214 /* Init the dram info */
215 dram_info_init(SAVED_DRAM_TIMING_BASE);
216
217 plat_gic_driver_init();
218 plat_gic_init();
219
220 imx_gpc_init();
221 }
222
bl31_plat_get_next_image_ep_info(unsigned int type)223 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
224 {
225 if (type == NON_SECURE) {
226 return &bl33_image_ep_info;
227 }
228
229 if (type == SECURE) {
230 return &bl32_image_ep_info;
231 }
232
233 return NULL;
234 }
235
plat_get_syscnt_freq2(void)236 unsigned int plat_get_syscnt_freq2(void)
237 {
238 return COUNTER_FREQUENCY;
239 }
240
241 #ifdef SPD_trusty
plat_trusty_set_boot_args(aapcs64_params_t * args)242 void plat_trusty_set_boot_args(aapcs64_params_t *args)
243 {
244 args->arg0 = BL32_SIZE;
245 args->arg1 = BL32_BASE;
246 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
247 }
248 #endif
249