1 /* 2 * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLAT_SOCFPGA_DEF_H 9 #define PLAT_SOCFPGA_DEF_H 10 11 #include <platform_def.h> 12 13 /* Platform Setting */ 14 #define PLATFORM_MODEL PLAT_SOCFPGA_N5X 15 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 16 17 /* FPGA config helpers */ 18 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 19 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 20 21 /* Register Mapping */ 22 #define SOCFPGA_CCU_NOC_REG_BASE U(0xf7000000) 23 #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) 24 25 #define SOCFPGA_MMC_REG_BASE U(0xff808000) 26 27 #define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000) 28 #define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000) 29 30 #define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000) 31 #define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100) 32 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200) 33 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300) 34 35 /* Platform specific system counter */ 36 /* 37 * In N5X the clk init is done in Uboot SPL. 38 * BL31 shall bypass the clk init and only provides other APIs. 39 */ 40 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400) 41 42 #endif /* PLAT_SOCFPGA_DEF_H */ 43