1 /*
2  * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
3  * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #include <arch.h>
9 #include <arch_helpers.h>
10 #include <assert.h>
11 #include <common/bl_common.h>
12 #include <drivers/arm/gicv2.h>
13 #include <drivers/ti/uart/uart_16550.h>
14 #include <lib/xlat_tables/xlat_tables.h>
15 #include <lib/mmio.h>
16 #include <plat/common/platform.h>
17 #include <platform_def.h>
18 
19 #include "socfpga_mailbox.h"
20 #include "socfpga_noc.h"
21 #include "socfpga_private.h"
22 #include "socfpga_reset_manager.h"
23 #include "socfpga_system_manager.h"
24 #include "s10_memory_controller.h"
25 #include "s10_pinmux.h"
26 #include "s10_clock_manager.h"
27 
28 
29 static entry_point_info_t bl32_image_ep_info;
30 static entry_point_info_t bl33_image_ep_info;
31 
bl31_plat_get_next_image_ep_info(uint32_t type)32 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
33 {
34 	entry_point_info_t *next_image_info;
35 
36 	next_image_info = (type == NON_SECURE) ?
37 			  &bl33_image_ep_info : &bl32_image_ep_info;
38 
39 	/* None of the images on this platform can have 0x0 as the entrypoint */
40 	if (next_image_info->pc)
41 		return next_image_info;
42 	else
43 		return NULL;
44 }
45 
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)46 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
47 				u_register_t arg2, u_register_t arg3)
48 {
49 	static console_t console;
50 
51 	mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
52 
53 	console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
54 		PLAT_BAUDRATE, &console);
55 	/*
56 	 * Check params passed from BL31 should not be NULL,
57 	 */
58 	void *from_bl2 = (void *) arg0;
59 
60 	bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
61 	assert(params_from_bl2 != NULL);
62 
63 	/*
64 	 * Copy BL32 (if populated by BL31) and BL33 entry point information.
65 	 * They are stored in Secure RAM, in BL31's address space.
66 	 */
67 
68 	if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
69 		params_from_bl2->h.version >= VERSION_2) {
70 
71 		bl_params_node_t *bl_params = params_from_bl2->head;
72 
73 		while (bl_params) {
74 			if (bl_params->image_id == BL33_IMAGE_ID)
75 				bl33_image_ep_info = *bl_params->ep_info;
76 
77 			bl_params = bl_params->next_params_info;
78 		}
79 	} else {
80 		struct socfpga_bl31_params *arg_from_bl2 =
81 			(struct socfpga_bl31_params *) from_bl2;
82 
83 		assert(arg_from_bl2->h.type == PARAM_BL31);
84 		assert(arg_from_bl2->h.version >= VERSION_1);
85 
86 		bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
87 		bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
88 	}
89 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
90 }
91 
92 static const interrupt_prop_t s10_interrupt_props[] = {
93 	PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
94 	PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
95 };
96 
97 static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
98 
99 static const gicv2_driver_data_t plat_gicv2_gic_data = {
100 	.gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
101 	.gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
102 	.interrupt_props = s10_interrupt_props,
103 	.interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
104 	.target_masks = target_mask_array,
105 	.target_masks_num = ARRAY_SIZE(target_mask_array),
106 };
107 
108 /*******************************************************************************
109  * Perform any BL3-1 platform setup code
110  ******************************************************************************/
bl31_platform_setup(void)111 void bl31_platform_setup(void)
112 {
113 	socfpga_delay_timer_init();
114 
115 	/* Initialize the gic cpu and distributor interfaces */
116 	gicv2_driver_init(&plat_gicv2_gic_data);
117 	gicv2_distif_init();
118 	gicv2_pcpu_distif_init();
119 	gicv2_cpuif_enable();
120 
121 	/* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
122 	mmio_write_64(PLAT_CPU_RELEASE_ADDR,
123 		(uint64_t)plat_secondary_cpus_bl31_entry);
124 
125 	mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
126 
127 	enable_ocram_firewall();
128 }
129 
130 const mmap_region_t plat_stratix10_mmap[] = {
131 	MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
132 		MT_MEMORY | MT_RW | MT_NS),
133 	MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
134 		MT_DEVICE | MT_RW | MT_NS),
135 	MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
136 		MT_DEVICE | MT_RW | MT_SECURE),
137 	MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
138 		MT_NON_CACHEABLE | MT_RW | MT_SECURE),
139 	MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
140 		MT_DEVICE | MT_RW | MT_SECURE),
141 	MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
142 		MT_DEVICE | MT_RW | MT_NS),
143 	MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
144 		MT_DEVICE | MT_RW | MT_NS),
145 	{0}
146 };
147 
148 /*******************************************************************************
149  * Perform the very early platform specific architectural setup here. At the
150  * moment this is only intializes the mmu in a quick and dirty way.
151  ******************************************************************************/
bl31_plat_arch_setup(void)152 void bl31_plat_arch_setup(void)
153 {
154 	const mmap_region_t bl_regions[] = {
155 		MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
156 			MT_MEMORY | MT_RW | MT_SECURE),
157 		MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
158 			MT_CODE | MT_SECURE),
159 		MAP_REGION_FLAT(BL_RO_DATA_BASE,
160 			BL_RO_DATA_END - BL_RO_DATA_BASE,
161 			MT_RO_DATA | MT_SECURE),
162 #if USE_COHERENT_MEM
163 		MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
164 			BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
165 			MT_DEVICE | MT_RW | MT_SECURE),
166 #endif
167 		{0}
168 	};
169 
170 	setup_page_tables(bl_regions, plat_stratix10_mmap);
171 	enable_mmu_el3(0);
172 }
173 
174