1 /*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 #include <drivers/delay_timer.h>
9 #include <lib/mmio.h>
10
11 #include <armada_common.h>
12
13 /*
14 * If bootrom is currently at BLE there's no need to include the memory
15 * maps structure at this point
16 */
17 #include <mvebu_def.h>
18 #ifndef IMAGE_BLE
19
20 /*****************************************************************************
21 * GPIO Configuration
22 *****************************************************************************
23 */
24 #define MPP_CONTROL_REGISTER 0xf2440018
25 #define MPP_CONTROL_MPP_SEL_52_MASK 0xf0000
26 #define GPIO_DATA_OUT1_REGISTER 0xf2440140
27 #define GPIO_DATA_OUT_EN_CTRL1_REGISTER 0xf2440144
28 #define GPIO52_MASK 0x100000
29
30 /* Reset PCIe via GPIO number 52 */
marvell_gpio_config(void)31 int marvell_gpio_config(void)
32 {
33 uint32_t reg;
34
35 reg = mmio_read_32(MPP_CONTROL_REGISTER);
36 reg |= MPP_CONTROL_MPP_SEL_52_MASK;
37 mmio_write_32(MPP_CONTROL_REGISTER, reg);
38
39 reg = mmio_read_32(GPIO_DATA_OUT1_REGISTER);
40 reg |= GPIO52_MASK;
41 mmio_write_32(GPIO_DATA_OUT1_REGISTER, reg);
42
43 reg = mmio_read_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER);
44 reg &= ~GPIO52_MASK;
45 mmio_write_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER, reg);
46 udelay(100);
47
48 return 0;
49 }
50
51 /*****************************************************************************
52 * AMB Configuration
53 *****************************************************************************
54 */
55 struct addr_map_win amb_memory_map[] = {
56 /* CP1 SPI1 CS0 Direct Mode access */
57 {0xf900, 0x1000000, AMB_SPI1_CS0_ID},
58 };
59
marvell_get_amb_memory_map(struct addr_map_win ** win,uint32_t * size,uintptr_t base)60 int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
61 uintptr_t base)
62 {
63 *win = amb_memory_map;
64 if (*win == NULL)
65 *size = 0;
66 else
67 *size = ARRAY_SIZE(amb_memory_map);
68
69 return 0;
70 }
71 #endif
72
73 /*****************************************************************************
74 * IO WIN Configuration
75 *****************************************************************************
76 */
77 struct addr_map_win io_win_memory_map[] = {
78 /* CP1 (MCI0) internal regs */
79 {0x00000000f4000000, 0x2000000, MCI_0_TID},
80 #ifndef IMAGE_BLE
81 /* PCIe0-2 and SPI1_CS0 (RUNIT) on CP1*/
82 {0x00000000f9000000, 0x4000000, MCI_0_TID},
83 /* MCI 0 indirect window */
84 {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
85 /* MCI 1 indirect window */
86 {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
87 #endif
88 };
89
marvell_get_io_win_gcr_target(int ap_index)90 uint32_t marvell_get_io_win_gcr_target(int ap_index)
91 {
92 return PIDI_TID;
93 }
94
marvell_get_io_win_memory_map(int ap_index,struct addr_map_win ** win,uint32_t * size)95 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
96 uint32_t *size)
97 {
98 *win = io_win_memory_map;
99 if (*win == NULL)
100 *size = 0;
101 else
102 *size = ARRAY_SIZE(io_win_memory_map);
103
104 return 0;
105 }
106
107 #ifndef IMAGE_BLE
108 /*****************************************************************************
109 * IOB Configuration
110 *****************************************************************************
111 */
112 struct addr_map_win iob_memory_map_cp0[] = {
113 /* CP0 */
114 /* PEX1_X1 window */
115 {0x00000000f7000000, 0x1000000, PEX1_TID},
116 /* PEX2_X1 window */
117 {0x00000000f8000000, 0x1000000, PEX2_TID},
118 /* PEX0_X4 window */
119 {0x00000000f6000000, 0x1000000, PEX0_TID},
120 {0x00000000c0000000, 0x30000000, PEX0_TID},
121 {0x0000000800000000, 0x100000000, PEX0_TID},
122 };
123
124 struct addr_map_win iob_memory_map_cp1[] = {
125 /* CP1 */
126 /* SPI1_CS0 (RUNIT) window */
127 {0x00000000f9000000, 0x1000000, RUNIT_TID},
128 /* PEX1_X1 window */
129 {0x00000000fb000000, 0x1000000, PEX1_TID},
130 /* PEX2_X1 window */
131 {0x00000000fc000000, 0x1000000, PEX2_TID},
132 /* PEX0_X4 window */
133 {0x00000000fa000000, 0x1000000, PEX0_TID}
134 };
135
marvell_get_iob_memory_map(struct addr_map_win ** win,uint32_t * size,uintptr_t base)136 int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
137 uintptr_t base)
138 {
139 switch (base) {
140 case MVEBU_CP_REGS_BASE(0):
141 *win = iob_memory_map_cp0;
142 *size = ARRAY_SIZE(iob_memory_map_cp0);
143 return 0;
144 case MVEBU_CP_REGS_BASE(1):
145 *win = iob_memory_map_cp1;
146 *size = ARRAY_SIZE(iob_memory_map_cp1);
147 return 0;
148 default:
149 *size = 0;
150 *win = 0;
151 return 1;
152 }
153 }
154 #endif
155
156 /*****************************************************************************
157 * CCU Configuration
158 *****************************************************************************
159 */
160 struct addr_map_win ccu_memory_map[] = {
161 #ifdef IMAGE_BLE
162 {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
163 #else
164 #if LLC_SRAM
165 /* This entry is prepared for OP-TEE OS that enables the LLC SRAM
166 * and changes the window target to SRAM_TID.
167 */
168 {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
169 #endif
170 {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
171 {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
172 {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
173 #endif
174 };
175
marvell_get_ccu_gcr_target(int ap)176 uint32_t marvell_get_ccu_gcr_target(int ap)
177 {
178 return DRAM_0_TID;
179 }
180
marvell_get_ccu_memory_map(int ap_index,struct addr_map_win ** win,uint32_t * size)181 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
182 uint32_t *size)
183 {
184 *win = ccu_memory_map;
185 *size = ARRAY_SIZE(ccu_memory_map);
186
187 return 0;
188 }
189
190 /* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
191
192 /*****************************************************************************
193 * SKIP IMAGE Configuration
194 *****************************************************************************
195 */
plat_marvell_get_skip_image_data(void)196 void *plat_marvell_get_skip_image_data(void)
197 {
198 /* No recovery button on A8k-MCBIN board */
199 return NULL;
200 }
201