1 /*
2 * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #include <arch_helpers.h>
7 #include <common/debug.h>
8 #include <lib/mmio.h>
9 #include <dfd.h>
10 #include <plat_dfd.h>
11
12 static uint64_t dfd_cache_dump;
13 static bool dfd_enabled;
14 static uint64_t dfd_base_addr;
15 static uint64_t dfd_chain_length;
16
dfd_setup(uint64_t base_addr,uint64_t chain_length,uint64_t cache_dump)17 void dfd_setup(uint64_t base_addr, uint64_t chain_length, uint64_t cache_dump)
18 {
19 mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL);
20 mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL);
21 mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL);
22
23 mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, BIT(2));
24 mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1);
25 sync_writel(DFD_INTERNAL_CTL, 0x5);
26 mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13));
27 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3);
28 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9);
29 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19);
30
31 mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB);
32 mmio_write_32(DFD_CHAIN_LENGTH0, chain_length);
33 mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0);
34 mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1);
35
36 mmio_write_32(DFD_TEST_SI_0, 0x0);
37 mmio_write_32(DFD_TEST_SI_1, 0x0);
38 mmio_write_32(DFD_TEST_SI_2, 0x0);
39 mmio_write_32(DFD_TEST_SI_3, 0x0);
40
41 sync_writel(DFD_POWER_CTL, 0xF9);
42 sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL);
43 sync_writel(DFD_V30_CTL, 0xD);
44
45 mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24);
46 mmio_write_32(DFD_O_REG_0, 0);
47
48 /* setup global variables for suspend and resume */
49 dfd_enabled = true;
50 dfd_base_addr = base_addr;
51 dfd_chain_length = chain_length;
52 dfd_cache_dump = cache_dump;
53
54 if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) {
55 mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_CACHE_VAL);
56 sync_writel(DFD_V35_ENABLE, 0x1);
57 sync_writel(DFD_V35_TAP_NUMBER, 0xB);
58 sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL);
59 sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL);
60
61 /* Cache dump only mode */
62 sync_writel(DFD_V35_CTL, 0x1);
63 mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 0xF);
64 mmio_write_32(DFD_CHAIN_LENGTH0, DFD_CHAIN_LENGTH_VAL);
65 mmio_write_32(DFD_CHAIN_LENGTH1, DFD_CHAIN_LENGTH_VAL);
66 mmio_write_32(DFD_CHAIN_LENGTH2, DFD_CHAIN_LENGTH_VAL);
67 mmio_write_32(DFD_CHAIN_LENGTH3, DFD_CHAIN_LENGTH_VAL);
68
69 if ((cache_dump & DFD_PARITY_ERR_TRIGGER) != 0UL) {
70 sync_writel(DFD_HW_TRIGGER_MASK, 0xC);
71 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4);
72 }
73 }
74 dsbsy();
75 }
76
dfd_resume(void)77 void dfd_resume(void)
78 {
79 if (dfd_enabled == true) {
80 dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump);
81 }
82 }
83