1 /* 2 * Copyright (c) 2022, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_DEF_H 8 #define ARCH_DEF_H 9 10 /* Topology constants */ 11 #define PLAT_MAX_PWR_LVL (2) 12 #define PLAT_MAX_RET_STATE (1) 13 #define PLAT_MAX_OFF_STATE (2) 14 15 #define PLATFORM_SYSTEM_COUNT (1) 16 #define PLATFORM_CLUSTER_COUNT (1) 17 #define PLATFORM_CLUSTER0_CORE_COUNT (8) 18 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 19 #define PLATFORM_MAX_CPUS_PER_CLUSTER (8) 20 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 21 PLATFORM_CLUSTER_COUNT + \ 22 PLATFORM_CORE_COUNT) 23 24 /******************************************************************************* 25 * Declarations and constants to access the mailboxes safely. Each mailbox is 26 * aligned on the biggest cache line size in the platform. This is known only 27 * to the platform as it might have a combination of integrated and external 28 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 29 * line at any cache level. They could belong to different cpus/clusters & 30 * get written while being protected by different locks causing corruption of 31 * a valid mailbox address. 32 ******************************************************************************/ 33 /* Cachline size */ 34 #define CACHE_WRITEBACK_SHIFT (6) 35 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 36 37 #endif /* ARCH_DEF_H */ 38 39