1 /*
2  * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef RTC_H
8 #define RTC_H
9 
10 #define PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK	(1U)
11 #define PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT	(1U)
12 #define PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK	(1U)
13 #define PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT	(3U)
14 #define PMIC_RG_RTC_EOSC32_CK_PDN_MASK		(1U)
15 #define PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT		(2U)
16 #define PMIC_RG_EOSC_CALI_TD_MASK		(7U)
17 #define PMIC_RG_EOSC_CALI_TD_SHIFT		(5U)
18 #define PMIC_RG_XO_EN32K_MAN_MASK		(1U)
19 #define PMIC_RG_XO_EN32K_MAN_SHIFT		(0U)
20 
21 /* RTC registers */
22 enum {
23 	RTC_BBPU = 0x0588,
24 	RTC_IRQ_STA = 0x058A,
25 	RTC_IRQ_EN = 0x058C,
26 	RTC_CII_EN = 0x058E
27 };
28 
29 enum {
30 	RTC_AL_SEC = 0x05A0,
31 	RTC_AL_MIN = 0x05A2,
32 	RTC_AL_HOU = 0x05A4,
33 	RTC_AL_DOM = 0x05A6,
34 	RTC_AL_DOW = 0x05A8,
35 	RTC_AL_MTH = 0x05AA,
36 	RTC_AL_YEA = 0x05AC,
37 	RTC_AL_MASK = 0x0590
38 };
39 
40 enum {
41 	RTC_OSC32CON = 0x05AE,
42 	RTC_CON = 0x05C4,
43 	RTC_WRTGR = 0x05C2
44 };
45 
46 enum {
47 	RTC_PDN1 = 0x05B4,
48 	RTC_PDN2 = 0x05B6,
49 	RTC_SPAR0 = 0x05B8,
50 	RTC_SPAR1 = 0x05BA,
51 	RTC_PROT = 0x05BC,
52 	RTC_DIFF = 0x05BE,
53 	RTC_CALI = 0x05C0
54 };
55 
56 enum {
57 	RTC_OSC32CON_UNLOCK1 = 0x1A57,
58 	RTC_OSC32CON_UNLOCK2 = 0x2B68
59 };
60 
61 enum {
62 	RTC_PROT_UNLOCK1 = 0x586A,
63 	RTC_PROT_UNLOCK2 = 0x9136
64 };
65 
66 enum {
67 	RTC_BBPU_PWREN	= 1U << 0,
68 	RTC_BBPU_CLR	= 1U << 1,
69 	RTC_BBPU_INIT	= 1U << 2,
70 	RTC_BBPU_AUTO	= 1U << 3,
71 	RTC_BBPU_CLRPKY	= 1U << 4,
72 	RTC_BBPU_RELOAD	= 1U << 5,
73 	RTC_BBPU_CBUSY	= 1U << 6
74 };
75 
76 enum {
77 	RTC_AL_MASK_SEC = 1U << 0,
78 	RTC_AL_MASK_MIN = 1U << 1,
79 	RTC_AL_MASK_HOU = 1U << 2,
80 	RTC_AL_MASK_DOM = 1U << 3,
81 	RTC_AL_MASK_DOW = 1U << 4,
82 	RTC_AL_MASK_MTH = 1U << 5,
83 	RTC_AL_MASK_YEA = 1U << 6
84 };
85 
86 enum {
87 	RTC_BBPU_AUTO_PDN_SEL = 1U << 6,
88 	RTC_BBPU_2SEC_CK_SEL = 1U << 7,
89 	RTC_BBPU_2SEC_EN = 1U << 8,
90 	RTC_BBPU_2SEC_MODE = 0x3 << 9,
91 	RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11,
92 	RTC_BBPU_2SEC_STAT_STA = 1U << 12
93 };
94 
95 enum {
96 	RTC_BBPU_KEY	= 0x43 << 8
97 };
98 
99 enum {
100 	RTC_EMBCK_SRC_SEL	= 1 << 8,
101 	RTC_EMBCK_SEL_MODE	= 3 << 6,
102 	RTC_XOSC32_ENB		= 1 << 5,
103 	RTC_REG_XOSC32_ENB	= 1 << 15
104 };
105 
106 enum {
107 	RTC_K_EOSC_RSV_0	= 1 << 8,
108 	RTC_K_EOSC_RSV_1	= 1 << 9,
109 	RTC_K_EOSC_RSV_2	= 1 << 10
110 };
111 
112 /* PMIC TOP Register Definition */
113 enum {
114 	PMIC_RG_TOP_CON = 0x001E,
115 	PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
116 	PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
117 	PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
118 	PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
119 	PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
120 	PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
121 };
122 
123 /* PMIC SCK Register Definition */
124 enum {
125 	PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x051A,
126 	PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x051C,
127 	PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x051E,
128 	PMIC_RG_EOSC_CALI_CON0 = 0x540
129 };
130 
131 /* PMIC DCXO Register Definition */
132 enum {
133 	PMIC_RG_DCXO_CW00 = 0x0788,
134 	PMIC_RG_DCXO_CW02 = 0x0790
135 };
136 
137 /* external API */
138 uint16_t RTC_Read(uint32_t addr);
139 void RTC_Write(uint32_t addr, uint16_t data);
140 int32_t rtc_busy_wait(void);
141 int32_t RTC_Write_Trigger(void);
142 int32_t Writeif_unlock(void);
143 void rtc_power_off_sequence(void);
144 
145 #endif /* RTC_H */
146