1 /*
2  * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef MTSPMC_PRIVATE_H
8 #define MTSPMC_PRIVATE_H
9 
10 #include <lib/utils_def.h>
11 #include <platform_def.h>
12 
13 unsigned long read_cpuectlr(void);
14 void write_cpuectlr(unsigned long cpuectlr);
15 
16 unsigned long read_cpupwrctlr_el1(void);
17 void write_cpupwrctlr_el1(unsigned long cpuectlr);
18 
19 /* per_cpu/cluster helper */
20 struct per_cpu_reg {
21 	unsigned int cluster_addr;
22 	unsigned int cpu_stride;
23 };
24 
25 #define per_cpu(cluster, cpu, reg)	\
26 	(reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride))
27 
28 #define per_cluster(cluster, reg)	(reg[cluster].cluster_addr)
29 
30 #define SPM_REG(ofs)			(uint32_t)(SPM_BASE + (ofs))
31 #define MCUCFG_REG(ofs)			(uint32_t)(MCUCFG_BASE + (ofs))
32 #define INFRACFG_AO_REG(ofs)		(uint32_t)(INFRACFG_AO_BASE + (ofs))
33 
34 /* SPMC related registers */
35 #define SPM_POWERON_CONFIG_EN		SPM_REG(0x000)
36 /* bit-fields of SPM_POWERON_CONFIG_EN */
37 #define PROJECT_CODE			(U(0xb16) << 16)
38 #define BCLK_CG_EN			BIT(0)
39 
40 #define SPM_PWR_STATUS			SPM_REG(0x16c)
41 #define SPM_PWR_STATUS_2ND		SPM_REG(0x170)
42 #define SPM_CPU_PWR_STATUS		SPM_REG(0x174)
43 
44 /* bit-fields of SPM_PWR_STATUS */
45 #define MD				BIT(0)
46 #define CONN				BIT(1)
47 #define DDRPHY				BIT(2)
48 #define DISP				BIT(3)
49 #define MFG				BIT(4)
50 #define ISP				BIT(5)
51 #define INFRA				BIT(6)
52 #define VDEC				BIT(7)
53 #define MP0_CPUTOP			BIT(8)
54 #define MP0_CPU0			BIT(9)
55 #define MP0_CPU1			BIT(10)
56 #define MP0_CPU2			BIT(11)
57 #define MP0_CPU3			BIT(12)
58 #define MCUSYS				BIT(14)
59 #define MP0_CPU4			BIT(15)
60 #define MP0_CPU5			BIT(16)
61 #define MP0_CPU6			BIT(17)
62 #define MP0_CPU7			BIT(18)
63 #define VEN				BIT(21)
64 
65 /* SPMC related registers */
66 #define SPM_MCUSYS_PWR_CON		SPM_REG(0x200)
67 #define SPM_MP0_CPUTOP_PWR_CON		SPM_REG(0x204)
68 #define SPM_MP0_CPU0_PWR_CON		SPM_REG(0x208)
69 #define SPM_MP0_CPU1_PWR_CON		SPM_REG(0x20c)
70 #define SPM_MP0_CPU2_PWR_CON		SPM_REG(0x210)
71 #define SPM_MP0_CPU3_PWR_CON		SPM_REG(0x214)
72 #define SPM_MP0_CPU4_PWR_CON		SPM_REG(0x218)
73 #define SPM_MP0_CPU5_PWR_CON		SPM_REG(0x21c)
74 #define SPM_MP0_CPU6_PWR_CON		SPM_REG(0x220)
75 #define SPM_MP0_CPU7_PWR_CON		SPM_REG(0x224)
76 
77 /* bit-fields of SPM_*_PWR_CON */
78 #define PWR_ON_ACK			BIT(31)
79 #define VPROC_EXT_OFF			BIT(7)
80 #define DORMANT_EN			BIT(6)
81 #define RESETPWRON_CONFIG		BIT(5)
82 #define PWR_CLK_DIS			BIT(4)
83 #define PWR_ON				BIT(2)
84 #define PWR_RST_B			BIT(0)
85 
86 /* per_cpu registers for SPM_MP0_CPU_PWR_CON */
87 static const struct per_cpu_reg SPM_CPU_PWR[] = {
88 	{ .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
89 };
90 
91 /* per_cluster registers for SPM_MP0_CPUTOP_PWR_CON */
92 static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
93 	{ .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
94 };
95 
96 /* MCUCFG related registers */
97 #define MCUCFG_MP0_CLUSTER_CFG5		MCUCFG_REG(0xc8e4)
98 /* reset vectors */
99 #define MCUCFG_MP0_CLUSTER_CFG8		MCUCFG_REG(0xc900)
100 #define MCUCFG_MP0_CLUSTER_CFG10	MCUCFG_REG(0xc908)
101 #define MCUCFG_MP0_CLUSTER_CFG12	MCUCFG_REG(0xc910)
102 #define MCUCFG_MP0_CLUSTER_CFG14	MCUCFG_REG(0xc918)
103 #define MCUCFG_MP0_CLUSTER_CFG16	MCUCFG_REG(0xc920)
104 #define MCUCFG_MP0_CLUSTER_CFG18	MCUCFG_REG(0xc928)
105 #define MCUCFG_MP0_CLUSTER_CFG20	MCUCFG_REG(0xc930)
106 #define MCUCFG_MP0_CLUSTER_CFG22	MCUCFG_REG(0xc938)
107 
108 /* per_cpu registers for MCUCFG_MP0_CLUSTER_CFG */
109 static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
110 	{ .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U }
111 };
112 
113 /* per_cpu registers for MCUCFG_MP0_CLUSTER_CFG5 */
114 static const struct per_cpu_reg MCUCFG_INITARCH[] = {
115 	{ .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
116 };
117 
118 #define MCUCFG_INITARCH_CPU_BIT(cpu)	BIT(16U + cpu)
119 /* CPC control */
120 #define MCUCFG_CPC_FLOW_CTRL_CFG	MCUCFG_REG(0xa814)
121 #define MCUCFG_CPC_SPMC_PWR_STATUS	MCUCFG_REG(0xa840)
122 
123 /* bit-fields of CPC_FLOW_CTRL_CFG */
124 #define CPC_CTRL_ENABLE			BIT(16)
125 #define SSPM_ALL_PWR_CTRL_EN		BIT(13) /* for cpu-hotplug */
126 #define GIC_WAKEUP_IGNORE(cpu)		BIT(21 + cpu)
127 
128 /* bit-fields of CPC_SPMC_PWR_STATUS */
129 #define CORE_SPMC_PWR_ON_ACK		GENMASK(11, 0)
130 
131 /* APB module infracfg_ao */
132 #define INFRA_TOPAXI_PROTECTEN		INFRACFG_AO_REG(0x0220)
133 #define INFRA_TOPAXI_PROTECTEN_STA0	INFRACFG_AO_REG(0x0224)
134 #define INFRA_TOPAXI_PROTECTEN_STA1	INFRACFG_AO_REG(0x0228)
135 #define INFRA_TOPAXI_PROTECTEN_SET	INFRACFG_AO_REG(0x02a0)
136 #define INFRA_TOPAXI_PROTECTEN_CLR	INFRACFG_AO_REG(0x02a4)
137 #define INFRA_TOPAXI_PROTECTEN_1	INFRACFG_AO_REG(0x0250)
138 #define INFRA_TOPAXI_PROTECTEN_STA0_1	INFRACFG_AO_REG(0x0254)
139 #define INFRA_TOPAXI_PROTECTEN_STA1_1	INFRACFG_AO_REG(0x0258)
140 #define INFRA_TOPAXI_PROTECTEN_1_SET	INFRACFG_AO_REG(0x02a8)
141 #define INFRA_TOPAXI_PROTECTEN_1_CLR	INFRACFG_AO_REG(0x02ac)
142 
143 /* bit-fields of INFRA_TOPAXI_PROTECTEN */
144 #define MP0_SPMC_PROT_STEP1_0_MASK	BIT(12)
145 #define MP0_SPMC_PROT_STEP1_1_MASK	(BIT(26) | BIT(12))
146 
147 /* SPARK */
148 #define VOLTAGE_04			U(0x40)
149 #define VOLTAGE_05			U(0x60)
150 
151 #define PTP3_CPU0_SPMC_SW_CFG		MCUCFG_REG(0x200)
152 #define CPU0_ILDO_CONTROL5		MCUCFG_REG(0x334)
153 #define CPU0_ILDO_CONTROL8		MCUCFG_REG(0x340)
154 
155 /* bit-fields of CPU0_ILDO_CONTROL5 */
156 #define ILDO_RET_VOSEL			GENMASK(7, 0)
157 
158 /* bit-fields of PTP3_CPU_SPMC_SW_CFG */
159 #define SW_SPARK_EN			BIT(0)
160 
161 /* bit-fields of CPU0_ILDO_CONTROL8 */
162 #define ILDO_BYPASS_B			BIT(0)
163 
164 static const struct per_cpu_reg MCUCFG_SPARK[] = {
165 	{ .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U }
166 };
167 
168 static const struct per_cpu_reg ILDO_CONTROL5[] = {
169 	{ .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U }
170 };
171 
172 static const struct per_cpu_reg ILDO_CONTROL8[] = {
173 	{ .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U }
174 };
175 
176 #endif /* MTSPMC_PRIVATE_H */
177