1 /* 2 * Copyright (c) 2022, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SPM_REG_H 8 #define SPM_REG_H 9 10 #include <platform_def.h> 11 12 /* Register_SPM_CFG */ 13 #define MD32PCM_CFG_BASE (SPM_BASE + 0xA00) 14 #define POWERON_CONFIG_EN (SPM_BASE + 0x000) 15 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) 16 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) 17 #define SPM_CLK_CON (SPM_BASE + 0x00C) 18 #define SPM_CLK_SETTLE (SPM_BASE + 0x010) 19 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) 20 #define PCM_CON0 (SPM_BASE + 0x018) 21 #define PCM_CON1 (SPM_BASE + 0x01C) 22 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020) 23 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024) 24 #define PCM_REG_DATA_INI (SPM_BASE + 0x028) 25 #define PCM_PWR_IO_EN (SPM_BASE + 0x02C) 26 #define PCM_TIMER_VAL (SPM_BASE + 0x030) 27 #define PCM_WDT_VAL (SPM_BASE + 0x034) 28 #define SPM_SW_RST_CON (SPM_BASE + 0x040) 29 #define SPM_SW_RST_CON_SET (SPM_BASE + 0x044) 30 #define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048) 31 #define SPM_ARBITER_EN (SPM_BASE + 0x050) 32 #define SCPSYS_CLK_CON (SPM_BASE + 0x054) 33 #define SPM_SRAM_RSV_CON (SPM_BASE + 0x058) 34 #define SPM_SWINT (SPM_BASE + 0x05C) 35 #define SPM_SWINT_SET (SPM_BASE + 0x060) 36 #define SPM_SWINT_CLR (SPM_BASE + 0x064) 37 #define SPM_SCP_MAILBOX (SPM_BASE + 0x068) 38 #define SCP_SPM_MAILBOX (SPM_BASE + 0x06C) 39 #define SPM_SCP_IRQ (SPM_BASE + 0x070) 40 #define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x074) 41 #define SPM_IRQ_MASK (SPM_BASE + 0x078) 42 #define SPM_SRC_REQ (SPM_BASE + 0x080) 43 #define SPM_SRC_MASK (SPM_BASE + 0x084) 44 #define SPM_SRC2_MASK (SPM_BASE + 0x088) 45 #define SPM_SRC3_MASK (SPM_BASE + 0x090) 46 #define SPM_SRC4_MASK (SPM_BASE + 0x094) 47 #define SPM_WAKEUP_EVENT_MASK2 (SPM_BASE + 0x098) 48 #define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x09C) 49 #define SPM_WAKEUP_EVENT_SENS (SPM_BASE + 0x0A0) 50 #define SPM_WAKEUP_EVENT_CLEAR (SPM_BASE + 0x0A4) 51 #define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0A8) 52 #define SCP_CLK_CON (SPM_BASE + 0x0AC) 53 #define PCM_DEBUG_CON (SPM_BASE + 0x0B0) 54 #define DDREN_DBC_CON (SPM_BASE + 0x0B4) 55 #define SPM_RESOURCE_ACK_CON0 (SPM_BASE + 0x0B8) 56 #define SPM_RESOURCE_ACK_CON1 (SPM_BASE + 0x0BC) 57 #define SPM_RESOURCE_ACK_CON2 (SPM_BASE + 0x0C0) 58 #define SPM_RESOURCE_ACK_CON3 (SPM_BASE + 0x0C4) 59 #define SPM_RESOURCE_ACK_CON4 (SPM_BASE + 0x0C8) 60 #define SPM_SRAM_CON (SPM_BASE + 0x0CC) 61 #define PCM_REG0_DATA (SPM_BASE + 0x100) 62 #define PCM_REG2_DATA (SPM_BASE + 0x104) 63 #define PCM_REG6_DATA (SPM_BASE + 0x108) 64 #define PCM_REG7_DATA (SPM_BASE + 0x10C) 65 #define PCM_REG13_DATA (SPM_BASE + 0x110) 66 #define SRC_REQ_STA_0 (SPM_BASE + 0x114) 67 #define SRC_REQ_STA_1 (SPM_BASE + 0x118) 68 #define SRC_REQ_STA_2 (SPM_BASE + 0x120) 69 #define SRC_REQ_STA_3 (SPM_BASE + 0x124) 70 #define SRC_REQ_STA_4 (SPM_BASE + 0x128) 71 #define PCM_TIMER_OUT (SPM_BASE + 0x130) 72 #define PCM_WDT_OUT (SPM_BASE + 0x134) 73 #define SPM_IRQ_STA (SPM_BASE + 0x138) 74 #define MD32PCM_WAKEUP_STA (SPM_BASE + 0x13C) 75 #define MD32PCM_EVENT_STA (SPM_BASE + 0x140) 76 #define SPM_WAKEUP_STA (SPM_BASE + 0x144) 77 #define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x148) 78 #define SPM_WAKEUP_MISC (SPM_BASE + 0x14C) 79 #define MM_DVFS_HALT (SPM_BASE + 0x150) 80 #define SUBSYS_IDLE_STA (SPM_BASE + 0x164) 81 #define PCM_STA (SPM_BASE + 0x168) 82 #define PWR_STATUS (SPM_BASE + 0x16C) 83 #define PWR_STATUS_2ND (SPM_BASE + 0x170) 84 #define CPU_PWR_STATUS (SPM_BASE + 0x174) 85 #define CPU_PWR_STATUS_2ND (SPM_BASE + 0x178) 86 #define SPM_VTCXO_EVENT_COUNT_STA (SPM_BASE + 0x17C) 87 #define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x180) 88 #define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x184) 89 #define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x188) 90 #define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x18C) 91 #define MD32PCM_STA (SPM_BASE + 0x190) 92 #define MD32PCM_PC (SPM_BASE + 0x194) 93 #define OTHER_PWR_STATUS (SPM_BASE + 0x198) 94 #define DVFSRC_EVENT_STA (SPM_BASE + 0x19C) 95 #define BUS_PROTECT_RDY (SPM_BASE + 0x1A0) 96 #define BUS_PROTECT1_RDY (SPM_BASE + 0x1A4) 97 #define BUS_PROTECT2_RDY (SPM_BASE + 0x1A8) 98 #define BUS_PROTECT3_RDY (SPM_BASE + 0x1AC) 99 #define BUS_PROTECT4_RDY (SPM_BASE + 0x1B0) 100 #define BUS_PROTECT5_RDY (SPM_BASE + 0x1B4) 101 #define BUS_PROTECT6_RDY (SPM_BASE + 0x1B8) 102 #define BUS_PROTECT7_RDY (SPM_BASE + 0x1BC) 103 #define BUS_PROTECT8_RDY (SPM_BASE + 0x1C0) 104 #define BUS_PROTECT9_RDY (SPM_BASE + 0x1C4) 105 #define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1D0) 106 #define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1D4) 107 #define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1D8) 108 #define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1DC) 109 #define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1E0) 110 #define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1E4) 111 #define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1E8) 112 #define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1EC) 113 #define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1F0) 114 #define SPM_CG_CHECK_STA (SPM_BASE + 0x1F4) 115 #define SPM_DVFS_STA (SPM_BASE + 0x1F8) 116 #define SPM_DVFS_OPP_STA (SPM_BASE + 0x1FC) 117 #define CPUEB_PWR_CON (SPM_BASE + 0x200) 118 #define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x204) 119 #define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x208) 120 #define SPM_CPU0_PWR_CON (SPM_BASE + 0x20C) 121 #define SPM_CPU1_PWR_CON (SPM_BASE + 0x210) 122 #define SPM_CPU2_PWR_CON (SPM_BASE + 0x214) 123 #define SPM_CPU3_PWR_CON (SPM_BASE + 0x218) 124 #define SPM_CPU4_PWR_CON (SPM_BASE + 0x21C) 125 #define SPM_CPU5_PWR_CON (SPM_BASE + 0x220) 126 #define SPM_CPU6_PWR_CON (SPM_BASE + 0x224) 127 #define SPM_CPU7_PWR_CON (SPM_BASE + 0x228) 128 #define ARMPLL_CLK_CON (SPM_BASE + 0x22C) 129 #define MCUSYS_IDLE_STA (SPM_BASE + 0x230) 130 #define GIC_WAKEUP_STA (SPM_BASE + 0x234) 131 #define CPU_SPARE_CON (SPM_BASE + 0x238) 132 #define CPU_SPARE_CON_SET (SPM_BASE + 0x23C) 133 #define CPU_SPARE_CON_CLR (SPM_BASE + 0x240) 134 #define ARMPLL_CLK_SEL (SPM_BASE + 0x244) 135 #define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x248) 136 #define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x24C) 137 #define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x250) 138 #define CPU_IRQ_MASK (SPM_BASE + 0x260) 139 #define CPU_IRQ_MASK_SET (SPM_BASE + 0x264) 140 #define CPU_IRQ_MASK_CLR (SPM_BASE + 0x268) 141 #define CPU_WFI_EN (SPM_BASE + 0x280) 142 #define CPU_WFI_EN_SET (SPM_BASE + 0x284) 143 #define CPU_WFI_EN_CLR (SPM_BASE + 0x288) 144 #define SYSRAM_CON (SPM_BASE + 0x290) 145 #define SYSROM_CON (SPM_BASE + 0x294) 146 #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0) 147 #define ROOT_CORE_ADDR (SPM_BASE + 0x2A4) 148 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0) 149 #define SPM2SW_MAILBOX_1 (SPM_BASE + 0x2D4) 150 #define SPM2SW_MAILBOX_2 (SPM_BASE + 0x2D8) 151 #define SPM2SW_MAILBOX_3 (SPM_BASE + 0x2DC) 152 #define SW2SPM_INT (SPM_BASE + 0x2E0) 153 #define SW2SPM_INT_SET (SPM_BASE + 0x2E4) 154 #define SW2SPM_INT_CLR (SPM_BASE + 0x2E8) 155 #define SW2SPM_MAILBOX_0 (SPM_BASE + 0x2EC) 156 #define SW2SPM_MAILBOX_1 (SPM_BASE + 0x2F0) 157 #define SW2SPM_MAILBOX_2 (SPM_BASE + 0x2F4) 158 #define SW2SPM_MAILBOX_3 (SPM_BASE + 0x2F8) 159 #define SW2SPM_CFG (SPM_BASE + 0x2FC) 160 #define MFG0_PWR_CON (SPM_BASE + 0x300) 161 #define MFG1_PWR_CON (SPM_BASE + 0x304) 162 #define MFG2_PWR_CON (SPM_BASE + 0x308) 163 #define MFG3_PWR_CON (SPM_BASE + 0x30C) 164 #define MFG4_PWR_CON (SPM_BASE + 0x310) 165 #define MFG5_PWR_CON (SPM_BASE + 0x314) 166 #define IFR_PWR_CON (SPM_BASE + 0x318) 167 #define IFR_SUB_PWR_CON (SPM_BASE + 0x31C) 168 #define PERI_PWR_CON (SPM_BASE + 0x320) 169 #define PEXTP_MAC_TOP_P0_PWR_CON (SPM_BASE + 0x324) 170 #define PEXTP_PHY_TOP_PWR_CON (SPM_BASE + 0x328) 171 #define APHY_N_PWR_CON (SPM_BASE + 0x32C) 172 #define APHY_S_PWR_CON (SPM_BASE + 0x330) 173 #define ETHER_PWR_CON (SPM_BASE + 0x338) 174 #define DPY0_PWR_CON (SPM_BASE + 0x33C) 175 #define DPY1_PWR_CON (SPM_BASE + 0x340) 176 #define DPM0_PWR_CON (SPM_BASE + 0x344) 177 #define DPM1_PWR_CON (SPM_BASE + 0x348) 178 #define AUDIO_PWR_CON (SPM_BASE + 0x34C) 179 #define AUDIO_ASRC_PWR_CON (SPM_BASE + 0x350) 180 #define ADSP_PWR_CON (SPM_BASE + 0x354) 181 #define ADSP_INFRA_PWR_CON (SPM_BASE + 0x358) 182 #define ADSP_AO_PWR_CON (SPM_BASE + 0x35C) 183 #define VPPSYS0_PWR_CON (SPM_BASE + 0x360) 184 #define VPPSYS1_PWR_CON (SPM_BASE + 0x364) 185 #define VDOSYS0_PWR_CON (SPM_BASE + 0x368) 186 #define VDOSYS1_PWR_CON (SPM_BASE + 0x36C) 187 #define WPESYS_PWR_CON (SPM_BASE + 0x370) 188 #define DP_TX_PWR_CON (SPM_BASE + 0x374) 189 #define EDP_TX_PWR_CON (SPM_BASE + 0x378) 190 #define HDMI_TX_PWR_CON (SPM_BASE + 0x37C) 191 #define VDE0_PWR_CON (SPM_BASE + 0x380) 192 #define VDE1_PWR_CON (SPM_BASE + 0x384) 193 #define VDE2_PWR_CON (SPM_BASE + 0x388) 194 #define VEN_PWR_CON (SPM_BASE + 0x38C) 195 #define VEN_CORE1_PWR_CON (SPM_BASE + 0x390) 196 #define CAM_MAIN_PWR_CON (SPM_BASE + 0x394) 197 #define CAM_SUBA_PWR_CON (SPM_BASE + 0x398) 198 #define CAM_SUBB_PWR_CON (SPM_BASE + 0x39C) 199 #define CAM_VCORE_PWR_CON (SPM_BASE + 0x3A0) 200 #define IMG_VCORE_PWR_CON (SPM_BASE + 0x3A4) 201 #define IMG_MAIN_PWR_CON (SPM_BASE + 0x3A8) 202 #define IMG_DIP_PWR_CON (SPM_BASE + 0x3AC) 203 #define IMG_IPE_PWR_CON (SPM_BASE + 0x3B0) 204 #define NNA0_PWR_CON (SPM_BASE + 0x3B4) 205 #define NNA1_PWR_CON (SPM_BASE + 0x3B8) 206 #define IPNNA_PWR_CON (SPM_BASE + 0x3C0) 207 #define CSI_RX_TOP_PWR_CON (SPM_BASE + 0x3C4) 208 #define SSPM_SRAM_CON (SPM_BASE + 0x3CC) 209 #define SCP_SRAM_CON (SPM_BASE + 0x3D0) 210 #define DEVAPC_IFR_SRAM_CON (SPM_BASE + 0x3D8) 211 #define DEVAPC_SUBIFR_SRAM_CON (SPM_BASE + 0x3DC) 212 #define DEVAPC_ACP_SRAM_CON (SPM_BASE + 0x3E0) 213 #define USB_SRAM_CON (SPM_BASE + 0x3E4) 214 #define DUMMY_SRAM_CON (SPM_BASE + 0x3E8) 215 #define EXT_BUCK_ISO (SPM_BASE + 0x3EC) 216 #define MSDC_SRAM_CON (SPM_BASE + 0x3F0) 217 #define DEBUGTOP_SRAM_CON (SPM_BASE + 0x3F4) 218 #define DPMAIF_SRAM_CON (SPM_BASE + 0x3F8) 219 #define GCPU_SRAM_CON (SPM_BASE + 0x3FC) 220 #define SPM_MEM_CK_SEL (SPM_BASE + 0x400) 221 #define SPM_BUS_PROTECT_MASK_B (SPM_BASE + 0x404) 222 #define SPM_BUS_PROTECT1_MASK_B (SPM_BASE + 0x408) 223 #define SPM_BUS_PROTECT2_MASK_B (SPM_BASE + 0x40C) 224 #define SPM_BUS_PROTECT3_MASK_B (SPM_BASE + 0x410) 225 #define SPM_BUS_PROTECT4_MASK_B (SPM_BASE + 0x414) 226 #define SPM_BUS_PROTECT5_MASK_B (SPM_BASE + 0x418) 227 #define SPM_BUS_PROTECT6_MASK_B (SPM_BASE + 0x41C) 228 #define SPM_BUS_PROTECT7_MASK_B (SPM_BASE + 0x420) 229 #define SPM_BUS_PROTECT8_MASK_B (SPM_BASE + 0x424) 230 #define SPM_BUS_PROTECT9_MASK_B (SPM_BASE + 0x428) 231 #define SPM_EMI_BW_MODE (SPM_BASE + 0x42C) 232 #define SPM2MM_CON (SPM_BASE + 0x434) 233 #define SPM2CPUEB_CON (SPM_BASE + 0x438) 234 #define AP_MDSRC_REQ (SPM_BASE + 0x43C) 235 #define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x440) 236 #define SPM_PLL_CON (SPM_BASE + 0x444) 237 #define RC_SPM_CTRL (SPM_BASE + 0x448) 238 #define SPM_DRAM_MCU_SW_CON_0 (SPM_BASE + 0x44C) 239 #define SPM_DRAM_MCU_SW_CON_1 (SPM_BASE + 0x450) 240 #define SPM_DRAM_MCU_SW_CON_2 (SPM_BASE + 0x454) 241 #define SPM_DRAM_MCU_SW_CON_3 (SPM_BASE + 0x458) 242 #define SPM_DRAM_MCU_SW_CON_4 (SPM_BASE + 0x45C) 243 #define SPM_DRAM_MCU_STA_0 (SPM_BASE + 0x460) 244 #define SPM_DRAM_MCU_STA_1 (SPM_BASE + 0x464) 245 #define SPM_DRAM_MCU_STA_2 (SPM_BASE + 0x468) 246 #define SPM_DRAM_MCU_SW_SEL_0 (SPM_BASE + 0x46C) 247 #define RELAY_DVFS_LEVEL (SPM_BASE + 0x470) 248 #define DRAMC_DPY_CLK_SW_CON_0 (SPM_BASE + 0x474) 249 #define DRAMC_DPY_CLK_SW_CON_1 (SPM_BASE + 0x478) 250 #define DRAMC_DPY_CLK_SW_CON_2 (SPM_BASE + 0x47C) 251 #define DRAMC_DPY_CLK_SW_CON_3 (SPM_BASE + 0x480) 252 #define DRAMC_DPY_CLK_SW_SEL_0 (SPM_BASE + 0x484) 253 #define DRAMC_DPY_CLK_SW_SEL_1 (SPM_BASE + 0x488) 254 #define DRAMC_DPY_CLK_SW_SEL_2 (SPM_BASE + 0x48C) 255 #define DRAMC_DPY_CLK_SW_SEL_3 (SPM_BASE + 0x490) 256 #define DRAMC_DPY_CLK_SPM_CON (SPM_BASE + 0x494) 257 #define SPM_DVFS_LEVEL (SPM_BASE + 0x498) 258 #define SPM_CIRQ_CON (SPM_BASE + 0x49C) 259 #define SPM_DVFS_MISC (SPM_BASE + 0x4A0) 260 #define RG_MODULE_SW_CG_0_MASK_REQ_0 (SPM_BASE + 0x4A4) 261 #define RG_MODULE_SW_CG_0_MASK_REQ_1 (SPM_BASE + 0x4A8) 262 #define RG_MODULE_SW_CG_0_MASK_REQ_2 (SPM_BASE + 0x4AC) 263 #define RG_MODULE_SW_CG_1_MASK_REQ_0 (SPM_BASE + 0x4B0) 264 #define RG_MODULE_SW_CG_1_MASK_REQ_1 (SPM_BASE + 0x4B4) 265 #define RG_MODULE_SW_CG_1_MASK_REQ_2 (SPM_BASE + 0x4B8) 266 #define RG_MODULE_SW_CG_2_MASK_REQ_0 (SPM_BASE + 0x4BC) 267 #define RG_MODULE_SW_CG_2_MASK_REQ_1 (SPM_BASE + 0x4C0) 268 #define RG_MODULE_SW_CG_2_MASK_REQ_2 (SPM_BASE + 0x4C4) 269 #define RG_MODULE_SW_CG_3_MASK_REQ_0 (SPM_BASE + 0x4C8) 270 #define RG_MODULE_SW_CG_3_MASK_REQ_1 (SPM_BASE + 0x4CC) 271 #define RG_MODULE_SW_CG_3_MASK_REQ_2 (SPM_BASE + 0x4D0) 272 #define PWR_STATUS_MASK_REQ_0 (SPM_BASE + 0x4D4) 273 #define PWR_STATUS_MASK_REQ_1 (SPM_BASE + 0x4D8) 274 #define PWR_STATUS_MASK_REQ_2 (SPM_BASE + 0x4DC) 275 #define SPM_CG_CHECK_CON (SPM_BASE + 0x4E0) 276 #define SPM_SRC_RDY_STA (SPM_BASE + 0x4E4) 277 #define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x4E8) 278 #define SPM_FORCE_DVFS (SPM_BASE + 0x4EC) 279 #define DRAMC_MCU_SRAM_CON (SPM_BASE + 0x4F0) 280 #define DRAMC_MCU2_SRAM_CON (SPM_BASE + 0x4F4) 281 #define DPY_SHU_SRAM_CON (SPM_BASE + 0x4F8) 282 #define DPY_SHU2_SRAM_CON (SPM_BASE + 0x4FC) 283 #define SPM_DPM_P2P_STA (SPM_BASE + 0x514) 284 #define SPM_DPM_P2P_CON (SPM_BASE + 0x518) 285 #define SPM_SW_FLAG_0 (SPM_BASE + 0x600) 286 #define SPM_SW_DEBUG_0 (SPM_BASE + 0x604) 287 #define SPM_SW_FLAG_1 (SPM_BASE + 0x608) 288 #define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C) 289 #define SPM_SW_RSV_0 (SPM_BASE + 0x610) 290 #define SPM_SW_RSV_1 (SPM_BASE + 0x614) 291 #define SPM_SW_RSV_2 (SPM_BASE + 0x618) 292 #define SPM_SW_RSV_3 (SPM_BASE + 0x61C) 293 #define SPM_SW_RSV_4 (SPM_BASE + 0x620) 294 #define SPM_SW_RSV_5 (SPM_BASE + 0x624) 295 #define SPM_SW_RSV_6 (SPM_BASE + 0x628) 296 #define SPM_SW_RSV_7 (SPM_BASE + 0x62C) 297 #define SPM_SW_RSV_8 (SPM_BASE + 0x630) 298 #define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634) 299 #define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638) 300 #define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C) 301 #define SPM_BK_PCM_TIMER (SPM_BASE + 0x640) 302 #define ULPOSC_CON (SPM_BASE + 0x644) 303 #define SPM_RSV_CON_0 (SPM_BASE + 0x650) 304 #define SPM_RSV_CON_1 (SPM_BASE + 0x654) 305 #define SPM_RSV_STA_0 (SPM_BASE + 0x658) 306 #define SPM_RSV_STA_1 (SPM_BASE + 0x65C) 307 #define SPM_SPARE_CON (SPM_BASE + 0x660) 308 #define SPM_SPARE_CON_SET (SPM_BASE + 0x664) 309 #define SPM_SPARE_CON_CLR (SPM_BASE + 0x668) 310 #define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C) 311 #define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670) 312 #define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674) 313 #define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678) 314 #define SCP_VCORE_LEVEL (SPM_BASE + 0x67C) 315 #define SC_MM_CK_SEL_CON (SPM_BASE + 0x680) 316 #define SPARE_ACK_MASK (SPM_BASE + 0x684) 317 #define SPM_DV_CON_0 (SPM_BASE + 0x68C) 318 #define SPM_DV_CON_1 (SPM_BASE + 0x690) 319 #define SPM_DV_STA (SPM_BASE + 0x694) 320 #define CONN_XOWCN_DEBUG_EN (SPM_BASE + 0x698) 321 #define SPM_SEMA_M0 (SPM_BASE + 0x69C) 322 #define SPM_SEMA_M1 (SPM_BASE + 0x6A0) 323 #define SPM_SEMA_M2 (SPM_BASE + 0x6A4) 324 #define SPM_SEMA_M3 (SPM_BASE + 0x6A8) 325 #define SPM_SEMA_M4 (SPM_BASE + 0x6AC) 326 #define SPM_SEMA_M5 (SPM_BASE + 0x6B0) 327 #define SPM_SEMA_M6 (SPM_BASE + 0x6B4) 328 #define SPM_SEMA_M7 (SPM_BASE + 0x6B8) 329 #define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC) 330 #define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0) 331 #define SPM_ADSP_IRQ (SPM_BASE + 0x6C4) 332 #define SPM_MD32_IRQ (SPM_BASE + 0x6C8) 333 #define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC) 334 #define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0) 335 #define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4) 336 #define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8) 337 #define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC) 338 #define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0) 339 #define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4) 340 #define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8) 341 #define SPM_AP_SEMA (SPM_BASE + 0x6F8) 342 #define SPM_SPM_SEMA (SPM_BASE + 0x6FC) 343 #define SPM_DVFS_CON (SPM_BASE + 0x700) 344 #define SPM_DVFS_CON_STA (SPM_BASE + 0x704) 345 #define SPM_PMIC_SPMI_CON (SPM_BASE + 0x708) 346 #define SPM_DVFS_CMD0 (SPM_BASE + 0x710) 347 #define SPM_DVFS_CMD1 (SPM_BASE + 0x714) 348 #define SPM_DVFS_CMD2 (SPM_BASE + 0x718) 349 #define SPM_DVFS_CMD3 (SPM_BASE + 0x71C) 350 #define SPM_DVFS_CMD4 (SPM_BASE + 0x720) 351 #define SPM_DVFS_CMD5 (SPM_BASE + 0x724) 352 #define SPM_DVFS_CMD6 (SPM_BASE + 0x728) 353 #define SPM_DVFS_CMD7 (SPM_BASE + 0x72C) 354 #define SPM_DVFS_CMD8 (SPM_BASE + 0x730) 355 #define SPM_DVFS_CMD9 (SPM_BASE + 0x734) 356 #define SPM_DVFS_CMD10 (SPM_BASE + 0x738) 357 #define SPM_DVFS_CMD11 (SPM_BASE + 0x73C) 358 #define SPM_DVFS_CMD12 (SPM_BASE + 0x740) 359 #define SPM_DVFS_CMD13 (SPM_BASE + 0x744) 360 #define SPM_DVFS_CMD14 (SPM_BASE + 0x748) 361 #define SPM_DVFS_CMD15 (SPM_BASE + 0x74C) 362 #define SPM_DVFS_CMD16 (SPM_BASE + 0x750) 363 #define SPM_DVFS_CMD17 (SPM_BASE + 0x754) 364 #define SPM_DVFS_CMD18 (SPM_BASE + 0x758) 365 #define SPM_DVFS_CMD19 (SPM_BASE + 0x75C) 366 #define SPM_DVFS_CMD20 (SPM_BASE + 0x760) 367 #define SPM_DVFS_CMD21 (SPM_BASE + 0x764) 368 #define SPM_DVFS_CMD22 (SPM_BASE + 0x768) 369 #define SPM_DVFS_CMD23 (SPM_BASE + 0x76C) 370 #define SYS_TIMER_VALUE_L (SPM_BASE + 0x770) 371 #define SYS_TIMER_VALUE_H (SPM_BASE + 0x774) 372 #define SYS_TIMER_START_L (SPM_BASE + 0x778) 373 #define SYS_TIMER_START_H (SPM_BASE + 0x77C) 374 #define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x780) 375 #define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x784) 376 #define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x788) 377 #define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x78C) 378 #define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x790) 379 #define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x794) 380 #define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x798) 381 #define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x79C) 382 #define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x7A0) 383 #define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x7A4) 384 #define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x7A8) 385 #define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x7AC) 386 #define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x7B0) 387 #define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x7B4) 388 #define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x7B8) 389 #define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x7BC) 390 #define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x7C0) 391 #define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x7C4) 392 #define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x7C8) 393 #define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x7CC) 394 #define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x7D0) 395 #define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x7D4) 396 #define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x7D8) 397 #define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x7DC) 398 #define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x7E0) 399 #define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x7E4) 400 #define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x7E8) 401 #define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x7EC) 402 #define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x7F0) 403 #define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x7F4) 404 #define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x7F8) 405 #define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x7FC) 406 #define PCM_WDT_LATCH_0 (SPM_BASE + 0x800) 407 #define PCM_WDT_LATCH_1 (SPM_BASE + 0x804) 408 #define PCM_WDT_LATCH_2 (SPM_BASE + 0x808) 409 #define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C) 410 #define PCM_WDT_LATCH_4 (SPM_BASE + 0x810) 411 #define PCM_WDT_LATCH_5 (SPM_BASE + 0x814) 412 #define PCM_WDT_LATCH_6 (SPM_BASE + 0x818) 413 #define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C) 414 #define PCM_WDT_LATCH_8 (SPM_BASE + 0x820) 415 #define PCM_WDT_LATCH_9 (SPM_BASE + 0x824) 416 #define PCM_WDT_LATCH_10 (SPM_BASE + 0x828) 417 #define PCM_WDT_LATCH_11 (SPM_BASE + 0x82C) 418 #define PCM_WDT_LATCH_12 (SPM_BASE + 0x830) 419 #define PCM_WDT_LATCH_13 (SPM_BASE + 0x834) 420 #define PCM_WDT_LATCH_14 (SPM_BASE + 0x838) 421 #define PCM_WDT_LATCH_15 (SPM_BASE + 0x83C) 422 #define PCM_WDT_LATCH_16 (SPM_BASE + 0x840) 423 #define PCM_WDT_LATCH_17 (SPM_BASE + 0x844) 424 #define PCM_WDT_LATCH_18 (SPM_BASE + 0x848) 425 #define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x84C) 426 #define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x850) 427 #define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x854) 428 #define DRAMC_GATING_ERR_LATCH_CH0_0 (SPM_BASE + 0x8A0) 429 #define DRAMC_GATING_ERR_LATCH_CH0_1 (SPM_BASE + 0x8A4) 430 #define DRAMC_GATING_ERR_LATCH_CH0_2 (SPM_BASE + 0x8A8) 431 #define DRAMC_GATING_ERR_LATCH_CH0_3 (SPM_BASE + 0x8AC) 432 #define DRAMC_GATING_ERR_LATCH_CH0_4 (SPM_BASE + 0x8B0) 433 #define DRAMC_GATING_ERR_LATCH_CH0_5 (SPM_BASE + 0x8B4) 434 #define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x8F4) 435 #define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x900) 436 #define SPM_ACK_CHK_PC_0 (SPM_BASE + 0x904) 437 #define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x908) 438 #define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x90C) 439 #define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x910) 440 #define SPM_ACK_CHK_SWINT_0 (SPM_BASE + 0x914) 441 #define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x920) 442 #define SPM_ACK_CHK_PC_1 (SPM_BASE + 0x924) 443 #define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x928) 444 #define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x92C) 445 #define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x930) 446 #define SPM_ACK_CHK_SWINT_1 (SPM_BASE + 0x934) 447 #define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x940) 448 #define SPM_ACK_CHK_PC_2 (SPM_BASE + 0x944) 449 #define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x948) 450 #define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x94C) 451 #define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x950) 452 #define SPM_ACK_CHK_SWINT_2 (SPM_BASE + 0x954) 453 #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960) 454 #define SPM_ACK_CHK_PC_3 (SPM_BASE + 0x964) 455 #define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x968) 456 #define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x96C) 457 #define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x970) 458 #define SPM_ACK_CHK_SWINT_3 (SPM_BASE + 0x974) 459 #define SPM_COUNTER_0 (SPM_BASE + 0x978) 460 #define SPM_COUNTER_1 (SPM_BASE + 0x97C) 461 #define SPM_COUNTER_2 (SPM_BASE + 0x980) 462 #define SYS_TIMER_CON (SPM_BASE + 0x98C) 463 #define SPM_TWAM_CON (SPM_BASE + 0x990) 464 #define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x994) 465 #define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x998) 466 #define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x99C) 467 #define PMSR_LAST_DAT (SPM_BASE + 0xF00) 468 #define PMSR_LAST_CNT (SPM_BASE + 0xF04) 469 #define PMSR_LAST_ACK (SPM_BASE + 0xF08) 470 #define SPM_PMSR_SEL_CON0 (SPM_BASE + 0xF10) 471 #define SPM_PMSR_SEL_CON1 (SPM_BASE + 0xF14) 472 #define SPM_PMSR_SEL_CON2 (SPM_BASE + 0xF18) 473 #define SPM_PMSR_SEL_CON3 (SPM_BASE + 0xF1C) 474 #define SPM_PMSR_SEL_CON4 (SPM_BASE + 0xF20) 475 #define SPM_PMSR_SEL_CON5 (SPM_BASE + 0xF24) 476 #define SPM_PMSR_SEL_CON6 (SPM_BASE + 0xF28) 477 #define SPM_PMSR_SEL_CON7 (SPM_BASE + 0xF2C) 478 #define SPM_PMSR_SEL_CON8 (SPM_BASE + 0xF30) 479 #define SPM_PMSR_SEL_CON9 (SPM_BASE + 0xF34) 480 #define SPM_PMSR_SEL_CON10 (SPM_BASE + 0xF3C) 481 #define SPM_PMSR_SEL_CON11 (SPM_BASE + 0xF40) 482 #define SPM_PMSR_TIEMR_STA0 (SPM_BASE + 0xFB8) 483 #define SPM_PMSR_TIEMR_STA1 (SPM_BASE + 0xFBC) 484 #define SPM_PMSR_TIEMR_STA2 (SPM_BASE + 0xFC0) 485 #define SPM_PMSR_GENERAL_CON0 (SPM_BASE + 0xFC4) 486 #define SPM_PMSR_GENERAL_CON1 (SPM_BASE + 0xFC8) 487 #define SPM_PMSR_GENERAL_CON2 (SPM_BASE + 0xFCC) 488 #define SPM_PMSR_GENERAL_CON3 (SPM_BASE + 0xFD0) 489 #define SPM_PMSR_GENERAL_CON4 (SPM_BASE + 0xFD4) 490 #define SPM_PMSR_GENERAL_CON5 (SPM_BASE + 0xFD8) 491 #define SPM_PMSR_SW_RESET (SPM_BASE + 0xFDC) 492 #define SPM_PMSR_MON_CON0 (SPM_BASE + 0xFE0) 493 #define SPM_PMSR_MON_CON1 (SPM_BASE + 0xFE4) 494 #define SPM_PMSR_MON_CON2 (SPM_BASE + 0xFE8) 495 #define SPM_PMSR_LEN_CON0 (SPM_BASE + 0xFEC) 496 #define SPM_PMSR_LEN_CON1 (SPM_BASE + 0xFF0) 497 #define SPM_PMSR_LEN_CON2 (SPM_BASE + 0xFF4) 498 499 #endif /* SPM_REG_H */ 500