1 /* 2 * Copyright 2018-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef SOC_H 9 #define SOC_H 10 11 /* Chassis specific defines - common across SoC's of a particular platform */ 12 #include <dcfg_lsch2.h> 13 14 #include <soc_default_base_addr.h> 15 #include <soc_default_helper_macros.h> 16 17 /* DDR Regions Info */ 18 #define NUM_DRAM_REGIONS U(3) 19 #define NXP_DRAM0_ADDR ULL(0x80000000) 20 #define NXP_DRAM0_MAX_SIZE ULL(0x80000000) /* 2 GB */ 21 22 #define NXP_DRAM1_ADDR ULL(0x880000000) 23 #define NXP_DRAM1_MAX_SIZE ULL(0x780000000) /* 30 GB */ 24 25 #define NXP_DRAM2_ADDR ULL(0x8800000000) 26 #define NXP_DRAM2_MAX_SIZE ULL(0x7800000000) /* 480 GB */ 27 28 /*DRAM0 Size defined in platform_def.h */ 29 #define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE 30 31 /* 32 * SVR Definition (not include major and minor rev) 33 * A: without security 34 * AE: with security 35 */ 36 #define SVR_LS1026A 0x870709 37 #define SVR_LS1026AE 0x870708 38 #define SVR_LS1046A 0x870701 39 #define SVR_LS1046AE 0x870700 40 41 /* Number of cores in platform */ 42 /* Used by common code for array initialization */ 43 #define NUMBER_OF_CLUSTERS U(1) 44 #define CORES_PER_CLUSTER U(4) 45 #define PLATFORM_CORE_COUNT (NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER) 46 47 /* 48 * Required LS standard platform porting definitions 49 * for CCI-400 50 */ 51 #define NXP_CCI_CLUSTER0_SL_IFACE_IX 4 52 53 54 /* Defines required for using XLAT tables from ARM common code */ 55 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40) 56 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40) 57 58 /* Clock Divisors */ 59 #define NXP_PLATFORM_CLK_DIVIDER U(1) 60 #define NXP_UART_CLK_DIVIDER U(2) 61 62 /* set to 0 if the clusters are not symmetrical */ 63 #define SYMMETRICAL_CLUSTERS U(1) 64 65 /* 66 * set this switch to 1 if you need to keep the debug block 67 * clocked during system power-down 68 */ 69 #define DEBUG_ACTIVE 0 70 71 /* 72 * pwr mgmt features supported in the soc-specific code: 73 * value == 0x0 the soc code does not support this feature 74 * value != 0x0 the soc code supports this feature 75 */ 76 #define SOC_CORE_RELEASE 0x1 77 #define SOC_CORE_RESTART 0x1 78 #define SOC_CORE_OFF 0x1 79 #define SOC_CORE_STANDBY 0x1 80 #define SOC_CORE_PWR_DWN 0x1 81 #define SOC_CLUSTER_STANDBY 0x1 82 #define SOC_CLUSTER_PWR_DWN 0x1 83 #define SOC_SYSTEM_STANDBY 0x1 84 #define SOC_SYSTEM_PWR_DWN 0x1 85 #define SOC_SYSTEM_OFF 0x1 86 #define SOC_SYSTEM_RESET 0x1 87 88 /* Start: Macros used by lib/psci files */ 89 #define SYSTEM_PWR_DOMAINS 1 90 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 91 NUMBER_OF_CLUSTERS + \ 92 SYSTEM_PWR_DOMAINS) 93 94 /* Power state coordination occurs at the system level */ 95 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 96 97 /* define retention state */ 98 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) 99 100 /* define power-down state */ 101 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1) 102 103 /* 104 * Some data must be aligned on the biggest cache line size in the platform. 105 * This is known only to the platform as it might have a combination of 106 * integrated and external caches. 107 * 108 * CACHE_WRITEBACK_GRANULE is defined in soc.def 109 */ 110 111 /* One cache line needed for bakery locks on ARM platforms */ 112 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 113 114 #ifndef __ASSEMBLER__ 115 /* CCI slave interfaces */ 116 static const int cci_map[] = { 117 NXP_CCI_CLUSTER0_SL_IFACE_IX, 118 }; 119 120 void soc_init_lowlevel(void); 121 void soc_init_percpu(void); 122 void _soc_set_start_addr(unsigned long addr); 123 #endif 124 125 #endif /* SOC_H */ 126