1 /**
2 * \file
3 * \brief Segment handling.
4 * \ingroup api_calls
5 */
6 /*
7 * (c) 2008-2009 Adam Lackorzynski <adam@os.inf.tu-dresden.de>
8 * economic rights: Technische Universität Dresden (Germany)
9 *
10 * This file is part of TUD:OS and distributed under the terms of the
11 * GNU General Public License 2.
12 * Please see the COPYING-GPL-2 file for details.
13 *
14 * As a special exception, you may use this file as part of a free software
15 * library without restriction. Specifically, if other files instantiate
16 * templates or use macros or inline functions from this file, or you compile
17 * this file and link it with other files to produce an executable, this
18 * file does not by itself cause the resulting executable to be covered by
19 * the GNU General Public License. This exception does not however
20 * invalidate any other reasons why the executable file might be covered by
21 * the GNU General Public License.
22 */
23 /*****************************************************************************/
24 #ifndef __L4_SYS__ARCH_X86__SEGMENT_H__
25 #define __L4_SYS__ARCH_X86__SEGMENT_H__
26
27 #ifndef L4API_l4f
28 #error This header file can only be used with a L4API version!
29 #endif
30
31 #include <l4/sys/ipc.h>
32
33 /**
34 * Set LDT segments descriptors.
35 * \ingroup api_calls_fiasco
36 *
37 * \param task Task to set the segment for.
38 * \param ldt Pointer to LDT hardware descriptors.
39 * \param num_desc Number of descriptors.
40 * \param entry_number_start Entry number to start.
41 * \param utcb UTCB of the caller.
42 */
43 L4_INLINE long
44 fiasco_ldt_set(l4_cap_idx_t task, void *ldt, unsigned int num_desc,
45 unsigned int entry_number_start, l4_utcb_t *utcb);
46
47 /**
48 * Set GDT segment descriptors. Fiasco supports 3 consecutive entries,
49 * starting at the value returned by fiasco_gdt_get_entry_offset()
50 * \ingroup api_calls_fiasco
51 *
52 * \param thread Thread to set the GDT entry for.
53 * \param desc Pointer to GDT descriptors.
54 * \param size Size of the descriptors in bytes
55 * (multiple of 8).
56 * \param entry_number_start Entry number to start (valid values: 0-2).
57 * \param utcb UTCB of the caller.
58 * \return System call error
59 */
60 L4_INLINE long
61 fiasco_gdt_set(l4_cap_idx_t thread, void *desc, unsigned int size,
62 unsigned int entry_number_start, l4_utcb_t *utcb);
63
64 /**
65 * Return the offset of the entry in the GDT.
66 * \param thread Thread to get info from.
67 * \param utcb UTCB of the caller.
68 * \ingroup api_calls_fiasco
69 */
70 L4_INLINE unsigned
71 fiasco_gdt_get_entry_offset(l4_cap_idx_t thread, l4_utcb_t *utcb);
72
73 /**
74 * \brief Contants for LDT handling.
75 */
76 enum L4_task_ldt_x86_consts
77 {
78 /** Size of an LDT entry. */
79 L4_TASK_LDT_X86_ENTRY_SIZE = 8,
80 /** Maximum number of LDT entries that can be written with one call. */
81 L4_TASK_LDT_X86_MAX_ENTRIES
82 = (L4_UTCB_GENERIC_DATA_SIZE - 2)
83 / (L4_TASK_LDT_X86_ENTRY_SIZE / (L4_MWORD_BITS / 8)),
84 };
85
86 /**
87 * Set the base address for the FS segment.
88 * \param thread Thread for which the FS base address shall be modified.
89 * \param base Base address.
90 * \param utcb UTCB of the caller.
91 *
92 * \retval L4_EOK Success.
93 * \retval -L4_EINVAL Invalid base address (\p base).
94 * \retval -L4_ENOSYS Operation not supported with current kernel
95 * configuration.
96 *
97 * \note
98 * Calling this function is equivalent to calling
99 * `fiasco_amd64_set_segment_base(thread, L4_AMD64_SEGMENT_FS, base, utcb)`.
100 */
101 L4_INLINE long
102 fiasco_amd64_set_fs(l4_cap_idx_t thread, l4_umword_t base, l4_utcb_t *utcb);
103
104 /**
105 * Constants for identifying segments.
106 */
107 enum L4_sys_segment
108 {
109 /// Constant identifying the FS segment.
110 L4_AMD64_SEGMENT_FS = 0,
111 /// Constant identifying the GS segment.
112 L4_AMD64_SEGMENT_GS = 1
113 };
114
115 /**
116 * Set the base address for a segment.
117 * \param thread Thread for which the base address of the selected segment
118 * shall be modified.
119 * \param segr Segment to modify (one of ::L4_sys_segment).
120 * \param base Base address.
121 * \param utcb UTCB of the caller.
122 *
123 * \retval L4_EOK Success.
124 * \retval -L4_EINVAL Invalid segment (\p segr) or base address (\p base).
125 * \retval -L4_ENOSYS Operation not supported with current kernel
126 * configuration.
127 */
128 L4_INLINE long
129 fiasco_amd64_set_segment_base(l4_cap_idx_t thread, enum L4_sys_segment segr,
130 l4_umword_t base, l4_utcb_t *utcb);
131
132 /**
133 * Get segment information.
134 * \param[in] thread Thread to get info from.
135 * \param[out] user_ds DS segment selector.
136 * \param[out] user_cs 64-bit CS segment selector.
137 * \param[out] user32_cs 32-bit CS segment selector.
138 * \param[in] utcb UTCB of the caller.
139 * \return System call error
140 */
141 L4_INLINE long
142 fiasco_amd64_segment_info(l4_cap_idx_t thread, unsigned *user_ds,
143 unsigned *user_cs, unsigned *user32_cs,
144 l4_utcb_t *utcb);
145
146 /*****************************************************************************
147 *** Implementation
148 *****************************************************************************/
149
150 #include <l4/sys/task.h>
151 #include <l4/sys/thread.h>
152
153 L4_INLINE long
fiasco_ldt_set(l4_cap_idx_t task,void * ldt,unsigned int num_desc,unsigned int entry_number_start,l4_utcb_t * utcb)154 fiasco_ldt_set(l4_cap_idx_t task, void *ldt, unsigned int num_desc,
155 unsigned int entry_number_start, l4_utcb_t *utcb)
156 {
157 if (num_desc > L4_TASK_LDT_X86_MAX_ENTRIES)
158 return -L4_EINVAL;
159 l4_utcb_mr_u(utcb)->mr[0] = L4_TASK_LDT_SET_X86_OP;
160 l4_utcb_mr_u(utcb)->mr[1] = entry_number_start;
161 __builtin_memcpy(&l4_utcb_mr_u(utcb)->mr[2], ldt,
162 num_desc * L4_TASK_LDT_X86_ENTRY_SIZE);
163 return l4_error_u(l4_ipc_call(task, utcb, l4_msgtag(L4_PROTO_TASK, 2 + num_desc * 2, 0, 0), L4_IPC_NEVER), utcb);
164 }
165
166 L4_INLINE unsigned
fiasco_gdt_get_entry_offset(l4_cap_idx_t thread,l4_utcb_t * utcb)167 fiasco_gdt_get_entry_offset(l4_cap_idx_t thread, l4_utcb_t *utcb)
168 {
169 l4_utcb_mr_u(utcb)->mr[0] = L4_THREAD_X86_GDT_OP;
170 if (l4_error_u(l4_ipc_call(thread, utcb, l4_msgtag(L4_PROTO_THREAD, 1, 0, 0), L4_IPC_NEVER), utcb))
171 return -1;
172 return l4_utcb_mr_u(utcb)->mr[0];
173 }
174
175 L4_INLINE long
fiasco_amd64_segment_info(l4_cap_idx_t thread,unsigned * user_ds,unsigned * user_cs,unsigned * user32_cs,l4_utcb_t * utcb)176 fiasco_amd64_segment_info(l4_cap_idx_t thread, unsigned *user_ds,
177 unsigned *user_cs, unsigned *user32_cs,
178 l4_utcb_t *utcb)
179 {
180 l4_msg_regs_t *m = l4_utcb_mr_u(utcb);
181 int r;
182
183 m->mr[0] = L4_THREAD_AMD64_GET_SEGMENT_INFO_OP;
184
185 r = l4_error_u(l4_ipc_call(thread, utcb, l4_msgtag(L4_PROTO_THREAD, 1, 0, 0),
186 L4_IPC_NEVER), utcb);
187 if (r < 0)
188 return r;
189
190 *user_ds = m->mr[0];
191 *user_cs = m->mr[1];
192 *user32_cs = m->mr[2];
193
194 return 0;
195 }
196
197 #endif /* ! __L4_SYS__ARCH_X86__SEGMENT_H__ */
198