1 /* 2 * (c) 2009 Adam Lackorzynski <adam@os.inf.tu-dresden.de>, 3 * Alexander Warg <warg@os.inf.tu-dresden.de> 4 * economic rights: Technische Universität Dresden (Germany) 5 * 6 * This file is part of TUD:OS and distributed under the terms of the 7 * GNU General Public License 2. 8 * Please see the COPYING-GPL-2 file for details. 9 * 10 * As a special exception, you may use this file as part of a free software 11 * library without restriction. Specifically, if other files instantiate 12 * templates or use macros or inline functions from this file, or you compile 13 * this file and link it with other files to produce an executable, this 14 * file does not by itself cause the resulting executable to be covered by 15 * the GNU General Public License. This exception does not however 16 * invalidate any other reasons why the executable file might be covered by 17 * the GNU General Public License. 18 */ 19 #pragma once 20 21 #include <l4/sys/types.h> 22 #include <l4/sys/__vcpu-arm.h> 23 24 enum 25 { 26 /** 27 * Architecture specific version ID. 28 * 29 * This ID must match the version field in the l4_vcpu_state_t structure 30 * after enabling vCPU mode or extended vCPU mode for a thread. 31 */ 32 L4_VCPU_STATE_VERSION = 0x35 33 }; 34 35 /** 36 * \brief vCPU registers. 37 * \ingroup l4_vcpu_api 38 */ 39 typedef struct l4_vcpu_regs_t 40 { 41 l4_umword_t pfa; 42 l4_umword_t err; 43 44 l4_umword_t r[13]; 45 46 l4_umword_t sp; 47 l4_umword_t lr; 48 l4_umword_t _dummy; 49 l4_umword_t ip; 50 l4_umword_t flags; 51 l4_umword_t tpidruro; /**< Thread-ID register */ 52 } l4_vcpu_regs_t; 53 54 typedef struct l4_vcpu_arch_state_t 55 { 56 l4_umword_t host_tpidruro; 57 } l4_vcpu_arch_state_t; 58 59 /** 60 * \brief vCPU message registers. 61 * \ingroup l4_vcpu_api 62 */ 63 typedef struct l4_vcpu_ipc_regs_t 64 { 65 l4_msgtag_t tag; 66 l4_umword_t _d1[3]; 67 l4_umword_t label; 68 l4_umword_t _d2[8]; 69 } l4_vcpu_ipc_regs_t; 70 71 /** 72 * IDs for extended vCPU state fields. 73 * 74 * Bits 14..15: are the field size: 75 * * 0 = 32bit field 76 * * 1 = register width field 77 * * 2 = 64bit field 78 */ 79 enum L4_vcpu_e_field_ids 80 { 81 L4_VCPU_E_HCR = 0x8008, 82 L4_VCPU_E_TTBR0 = 0x8010, 83 L4_VCPU_E_TTBR1 = 0x8018, 84 L4_VCPU_E_TTBCR = 0x0020, 85 L4_VCPU_E_SCTLR = 0x0024, 86 L4_VCPU_E_DACR = 0x0028, 87 L4_VCPU_E_FCSEIDR = 0x002c, 88 89 L4_VCPU_E_CNTVCTL = 0x0030, 90 L4_VCPU_E_CNTVOFF = 0x8038, 91 92 L4_VCPU_E_VMPIDR = 0x0040, 93 L4_VCPU_E_VPIDR = 0x0044, 94 95 L4_VCPU_E_GIC_HCR = 0x0050, 96 L4_VCPU_E_GIC_VTR = 0x0054, 97 L4_VCPU_E_GIC_VMCR = 0x0058, 98 L4_VCPU_E_GIC_MISR = 0x005c, 99 L4_VCPU_E_GIC_EISR = 0x0060, 100 L4_VCPU_E_GIC_ELSR = 0x0064, 101 L4_VCPU_E_GIC_V2_LR0 = 0x0068, 102 L4_VCPU_E_GIC_V3_LR0 = 0x8068, 103 }; 104