1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
5#include <dt-bindings/clock/qcom,lcc-msm8960.h>
6#include <dt-bindings/reset/qcom,gcc-msm8960.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15	model = "Qualcomm APQ8064";
16	compatible = "qcom,apq8064";
17	interrupt-parent = <&intc>;
18
19	reserved-memory {
20		#address-cells = <1>;
21		#size-cells = <1>;
22		ranges;
23
24		smem_region: smem@80000000 {
25			reg = <0x80000000 0x200000>;
26			no-map;
27		};
28
29		wcnss_mem: wcnss@8f000000 {
30			reg = <0x8f000000 0x700000>;
31			no-map;
32		};
33	};
34
35	cpus {
36		#address-cells = <1>;
37		#size-cells = <0>;
38
39		CPU0: cpu@0 {
40			compatible = "qcom,krait";
41			enable-method = "qcom,kpss-acc-v1";
42			device_type = "cpu";
43			reg = <0>;
44			next-level-cache = <&L2>;
45			qcom,acc = <&acc0>;
46			qcom,saw = <&saw0>;
47			cpu-idle-states = <&CPU_SPC>;
48		};
49
50		CPU1: cpu@1 {
51			compatible = "qcom,krait";
52			enable-method = "qcom,kpss-acc-v1";
53			device_type = "cpu";
54			reg = <1>;
55			next-level-cache = <&L2>;
56			qcom,acc = <&acc1>;
57			qcom,saw = <&saw1>;
58			cpu-idle-states = <&CPU_SPC>;
59		};
60
61		CPU2: cpu@2 {
62			compatible = "qcom,krait";
63			enable-method = "qcom,kpss-acc-v1";
64			device_type = "cpu";
65			reg = <2>;
66			next-level-cache = <&L2>;
67			qcom,acc = <&acc2>;
68			qcom,saw = <&saw2>;
69			cpu-idle-states = <&CPU_SPC>;
70		};
71
72		CPU3: cpu@3 {
73			compatible = "qcom,krait";
74			enable-method = "qcom,kpss-acc-v1";
75			device_type = "cpu";
76			reg = <3>;
77			next-level-cache = <&L2>;
78			qcom,acc = <&acc3>;
79			qcom,saw = <&saw3>;
80			cpu-idle-states = <&CPU_SPC>;
81		};
82
83		L2: l2-cache {
84			compatible = "cache";
85			cache-level = <2>;
86		};
87
88		idle-states {
89			CPU_SPC: spc {
90				compatible = "qcom,idle-state-spc",
91						"arm,idle-state";
92				entry-latency-us = <400>;
93				exit-latency-us = <900>;
94				min-residency-us = <3000>;
95			};
96		};
97	};
98
99	memory@0 {
100		device_type = "memory";
101		reg = <0x0 0x0>;
102	};
103
104	thermal-zones {
105		cpu0-thermal {
106			polling-delay-passive = <250>;
107			polling-delay = <1000>;
108
109			thermal-sensors = <&tsens 7>;
110			coefficients = <1199 0>;
111
112			trips {
113				cpu_alert0: trip0 {
114					temperature = <75000>;
115					hysteresis = <2000>;
116					type = "passive";
117				};
118				cpu_crit0: trip1 {
119					temperature = <110000>;
120					hysteresis = <2000>;
121					type = "critical";
122				};
123			};
124		};
125
126		cpu1-thermal {
127			polling-delay-passive = <250>;
128			polling-delay = <1000>;
129
130			thermal-sensors = <&tsens 8>;
131			coefficients = <1132 0>;
132
133			trips {
134				cpu_alert1: trip0 {
135					temperature = <75000>;
136					hysteresis = <2000>;
137					type = "passive";
138				};
139				cpu_crit1: trip1 {
140					temperature = <110000>;
141					hysteresis = <2000>;
142					type = "critical";
143				};
144			};
145		};
146
147		cpu2-thermal {
148			polling-delay-passive = <250>;
149			polling-delay = <1000>;
150
151			thermal-sensors = <&tsens 9>;
152			coefficients = <1199 0>;
153
154			trips {
155				cpu_alert2: trip0 {
156					temperature = <75000>;
157					hysteresis = <2000>;
158					type = "passive";
159				};
160				cpu_crit2: trip1 {
161					temperature = <110000>;
162					hysteresis = <2000>;
163					type = "critical";
164				};
165			};
166		};
167
168		cpu3-thermal {
169			polling-delay-passive = <250>;
170			polling-delay = <1000>;
171
172			thermal-sensors = <&tsens 10>;
173			coefficients = <1132 0>;
174
175			trips {
176				cpu_alert3: trip0 {
177					temperature = <75000>;
178					hysteresis = <2000>;
179					type = "passive";
180				};
181				cpu_crit3: trip1 {
182					temperature = <110000>;
183					hysteresis = <2000>;
184					type = "critical";
185				};
186			};
187		};
188	};
189
190	cpu-pmu {
191		compatible = "qcom,krait-pmu";
192		interrupts = <1 10 0x304>;
193	};
194
195	clocks {
196		cxo_board: cxo_board {
197			compatible = "fixed-clock";
198			#clock-cells = <0>;
199			clock-frequency = <19200000>;
200		};
201
202		pxo_board: pxo_board {
203			compatible = "fixed-clock";
204			#clock-cells = <0>;
205			clock-frequency = <27000000>;
206		};
207
208		sleep_clk: sleep_clk {
209			compatible = "fixed-clock";
210			#clock-cells = <0>;
211			clock-frequency = <32768>;
212		};
213	};
214
215	sfpb_mutex: hwmutex {
216		compatible = "qcom,sfpb-mutex";
217		syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
218		#hwlock-cells = <1>;
219	};
220
221	smem {
222		compatible = "qcom,smem";
223		memory-region = <&smem_region>;
224
225		hwlocks = <&sfpb_mutex 3>;
226	};
227
228	smd {
229		compatible = "qcom,smd";
230
231		modem-edge {
232			interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
233
234			qcom,ipc = <&l2cc 8 3>;
235			qcom,smd-edge = <0>;
236
237			status = "disabled";
238		};
239
240		q6-edge {
241			interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
242
243			qcom,ipc = <&l2cc 8 15>;
244			qcom,smd-edge = <1>;
245
246			status = "disabled";
247		};
248
249		dsps-edge {
250			interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
251
252			qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
253			qcom,smd-edge = <3>;
254
255			status = "disabled";
256		};
257
258		riva-edge {
259			interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
260
261			qcom,ipc = <&l2cc 8 25>;
262			qcom,smd-edge = <6>;
263
264			status = "disabled";
265		};
266	};
267
268	smsm {
269		compatible = "qcom,smsm";
270
271		#address-cells = <1>;
272		#size-cells = <0>;
273
274		qcom,ipc-1 = <&l2cc 8 4>;
275		qcom,ipc-2 = <&l2cc 8 14>;
276		qcom,ipc-3 = <&l2cc 8 23>;
277		qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
278
279		apps_smsm: apps@0 {
280			reg = <0>;
281			#qcom,smem-state-cells = <1>;
282		};
283
284		modem_smsm: modem@1 {
285			reg = <1>;
286			interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
287
288			interrupt-controller;
289			#interrupt-cells = <2>;
290		};
291
292		q6_smsm: q6@2 {
293			reg = <2>;
294			interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
295
296			interrupt-controller;
297			#interrupt-cells = <2>;
298		};
299
300		wcnss_smsm: wcnss@3 {
301			reg = <3>;
302			interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
303
304			interrupt-controller;
305			#interrupt-cells = <2>;
306		};
307
308		dsps_smsm: dsps@4 {
309			reg = <4>;
310			interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
311
312			interrupt-controller;
313			#interrupt-cells = <2>;
314		};
315	};
316
317	firmware {
318		scm {
319			compatible = "qcom,scm-apq8064", "qcom,scm";
320
321			clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
322			clock-names = "core";
323		};
324	};
325
326
327	/*
328	 * These channels from the ADC are simply hardware monitors.
329	 * That is why the ADC is referred to as "HKADC" - HouseKeeping
330	 * ADC.
331	 */
332	iio-hwmon {
333		compatible = "iio-hwmon";
334		io-channels = <&xoadc 0x00 0x01>, /* Battery */
335			    <&xoadc 0x00 0x02>, /* DC in (charger) */
336			    <&xoadc 0x00 0x04>, /* VPH the main system voltage */
337			    <&xoadc 0x00 0x0b>, /* Die temperature */
338			    <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
339			    <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
340			    <&xoadc 0x00 0x0e>; /* Charger temperature */
341	};
342
343	soc: soc {
344		#address-cells = <1>;
345		#size-cells = <1>;
346		ranges;
347		compatible = "simple-bus";
348
349		tlmm_pinmux: pinctrl@800000 {
350			compatible = "qcom,apq8064-pinctrl";
351			reg = <0x800000 0x4000>;
352
353			gpio-controller;
354			gpio-ranges = <&tlmm_pinmux 0 0 90>;
355			#gpio-cells = <2>;
356			interrupt-controller;
357			#interrupt-cells = <2>;
358			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
359
360			pinctrl-names = "default";
361			pinctrl-0 = <&ps_hold>;
362		};
363
364		sfpb_wrapper_mutex: syscon@1200000 {
365			compatible = "syscon";
366			reg = <0x01200000 0x8000>;
367		};
368
369		intc: interrupt-controller@2000000 {
370			compatible = "qcom,msm-qgic2";
371			interrupt-controller;
372			#interrupt-cells = <3>;
373			reg = <0x02000000 0x1000>,
374			      <0x02002000 0x1000>;
375		};
376
377		timer@200a000 {
378			compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
379				     "qcom,msm-timer";
380			interrupts = <1 1 0x301>,
381				     <1 2 0x301>,
382				     <1 3 0x301>;
383			reg = <0x0200a000 0x100>;
384			clock-frequency = <27000000>;
385			cpu-offset = <0x80000>;
386		};
387
388		acc0: clock-controller@2088000 {
389			compatible = "qcom,kpss-acc-v1";
390			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
391		};
392
393		acc1: clock-controller@2098000 {
394			compatible = "qcom,kpss-acc-v1";
395			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
396		};
397
398		acc2: clock-controller@20a8000 {
399			compatible = "qcom,kpss-acc-v1";
400			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
401		};
402
403		acc3: clock-controller@20b8000 {
404			compatible = "qcom,kpss-acc-v1";
405			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
406		};
407
408		saw0: power-controller@2089000 {
409			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
410			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
411			regulator;
412		};
413
414		saw1: power-controller@2099000 {
415			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
416			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
417			regulator;
418		};
419
420		saw2: power-controller@20a9000 {
421			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
422			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
423			regulator;
424		};
425
426		saw3: power-controller@20b9000 {
427			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
428			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
429			regulator;
430		};
431
432		sps_sic_non_secure: sps-sic-non-secure@12100000 {
433			compatible = "syscon";
434			reg = <0x12100000 0x10000>;
435		};
436
437		gsbi1: gsbi@12440000 {
438			status = "disabled";
439			compatible = "qcom,gsbi-v1.0.0";
440			cell-index = <1>;
441			reg = <0x12440000 0x100>;
442			clocks = <&gcc GSBI1_H_CLK>;
443			clock-names = "iface";
444			#address-cells = <1>;
445			#size-cells = <1>;
446			ranges;
447
448			syscon-tcsr = <&tcsr>;
449
450			gsbi1_serial: serial@12450000 {
451				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
452				reg = <0x12450000 0x100>,
453				      <0x12400000 0x03>;
454				interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
455				clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
456				clock-names = "core", "iface";
457				status = "disabled";
458			};
459
460			gsbi1_i2c: i2c@12460000 {
461				compatible = "qcom,i2c-qup-v1.1.1";
462				pinctrl-0 = <&i2c1_pins>;
463				pinctrl-1 = <&i2c1_pins_sleep>;
464				pinctrl-names = "default", "sleep";
465				reg = <0x12460000 0x1000>;
466				interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
467				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
468				clock-names = "core", "iface";
469				#address-cells = <1>;
470				#size-cells = <0>;
471				status = "disabled";
472			};
473
474		};
475
476		gsbi2: gsbi@12480000 {
477			status = "disabled";
478			compatible = "qcom,gsbi-v1.0.0";
479			cell-index = <2>;
480			reg = <0x12480000 0x100>;
481			clocks = <&gcc GSBI2_H_CLK>;
482			clock-names = "iface";
483			#address-cells = <1>;
484			#size-cells = <1>;
485			ranges;
486
487			syscon-tcsr = <&tcsr>;
488
489			gsbi2_i2c: i2c@124a0000 {
490				compatible = "qcom,i2c-qup-v1.1.1";
491				reg = <0x124a0000 0x1000>;
492				pinctrl-0 = <&i2c2_pins>;
493				pinctrl-1 = <&i2c2_pins_sleep>;
494				pinctrl-names = "default", "sleep";
495				interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
496				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
497				clock-names = "core", "iface";
498				#address-cells = <1>;
499				#size-cells = <0>;
500				status = "disabled";
501			};
502		};
503
504		gsbi3: gsbi@16200000 {
505			status = "disabled";
506			compatible = "qcom,gsbi-v1.0.0";
507			cell-index = <3>;
508			reg = <0x16200000 0x100>;
509			clocks = <&gcc GSBI3_H_CLK>;
510			clock-names = "iface";
511			#address-cells = <1>;
512			#size-cells = <1>;
513			ranges;
514			gsbi3_i2c: i2c@16280000 {
515				compatible = "qcom,i2c-qup-v1.1.1";
516				pinctrl-0 = <&i2c3_pins>;
517				pinctrl-1 = <&i2c3_pins_sleep>;
518				pinctrl-names = "default", "sleep";
519				reg = <0x16280000 0x1000>;
520				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
521				clocks = <&gcc GSBI3_QUP_CLK>,
522					 <&gcc GSBI3_H_CLK>;
523				clock-names = "core", "iface";
524				#address-cells = <1>;
525				#size-cells = <0>;
526				status = "disabled";
527			};
528		};
529
530		gsbi4: gsbi@16300000 {
531			status = "disabled";
532			compatible = "qcom,gsbi-v1.0.0";
533			cell-index = <4>;
534			reg = <0x16300000 0x03>;
535			clocks = <&gcc GSBI4_H_CLK>;
536			clock-names = "iface";
537			#address-cells = <1>;
538			#size-cells = <1>;
539			ranges;
540
541			gsbi4_i2c: i2c@16380000 {
542				compatible = "qcom,i2c-qup-v1.1.1";
543				pinctrl-0 = <&i2c4_pins>;
544				pinctrl-1 = <&i2c4_pins_sleep>;
545				pinctrl-names = "default", "sleep";
546				reg = <0x16380000 0x1000>;
547				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
548				clocks = <&gcc GSBI4_QUP_CLK>,
549					 <&gcc GSBI4_H_CLK>;
550				clock-names = "core", "iface";
551				status = "disabled";
552			};
553		};
554
555		gsbi5: gsbi@1a200000 {
556			status = "disabled";
557			compatible = "qcom,gsbi-v1.0.0";
558			cell-index = <5>;
559			reg = <0x1a200000 0x03>;
560			clocks = <&gcc GSBI5_H_CLK>;
561			clock-names = "iface";
562			#address-cells = <1>;
563			#size-cells = <1>;
564			ranges;
565
566			gsbi5_serial: serial@1a240000 {
567				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
568				reg = <0x1a240000 0x100>,
569				      <0x1a200000 0x03>;
570				interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
571				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
572				clock-names = "core", "iface";
573				status = "disabled";
574			};
575
576			gsbi5_spi: spi@1a280000 {
577				compatible = "qcom,spi-qup-v1.1.1";
578				reg = <0x1a280000 0x1000>;
579				interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
580				pinctrl-0 = <&spi5_default>;
581				pinctrl-1 = <&spi5_sleep>;
582				pinctrl-names = "default", "sleep";
583				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
584				clock-names = "core", "iface";
585				status = "disabled";
586				#address-cells = <1>;
587				#size-cells = <0>;
588			};
589		};
590
591		gsbi6: gsbi@16500000 {
592			status = "disabled";
593			compatible = "qcom,gsbi-v1.0.0";
594			cell-index = <6>;
595			reg = <0x16500000 0x03>;
596			clocks = <&gcc GSBI6_H_CLK>;
597			clock-names = "iface";
598			#address-cells = <1>;
599			#size-cells = <1>;
600			ranges;
601
602			gsbi6_serial: serial@16540000 {
603				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
604				reg = <0x16540000 0x100>,
605				      <0x16500000 0x03>;
606				interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
607				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
608				clock-names = "core", "iface";
609				status = "disabled";
610			};
611
612			gsbi6_i2c: i2c@16580000 {
613				compatible = "qcom,i2c-qup-v1.1.1";
614				pinctrl-0 = <&i2c6_pins>;
615				pinctrl-1 = <&i2c6_pins_sleep>;
616				pinctrl-names = "default", "sleep";
617				reg = <0x16580000 0x1000>;
618				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
619				clocks = <&gcc GSBI6_QUP_CLK>,
620					 <&gcc GSBI6_H_CLK>;
621				clock-names = "core", "iface";
622				status = "disabled";
623			};
624		};
625
626		gsbi7: gsbi@16600000 {
627			status = "disabled";
628			compatible = "qcom,gsbi-v1.0.0";
629			cell-index = <7>;
630			reg = <0x16600000 0x100>;
631			clocks = <&gcc GSBI7_H_CLK>;
632			clock-names = "iface";
633			#address-cells = <1>;
634			#size-cells = <1>;
635			ranges;
636			syscon-tcsr = <&tcsr>;
637
638			gsbi7_serial: serial@16640000 {
639				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
640				reg = <0x16640000 0x1000>,
641				      <0x16600000 0x1000>;
642				interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
643				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
644				clock-names = "core", "iface";
645				status = "disabled";
646			};
647
648			gsbi7_i2c: i2c@16680000 {
649				compatible = "qcom,i2c-qup-v1.1.1";
650				pinctrl-0 = <&i2c7_pins>;
651				pinctrl-1 = <&i2c7_pins_sleep>;
652				pinctrl-names = "default", "sleep";
653				reg = <0x16680000 0x1000>;
654				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
655				clocks = <&gcc GSBI7_QUP_CLK>,
656					 <&gcc GSBI7_H_CLK>;
657				clock-names = "core", "iface";
658				status = "disabled";
659			};
660		};
661
662		rng@1a500000 {
663			compatible = "qcom,prng";
664			reg = <0x1a500000 0x200>;
665			clocks = <&gcc PRNG_CLK>;
666			clock-names = "core";
667		};
668
669		ssbi@c00000 {
670			compatible = "qcom,ssbi";
671			reg = <0x00c00000 0x1000>;
672			qcom,controller-type = "pmic-arbiter";
673
674			pm8821: pmic {
675				compatible = "qcom,pm8821";
676				interrupt-parent = <&tlmm_pinmux>;
677				interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
678				#interrupt-cells = <2>;
679				interrupt-controller;
680				#address-cells = <1>;
681				#size-cells = <0>;
682
683				pm8821_mpps: mpps@50 {
684					compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
685					reg = <0x50>;
686					interrupt-controller;
687					#interrupt-cells = <2>;
688					gpio-controller;
689					#gpio-cells = <2>;
690					gpio-ranges = <&pm8821_mpps 0 0 4>;
691				};
692			};
693		};
694
695		ssbi@500000 {
696			compatible = "qcom,ssbi";
697			reg = <0x00500000 0x1000>;
698			qcom,controller-type = "pmic-arbiter";
699
700			pmicintc: pmic {
701				compatible = "qcom,pm8921";
702				interrupt-parent = <&tlmm_pinmux>;
703				interrupts = <74 8>;
704				#interrupt-cells = <2>;
705				interrupt-controller;
706				#address-cells = <1>;
707				#size-cells = <0>;
708
709				pm8921_gpio: gpio@150 {
710
711					compatible = "qcom,pm8921-gpio",
712						     "qcom,ssbi-gpio";
713					reg = <0x150>;
714					interrupt-controller;
715					#interrupt-cells = <2>;
716					gpio-controller;
717					gpio-ranges = <&pm8921_gpio 0 0 44>;
718					#gpio-cells = <2>;
719
720				};
721
722				pm8921_mpps: mpps@50 {
723					compatible = "qcom,pm8921-mpp",
724						     "qcom,ssbi-mpp";
725					reg = <0x50>;
726					gpio-controller;
727					#gpio-cells = <2>;
728					gpio-ranges = <&pm8921_mpps 0 0 12>;
729					interrupt-controller;
730					#interrupt-cells = <2>;
731				};
732
733				rtc@11d {
734					compatible = "qcom,pm8921-rtc";
735					interrupt-parent = <&pmicintc>;
736					interrupts = <39 1>;
737					reg = <0x11d>;
738					allow-set-time;
739				};
740
741				pwrkey@1c {
742					compatible = "qcom,pm8921-pwrkey";
743					reg = <0x1c>;
744					interrupt-parent = <&pmicintc>;
745					interrupts = <50 1>, <51 1>;
746					debounce = <15625>;
747					pull-up;
748				};
749
750				xoadc: xoadc@197 {
751					compatible = "qcom,pm8921-adc";
752					reg = <197>;
753					interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
754					#address-cells = <2>;
755					#size-cells = <0>;
756					#io-channel-cells = <2>;
757
758					vcoin: adc-channel@0 {
759						reg = <0x00 0x00>;
760					};
761					vbat: adc-channel@1 {
762						reg = <0x00 0x01>;
763					};
764					dcin: adc-channel@2 {
765						reg = <0x00 0x02>;
766					};
767					vph_pwr: adc-channel@4 {
768						reg = <0x00 0x04>;
769					};
770					batt_therm: adc-channel@8 {
771						reg = <0x00 0x08>;
772					};
773					batt_id: adc-channel@9 {
774						reg = <0x00 0x09>;
775					};
776					usb_vbus: adc-channel@a {
777						reg = <0x00 0x0a>;
778					};
779					die_temp: adc-channel@b {
780						reg = <0x00 0x0b>;
781					};
782					ref_625mv: adc-channel@c {
783						reg = <0x00 0x0c>;
784					};
785					ref_1250mv: adc-channel@d {
786						reg = <0x00 0x0d>;
787					};
788					chg_temp: adc-channel@e {
789						reg = <0x00 0x0e>;
790					};
791					ref_muxoff: adc-channel@f {
792						reg = <0x00 0x0f>;
793					};
794				};
795			};
796		};
797
798		qfprom: qfprom@700000 {
799			compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
800			reg = <0x00700000 0x1000>;
801			#address-cells = <1>;
802			#size-cells = <1>;
803			ranges;
804			tsens_calib: calib@404 {
805				reg = <0x404 0x10>;
806			};
807			tsens_backup: backup_calib@414 {
808				reg = <0x414 0x10>;
809			};
810		};
811
812		gcc: clock-controller@900000 {
813			compatible = "qcom,gcc-apq8064", "syscon";
814			reg = <0x00900000 0x4000>;
815			#clock-cells = <1>;
816			#power-domain-cells = <1>;
817			#reset-cells = <1>;
818			clocks = <&cxo_board>,
819				 <&pxo_board>,
820				 <&lcc PLL4>;
821			clock-names = "cxo", "pxo", "pll4";
822
823			tsens: thermal-sensor {
824				compatible = "qcom,msm8960-tsens";
825
826				nvmem-cells = <&tsens_calib>, <&tsens_backup>;
827				nvmem-cell-names = "calib", "calib_backup";
828				interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
829				interrupt-names = "uplow";
830
831				#qcom,sensors = <11>;
832				#thermal-sensor-cells = <1>;
833			};
834		};
835
836		lcc: clock-controller@28000000 {
837			compatible = "qcom,lcc-apq8064";
838			reg = <0x28000000 0x1000>;
839			#clock-cells = <1>;
840			#reset-cells = <1>;
841			clocks = <&pxo_board>,
842				 <&gcc PLL4_VOTE>,
843				 <0>,
844				 <0>, <0>,
845				 <0>, <0>,
846				 <0>;
847			clock-names = "pxo",
848				      "pll4_vote",
849				      "mi2s_codec_clk",
850				      "codec_i2s_mic_codec_clk",
851				      "spare_i2s_mic_codec_clk",
852				      "codec_i2s_spkr_codec_clk",
853				      "spare_i2s_spkr_codec_clk",
854				      "pcm_codec_clk";
855		};
856
857		mmcc: clock-controller@4000000 {
858			compatible = "qcom,mmcc-apq8064";
859			reg = <0x4000000 0x1000>;
860			#clock-cells = <1>;
861			#power-domain-cells = <1>;
862			#reset-cells = <1>;
863			clocks = <&pxo_board>,
864				 <&gcc PLL3>,
865				 <&gcc PLL8_VOTE>,
866				 <&dsi0_phy 1>,
867				 <&dsi0_phy 0>,
868				 <&dsi1_phy 1>,
869				 <&dsi1_phy 0>,
870				 <&hdmi_phy>;
871			clock-names = "pxo",
872				      "pll3",
873				      "pll8_vote",
874				      "dsi1pll",
875				      "dsi1pllbyte",
876				      "dsi2pll",
877				      "dsi2pllbyte",
878				      "hdmipll";
879		};
880
881		l2cc: clock-controller@2011000 {
882			compatible = "qcom,kpss-gcc", "syscon";
883			reg = <0x2011000 0x1000>;
884		};
885
886		rpm: rpm@108000 {
887			compatible = "qcom,rpm-apq8064";
888			reg = <0x108000 0x1000>;
889			qcom,ipc = <&l2cc 0x8 2>;
890
891			interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
892				     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
893				     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
894			interrupt-names = "ack", "err", "wakeup";
895
896			rpmcc: clock-controller {
897				compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
898				#clock-cells = <1>;
899				clocks = <&pxo_board>, <&cxo_board>;
900				clock-names = "pxo", "cxo";
901			};
902
903			regulators {
904				compatible = "qcom,rpm-pm8921-regulators";
905
906				pm8921_s1: s1 {};
907				pm8921_s2: s2 {};
908				pm8921_s3: s3 {};
909				pm8921_s4: s4 {};
910				pm8921_s7: s7 {};
911				pm8921_s8: s8 {};
912
913				pm8921_l1: l1 {};
914				pm8921_l2: l2 {};
915				pm8921_l3: l3 {};
916				pm8921_l4: l4 {};
917				pm8921_l5: l5 {};
918				pm8921_l6: l6 {};
919				pm8921_l7: l7 {};
920				pm8921_l8: l8 {};
921				pm8921_l9: l9 {};
922				pm8921_l10: l10 {};
923				pm8921_l11: l11 {};
924				pm8921_l12: l12 {};
925				pm8921_l14: l14 {};
926				pm8921_l15: l15 {};
927				pm8921_l16: l16 {};
928				pm8921_l17: l17 {};
929				pm8921_l18: l18 {};
930				pm8921_l21: l21 {};
931				pm8921_l22: l22 {};
932				pm8921_l23: l23 {};
933				pm8921_l24: l24 {};
934				pm8921_l25: l25 {};
935				pm8921_l26: l26 {};
936				pm8921_l27: l27 {};
937				pm8921_l28: l28 {};
938				pm8921_l29: l29 {};
939
940				pm8921_lvs1: lvs1 {};
941				pm8921_lvs2: lvs2 {};
942				pm8921_lvs3: lvs3 {};
943				pm8921_lvs4: lvs4 {};
944				pm8921_lvs5: lvs5 {};
945				pm8921_lvs6: lvs6 {};
946				pm8921_lvs7: lvs7 {};
947
948				pm8921_usb_switch: usb-switch {};
949
950				pm8921_hdmi_switch: hdmi-switch {
951					bias-pull-down;
952				};
953
954				pm8921_ncp: ncp {};
955			};
956		};
957
958		usb1: usb@12500000 {
959			compatible = "qcom,ci-hdrc";
960			reg = <0x12500000 0x200>,
961			      <0x12500200 0x200>;
962			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
963			clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
964			clock-names = "core", "iface";
965			assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
966			assigned-clock-rates = <60000000>;
967			resets = <&gcc USB_HS1_RESET>;
968			reset-names = "core";
969			phy_type = "ulpi";
970			ahb-burst-config = <0>;
971			phys = <&usb_hs1_phy>;
972			phy-names = "usb-phy";
973			status = "disabled";
974			#reset-cells = <1>;
975
976			ulpi {
977				usb_hs1_phy: phy {
978					compatible = "qcom,usb-hs-phy-apq8064",
979						     "qcom,usb-hs-phy";
980					clocks = <&sleep_clk>, <&cxo_board>;
981					clock-names = "sleep", "ref";
982					resets = <&usb1 0>;
983					reset-names = "por";
984					#phy-cells = <0>;
985				};
986			};
987		};
988
989		usb3: usb@12520000 {
990			compatible = "qcom,ci-hdrc";
991			reg = <0x12520000 0x200>,
992			      <0x12520200 0x200>;
993			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
994			clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
995			clock-names = "core", "iface";
996			assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
997			assigned-clock-rates = <60000000>;
998			resets = <&gcc USB_HS3_RESET>;
999			reset-names = "core";
1000			phy_type = "ulpi";
1001			ahb-burst-config = <0>;
1002			phys = <&usb_hs3_phy>;
1003			phy-names = "usb-phy";
1004			status = "disabled";
1005			#reset-cells = <1>;
1006
1007			ulpi {
1008				usb_hs3_phy: phy {
1009					compatible = "qcom,usb-hs-phy-apq8064",
1010						     "qcom,usb-hs-phy";
1011					#phy-cells = <0>;
1012					clocks = <&sleep_clk>, <&cxo_board>;
1013					clock-names = "sleep", "ref";
1014					resets = <&usb3 0>;
1015					reset-names = "por";
1016				};
1017			};
1018		};
1019
1020		usb4: usb@12530000 {
1021			compatible = "qcom,ci-hdrc";
1022			reg = <0x12530000 0x200>,
1023			      <0x12530200 0x200>;
1024			interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1025			clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1026			clock-names = "core", "iface";
1027			assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1028			assigned-clock-rates = <60000000>;
1029			resets = <&gcc USB_HS4_RESET>;
1030			reset-names = "core";
1031			phy_type = "ulpi";
1032			ahb-burst-config = <0>;
1033			phys = <&usb_hs4_phy>;
1034			phy-names = "usb-phy";
1035			status = "disabled";
1036			#reset-cells = <1>;
1037
1038			ulpi {
1039				usb_hs4_phy: phy {
1040					compatible = "qcom,usb-hs-phy-apq8064",
1041						     "qcom,usb-hs-phy";
1042					#phy-cells = <0>;
1043					clocks = <&sleep_clk>, <&cxo_board>;
1044					clock-names = "sleep", "ref";
1045					resets = <&usb4 0>;
1046					reset-names = "por";
1047				};
1048			};
1049		};
1050
1051		sata_phy0: phy@1b400000 {
1052			compatible = "qcom,apq8064-sata-phy";
1053			status = "disabled";
1054			reg = <0x1b400000 0x200>;
1055			reg-names = "phy_mem";
1056			clocks = <&gcc SATA_PHY_CFG_CLK>;
1057			clock-names = "cfg";
1058			#phy-cells = <0>;
1059		};
1060
1061		sata0: sata@29000000 {
1062			compatible = "qcom,apq8064-ahci", "generic-ahci";
1063			status	 = "disabled";
1064			reg	 = <0x29000000 0x180>;
1065			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1066
1067			clocks = <&gcc SFAB_SATA_S_H_CLK>,
1068				 <&gcc SATA_H_CLK>,
1069				 <&gcc SATA_A_CLK>,
1070				 <&gcc SATA_RXOOB_CLK>,
1071				 <&gcc SATA_PMALIVE_CLK>;
1072			clock-names = "slave_iface",
1073				      "iface",
1074				      "bus",
1075				      "rxoob",
1076				      "core_pmalive";
1077
1078			assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1079					  <&gcc SATA_PMALIVE_CLK>;
1080			assigned-clock-rates = <100000000>, <100000000>;
1081
1082			phys = <&sata_phy0>;
1083			phy-names = "sata-phy";
1084			ports-implemented = <0x1>;
1085		};
1086
1087		sdcc3: mmc@12180000 {
1088			compatible = "arm,pl18x", "arm,primecell";
1089			arm,primecell-periphid = <0x00051180>;
1090			status = "disabled";
1091			reg = <0x12180000 0x2000>;
1092			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1093			clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1094			clock-names = "mclk", "apb_pclk";
1095			bus-width = <4>;
1096			cap-sd-highspeed;
1097			cap-mmc-highspeed;
1098			max-frequency = <192000000>;
1099			no-1-8-v;
1100			dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1101			dma-names = "tx", "rx";
1102		};
1103
1104		sdcc3bam: dma-controller@12182000 {
1105			compatible = "qcom,bam-v1.3.0";
1106			reg = <0x12182000 0x8000>;
1107			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1108			clocks = <&gcc SDC3_H_CLK>;
1109			clock-names = "bam_clk";
1110			#dma-cells = <1>;
1111			qcom,ee = <0>;
1112		};
1113
1114		sdcc4: mmc@121c0000 {
1115			compatible = "arm,pl18x", "arm,primecell";
1116			arm,primecell-periphid = <0x00051180>;
1117			status = "disabled";
1118			reg = <0x121c0000 0x2000>;
1119			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1120			clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1121			clock-names = "mclk", "apb_pclk";
1122			bus-width = <4>;
1123			cap-sd-highspeed;
1124			cap-mmc-highspeed;
1125			max-frequency = <48000000>;
1126			dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1127			dma-names = "tx", "rx";
1128			pinctrl-names = "default";
1129			pinctrl-0 = <&sdc4_gpios>;
1130		};
1131
1132		sdcc4bam: dma-controller@121c2000 {
1133			compatible = "qcom,bam-v1.3.0";
1134			reg = <0x121c2000 0x8000>;
1135			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1136			clocks = <&gcc SDC4_H_CLK>;
1137			clock-names = "bam_clk";
1138			#dma-cells = <1>;
1139			qcom,ee = <0>;
1140		};
1141
1142		sdcc1: mmc@12400000 {
1143			status = "disabled";
1144			compatible = "arm,pl18x", "arm,primecell";
1145			pinctrl-names = "default";
1146			pinctrl-0 = <&sdcc1_pins>;
1147			arm,primecell-periphid = <0x00051180>;
1148			reg = <0x12400000 0x2000>;
1149			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1150			clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1151			clock-names = "mclk", "apb_pclk";
1152			bus-width = <8>;
1153			max-frequency = <96000000>;
1154			non-removable;
1155			cap-sd-highspeed;
1156			cap-mmc-highspeed;
1157			dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1158			dma-names = "tx", "rx";
1159		};
1160
1161		sdcc1bam: dma-controller@12402000 {
1162			compatible = "qcom,bam-v1.3.0";
1163			reg = <0x12402000 0x8000>;
1164			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1165			clocks = <&gcc SDC1_H_CLK>;
1166			clock-names = "bam_clk";
1167			#dma-cells = <1>;
1168			qcom,ee = <0>;
1169		};
1170
1171		tcsr: syscon@1a400000 {
1172			compatible = "qcom,tcsr-apq8064", "syscon";
1173			reg = <0x1a400000 0x100>;
1174		};
1175
1176		gpu: adreno-3xx@4300000 {
1177			compatible = "qcom,adreno-320.2", "qcom,adreno";
1178			reg = <0x04300000 0x20000>;
1179			reg-names = "kgsl_3d0_reg_memory";
1180			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1181			interrupt-names = "kgsl_3d0_irq";
1182			clock-names =
1183			    "core",
1184			    "iface",
1185			    "mem",
1186			    "mem_iface";
1187			clocks =
1188			    <&mmcc GFX3D_CLK>,
1189			    <&mmcc GFX3D_AHB_CLK>,
1190			    <&mmcc GFX3D_AXI_CLK>,
1191			    <&mmcc MMSS_IMEM_AHB_CLK>;
1192
1193			iommus = <&gfx3d 0
1194				  &gfx3d 1
1195				  &gfx3d 2
1196				  &gfx3d 3
1197				  &gfx3d 4
1198				  &gfx3d 5
1199				  &gfx3d 6
1200				  &gfx3d 7
1201				  &gfx3d 8
1202				  &gfx3d 9
1203				  &gfx3d 10
1204				  &gfx3d 11
1205				  &gfx3d 12
1206				  &gfx3d 13
1207				  &gfx3d 14
1208				  &gfx3d 15
1209				  &gfx3d 16
1210				  &gfx3d 17
1211				  &gfx3d 18
1212				  &gfx3d 19
1213				  &gfx3d 20
1214				  &gfx3d 21
1215				  &gfx3d 22
1216				  &gfx3d 23
1217				  &gfx3d 24
1218				  &gfx3d 25
1219				  &gfx3d 26
1220				  &gfx3d 27
1221				  &gfx3d 28
1222				  &gfx3d 29
1223				  &gfx3d 30
1224				  &gfx3d 31
1225				  &gfx3d1 0
1226				  &gfx3d1 1
1227				  &gfx3d1 2
1228				  &gfx3d1 3
1229				  &gfx3d1 4
1230				  &gfx3d1 5
1231				  &gfx3d1 6
1232				  &gfx3d1 7
1233				  &gfx3d1 8
1234				  &gfx3d1 9
1235				  &gfx3d1 10
1236				  &gfx3d1 11
1237				  &gfx3d1 12
1238				  &gfx3d1 13
1239				  &gfx3d1 14
1240				  &gfx3d1 15
1241				  &gfx3d1 16
1242				  &gfx3d1 17
1243				  &gfx3d1 18
1244				  &gfx3d1 19
1245				  &gfx3d1 20
1246				  &gfx3d1 21
1247				  &gfx3d1 22
1248				  &gfx3d1 23
1249				  &gfx3d1 24
1250				  &gfx3d1 25
1251				  &gfx3d1 26
1252				  &gfx3d1 27
1253				  &gfx3d1 28
1254				  &gfx3d1 29
1255				  &gfx3d1 30
1256				  &gfx3d1 31>;
1257
1258			operating-points-v2 = <&gpu_opp_table>;
1259
1260			gpu_opp_table: opp-table {
1261				compatible = "operating-points-v2";
1262
1263				opp-320000000 {
1264					opp-hz = /bits/ 64 <450000000>;
1265				};
1266
1267				opp-27000000 {
1268					opp-hz = /bits/ 64 <27000000>;
1269				};
1270			};
1271		};
1272
1273		mmss_sfpb: syscon@5700000 {
1274			compatible = "syscon";
1275			reg = <0x5700000 0x70>;
1276		};
1277
1278		dsi0: dsi@4700000 {
1279			compatible = "qcom,apq8064-dsi-ctrl",
1280				     "qcom,mdss-dsi-ctrl";
1281			label = "MDSS DSI CTRL->0";
1282			#address-cells = <1>;
1283			#size-cells = <0>;
1284			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1285			reg = <0x04700000 0x200>;
1286			reg-names = "dsi_ctrl";
1287
1288			clocks = <&mmcc DSI_M_AHB_CLK>,
1289				<&mmcc DSI_S_AHB_CLK>,
1290				<&mmcc AMP_AHB_CLK>,
1291				<&mmcc DSI_CLK>,
1292				<&mmcc DSI1_BYTE_CLK>,
1293				<&mmcc DSI_PIXEL_CLK>,
1294				<&mmcc DSI1_ESC_CLK>;
1295			clock-names = "iface", "bus", "core_mmss",
1296					"src", "byte", "pixel",
1297					"core";
1298
1299			assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1300					<&mmcc DSI1_ESC_SRC>,
1301					<&mmcc DSI_SRC>,
1302					<&mmcc DSI_PIXEL_SRC>;
1303			assigned-clock-parents = <&dsi0_phy 0>,
1304						<&dsi0_phy 0>,
1305						<&dsi0_phy 1>,
1306						<&dsi0_phy 1>;
1307			syscon-sfpb = <&mmss_sfpb>;
1308			phys = <&dsi0_phy>;
1309			status = "disabled";
1310
1311			ports {
1312				#address-cells = <1>;
1313				#size-cells = <0>;
1314
1315				port@0 {
1316					reg = <0>;
1317					dsi0_in: endpoint {
1318					};
1319				};
1320
1321				port@1 {
1322					reg = <1>;
1323					dsi0_out: endpoint {
1324					};
1325				};
1326			};
1327		};
1328
1329
1330		dsi0_phy: phy@4700200 {
1331			compatible = "qcom,dsi-phy-28nm-8960";
1332			#clock-cells = <1>;
1333			#phy-cells = <0>;
1334
1335			reg = <0x04700200 0x100>,
1336				<0x04700300 0x200>,
1337				<0x04700500 0x5c>;
1338			reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1339			clock-names = "iface", "ref";
1340			clocks = <&mmcc DSI_M_AHB_CLK>,
1341				 <&pxo_board>;
1342			status = "disabled";
1343		};
1344
1345		dsi1: dsi@5800000 {
1346			compatible = "qcom,mdss-dsi-ctrl";
1347			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1348			reg = <0x05800000 0x200>;
1349			reg-names = "dsi_ctrl";
1350
1351			clocks = <&mmcc DSI2_M_AHB_CLK>,
1352				 <&mmcc DSI2_S_AHB_CLK>,
1353				 <&mmcc AMP_AHB_CLK>,
1354				 <&mmcc DSI2_CLK>,
1355				 <&mmcc DSI2_BYTE_CLK>,
1356				 <&mmcc DSI2_PIXEL_CLK>,
1357				 <&mmcc DSI2_ESC_CLK>;
1358			clock-names = "iface",
1359				      "bus",
1360				      "core_mmss",
1361				      "src",
1362				      "byte",
1363				      "pixel",
1364				      "core";
1365
1366			assigned-clocks = <&mmcc DSI2_BYTE_SRC>,
1367					  <&mmcc DSI2_ESC_SRC>,
1368					  <&mmcc DSI2_SRC>,
1369					  <&mmcc DSI2_PIXEL_SRC>;
1370			assigned-clock-parents = <&dsi1_phy 0>,
1371						 <&dsi1_phy 0>,
1372						 <&dsi1_phy 1>,
1373						 <&dsi1_phy 1>;
1374
1375			syscon-sfpb = <&mmss_sfpb>;
1376			phys = <&dsi1_phy>;
1377
1378			#address-cells = <1>;
1379			#size-cells = <0>;
1380
1381			status = "disabled";
1382
1383			ports {
1384				#address-cells = <1>;
1385				#size-cells = <0>;
1386
1387				port@0 {
1388					reg = <0>;
1389					dsi1_in: endpoint {
1390					};
1391				};
1392
1393				port@1 {
1394					reg = <1>;
1395					dsi1_out: endpoint {
1396					};
1397				};
1398			};
1399		};
1400
1401
1402		dsi1_phy: dsi-phy@5800200 {
1403			compatible = "qcom,dsi-phy-28nm-8960";
1404			reg = <0x05800200 0x100>,
1405			      <0x05800300 0x200>,
1406			      <0x05800500 0x5c>;
1407			reg-names = "dsi_pll",
1408				    "dsi_phy",
1409				    "dsi_phy_regulator";
1410			clock-names = "iface",
1411				      "ref";
1412			clocks = <&mmcc DSI2_M_AHB_CLK>,
1413				 <&pxo_board>;
1414			#clock-cells = <1>;
1415			#phy-cells = <0>;
1416
1417			status = "disabled";
1418		};
1419
1420		mdp_port0: iommu@7500000 {
1421			compatible = "qcom,apq8064-iommu";
1422			#iommu-cells = <1>;
1423			clock-names =
1424			    "smmu_pclk",
1425			    "iommu_clk";
1426			clocks =
1427			    <&mmcc SMMU_AHB_CLK>,
1428			    <&mmcc MDP_AXI_CLK>;
1429			reg = <0x07500000 0x100000>;
1430			interrupts =
1431			    <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1432			    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1433			qcom,ncb = <2>;
1434		};
1435
1436		mdp_port1: iommu@7600000 {
1437			compatible = "qcom,apq8064-iommu";
1438			#iommu-cells = <1>;
1439			clock-names =
1440			    "smmu_pclk",
1441			    "iommu_clk";
1442			clocks =
1443			    <&mmcc SMMU_AHB_CLK>,
1444			    <&mmcc MDP_AXI_CLK>;
1445			reg = <0x07600000 0x100000>;
1446			interrupts =
1447			    <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1448			    <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1449			qcom,ncb = <2>;
1450		};
1451
1452		gfx3d: iommu@7c00000 {
1453			compatible = "qcom,apq8064-iommu";
1454			#iommu-cells = <1>;
1455			clock-names =
1456			    "smmu_pclk",
1457			    "iommu_clk";
1458			clocks =
1459			    <&mmcc SMMU_AHB_CLK>,
1460			    <&mmcc GFX3D_AXI_CLK>;
1461			reg = <0x07c00000 0x100000>;
1462			interrupts =
1463			    <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1464			    <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1465			qcom,ncb = <3>;
1466		};
1467
1468		gfx3d1: iommu@7d00000 {
1469			compatible = "qcom,apq8064-iommu";
1470			#iommu-cells = <1>;
1471			clock-names =
1472			    "smmu_pclk",
1473			    "iommu_clk";
1474			clocks =
1475			    <&mmcc SMMU_AHB_CLK>,
1476			    <&mmcc GFX3D_AXI_CLK>;
1477			reg = <0x07d00000 0x100000>;
1478			interrupts =
1479			    <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1480			    <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1481			qcom,ncb = <3>;
1482		};
1483
1484		pcie: pci@1b500000 {
1485			compatible = "qcom,pcie-apq8064";
1486			reg = <0x1b500000 0x1000>,
1487			      <0x1b502000 0x80>,
1488			      <0x1b600000 0x100>,
1489			      <0x0ff00000 0x100000>;
1490			reg-names = "dbi", "elbi", "parf", "config";
1491			device_type = "pci";
1492			linux,pci-domain = <0>;
1493			bus-range = <0x00 0xff>;
1494			num-lanes = <1>;
1495			#address-cells = <3>;
1496			#size-cells = <2>;
1497			ranges = <0x81000000 0 0          0x0fe00000 0 0x00100000>, /* I/O */
1498				 <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */
1499			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1500			interrupt-names = "msi";
1501			#interrupt-cells = <1>;
1502			interrupt-map-mask = <0 0 0 0x7>;
1503			interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1504					<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1505					<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1506					<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1507			clocks = <&gcc PCIE_A_CLK>,
1508				 <&gcc PCIE_H_CLK>,
1509				 <&gcc PCIE_PHY_REF_CLK>;
1510			clock-names = "core", "iface", "phy";
1511			resets = <&gcc PCIE_ACLK_RESET>,
1512				 <&gcc PCIE_HCLK_RESET>,
1513				 <&gcc PCIE_POR_RESET>,
1514				 <&gcc PCIE_PCI_RESET>,
1515				 <&gcc PCIE_PHY_RESET>;
1516			reset-names = "axi", "ahb", "por", "pci", "phy";
1517			status = "disabled";
1518		};
1519
1520		hdmi: hdmi-tx@4a00000 {
1521			compatible = "qcom,hdmi-tx-8960";
1522			pinctrl-names = "default";
1523			pinctrl-0 = <&hdmi_pinctrl>;
1524			reg = <0x04a00000 0x2f0>;
1525			reg-names = "core_physical";
1526			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1527			clocks = <&mmcc HDMI_APP_CLK>,
1528				 <&mmcc HDMI_M_AHB_CLK>,
1529				 <&mmcc HDMI_S_AHB_CLK>;
1530			clock-names = "core",
1531				      "master_iface",
1532				      "slave_iface";
1533
1534			phys = <&hdmi_phy>;
1535
1536			status = "disabled";
1537
1538			ports {
1539				#address-cells = <1>;
1540				#size-cells = <0>;
1541
1542				port@0 {
1543					reg = <0>;
1544					hdmi_in: endpoint {
1545					};
1546				};
1547
1548				port@1 {
1549					reg = <1>;
1550					hdmi_out: endpoint {
1551					};
1552				};
1553			};
1554		};
1555
1556		hdmi_phy: phy@4a00400 {
1557			compatible = "qcom,hdmi-phy-8960";
1558			reg = <0x4a00400 0x60>,
1559			      <0x4a00500 0x100>;
1560			reg-names = "hdmi_phy",
1561				    "hdmi_pll";
1562
1563			clocks = <&mmcc HDMI_S_AHB_CLK>;
1564			clock-names = "slave_iface";
1565			#phy-cells = <0>;
1566			#clock-cells = <0>;
1567
1568			status = "disabled";
1569		};
1570
1571		mdp: display-controller@5100000 {
1572			compatible = "qcom,mdp4";
1573			reg = <0x05100000 0xf0000>;
1574			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1575			clocks = <&mmcc MDP_CLK>,
1576				 <&mmcc MDP_AHB_CLK>,
1577				 <&mmcc MDP_AXI_CLK>,
1578				 <&mmcc MDP_LUT_CLK>,
1579				 <&mmcc HDMI_TV_CLK>,
1580				 <&mmcc MDP_TV_CLK>;
1581			clock-names = "core_clk",
1582				      "iface_clk",
1583				      "bus_clk",
1584				      "lut_clk",
1585				      "hdmi_clk",
1586				      "tv_clk";
1587
1588			iommus = <&mdp_port0 0
1589				  &mdp_port0 2
1590				  &mdp_port1 0
1591				  &mdp_port1 2>;
1592
1593			ports {
1594				#address-cells = <1>;
1595				#size-cells = <0>;
1596
1597				port@0 {
1598					reg = <0>;
1599					mdp_lvds_out: endpoint {
1600					};
1601				};
1602
1603				port@1 {
1604					reg = <1>;
1605					mdp_dsi1_out: endpoint {
1606					};
1607				};
1608
1609				port@2 {
1610					reg = <2>;
1611					mdp_dsi2_out: endpoint {
1612					};
1613				};
1614
1615				port@3 {
1616					reg = <3>;
1617					mdp_dtv_out: endpoint {
1618					};
1619				};
1620			};
1621		};
1622
1623		riva: riva-pil@3200800 {
1624			compatible = "qcom,riva-pil";
1625
1626			reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1627			reg-names = "ccu", "dxe", "pmu";
1628
1629			interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1630					      <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1631			interrupt-names = "wdog", "fatal";
1632
1633			memory-region = <&wcnss_mem>;
1634
1635			vddcx-supply = <&pm8921_s3>;
1636			vddmx-supply = <&pm8921_l24>;
1637			vddpx-supply = <&pm8921_s4>;
1638
1639			status = "disabled";
1640
1641			iris {
1642				compatible = "qcom,wcn3660";
1643
1644				clocks = <&cxo_board>;
1645				clock-names = "xo";
1646
1647				vddxo-supply = <&pm8921_l4>;
1648				vddrfa-supply = <&pm8921_s2>;
1649				vddpa-supply = <&pm8921_l10>;
1650				vdddig-supply = <&pm8921_lvs2>;
1651			};
1652
1653			smd-edge {
1654				interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1655
1656				qcom,ipc = <&l2cc 8 25>;
1657				qcom,smd-edge = <6>;
1658
1659				label = "riva";
1660
1661				wcnss {
1662					compatible = "qcom,wcnss";
1663					qcom,smd-channels = "WCNSS_CTRL";
1664
1665					qcom,mmio = <&riva>;
1666
1667					bluetooth {
1668						compatible = "qcom,wcnss-bt";
1669					};
1670
1671					wifi {
1672						compatible = "qcom,wcnss-wlan";
1673
1674						interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1675							     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1676						interrupt-names = "tx", "rx";
1677
1678						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1679						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1680					};
1681				};
1682			};
1683		};
1684
1685		etb@1a01000 {
1686			compatible = "arm,coresight-etb10", "arm,primecell";
1687			reg = <0x1a01000 0x1000>;
1688
1689			clocks = <&rpmcc RPM_QDSS_CLK>;
1690			clock-names = "apb_pclk";
1691
1692			in-ports {
1693				port {
1694					etb_in: endpoint {
1695						remote-endpoint = <&replicator_out0>;
1696					};
1697				};
1698			};
1699		};
1700
1701		tpiu@1a03000 {
1702			compatible = "arm,coresight-tpiu", "arm,primecell";
1703			reg = <0x1a03000 0x1000>;
1704
1705			clocks = <&rpmcc RPM_QDSS_CLK>;
1706			clock-names = "apb_pclk";
1707
1708			in-ports {
1709				port {
1710					tpiu_in: endpoint {
1711						remote-endpoint = <&replicator_out1>;
1712					};
1713				};
1714			};
1715		};
1716
1717		replicator {
1718			compatible = "arm,coresight-static-replicator";
1719
1720			clocks = <&rpmcc RPM_QDSS_CLK>;
1721			clock-names = "apb_pclk";
1722
1723			out-ports {
1724				#address-cells = <1>;
1725				#size-cells = <0>;
1726
1727				port@0 {
1728					reg = <0>;
1729					replicator_out0: endpoint {
1730						remote-endpoint = <&etb_in>;
1731					};
1732				};
1733				port@1 {
1734					reg = <1>;
1735					replicator_out1: endpoint {
1736						remote-endpoint = <&tpiu_in>;
1737					};
1738				};
1739			};
1740
1741			in-ports {
1742				port {
1743					replicator_in: endpoint {
1744						remote-endpoint = <&funnel_out>;
1745					};
1746				};
1747			};
1748		};
1749
1750		funnel@1a04000 {
1751			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1752			reg = <0x1a04000 0x1000>;
1753
1754			clocks = <&rpmcc RPM_QDSS_CLK>;
1755			clock-names = "apb_pclk";
1756
1757			in-ports {
1758				#address-cells = <1>;
1759				#size-cells = <0>;
1760
1761				/*
1762				 * Not described input ports:
1763				 * 2 - connected to STM component
1764				 * 3 - not-connected
1765				 * 6 - not-connected
1766				 * 7 - not-connected
1767				 */
1768				port@0 {
1769					reg = <0>;
1770					funnel_in0: endpoint {
1771						remote-endpoint = <&etm0_out>;
1772					};
1773				};
1774				port@1 {
1775					reg = <1>;
1776					funnel_in1: endpoint {
1777						remote-endpoint = <&etm1_out>;
1778					};
1779				};
1780				port@4 {
1781					reg = <4>;
1782					funnel_in4: endpoint {
1783						remote-endpoint = <&etm2_out>;
1784					};
1785				};
1786				port@5 {
1787					reg = <5>;
1788					funnel_in5: endpoint {
1789						remote-endpoint = <&etm3_out>;
1790					};
1791				};
1792			};
1793
1794			out-ports {
1795				port {
1796					funnel_out: endpoint {
1797						remote-endpoint = <&replicator_in>;
1798					};
1799				};
1800			};
1801		};
1802
1803		etm@1a1c000 {
1804			compatible = "arm,coresight-etm3x", "arm,primecell";
1805			reg = <0x1a1c000 0x1000>;
1806
1807			clocks = <&rpmcc RPM_QDSS_CLK>;
1808			clock-names = "apb_pclk";
1809
1810			cpu = <&CPU0>;
1811
1812			out-ports {
1813				port {
1814					etm0_out: endpoint {
1815						remote-endpoint = <&funnel_in0>;
1816					};
1817				};
1818			};
1819		};
1820
1821		etm@1a1d000 {
1822			compatible = "arm,coresight-etm3x", "arm,primecell";
1823			reg = <0x1a1d000 0x1000>;
1824
1825			clocks = <&rpmcc RPM_QDSS_CLK>;
1826			clock-names = "apb_pclk";
1827
1828			cpu = <&CPU1>;
1829
1830			out-ports {
1831				port {
1832					etm1_out: endpoint {
1833						remote-endpoint = <&funnel_in1>;
1834					};
1835				};
1836			};
1837		};
1838
1839		etm@1a1e000 {
1840			compatible = "arm,coresight-etm3x", "arm,primecell";
1841			reg = <0x1a1e000 0x1000>;
1842
1843			clocks = <&rpmcc RPM_QDSS_CLK>;
1844			clock-names = "apb_pclk";
1845
1846			cpu = <&CPU2>;
1847
1848			out-ports {
1849				port {
1850					etm2_out: endpoint {
1851						remote-endpoint = <&funnel_in4>;
1852					};
1853				};
1854			};
1855		};
1856
1857		etm@1a1f000 {
1858			compatible = "arm,coresight-etm3x", "arm,primecell";
1859			reg = <0x1a1f000 0x1000>;
1860
1861			clocks = <&rpmcc RPM_QDSS_CLK>;
1862			clock-names = "apb_pclk";
1863
1864			cpu = <&CPU3>;
1865
1866			out-ports {
1867				port {
1868					etm3_out: endpoint {
1869						remote-endpoint = <&funnel_in5>;
1870					};
1871				};
1872			};
1873		};
1874	};
1875};
1876#include "qcom-apq8064-pins.dtsi"
1877