1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mfd/qcom-rpm.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,gcc-ipq806x.h> 8#include <dt-bindings/clock/qcom,lcc-ipq806x.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/reset/qcom,gcc-ipq806x.h> 11#include <dt-bindings/soc/qcom,gsbi.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Qualcomm IPQ8064"; 18 compatible = "qcom,ipq8064"; 19 interrupt-parent = <&intc>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "qcom,krait"; 27 enable-method = "qcom,kpss-acc-v1"; 28 device_type = "cpu"; 29 reg = <0>; 30 next-level-cache = <&L2>; 31 qcom,acc = <&acc0>; 32 qcom,saw = <&saw0>; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "qcom,krait"; 37 enable-method = "qcom,kpss-acc-v1"; 38 device_type = "cpu"; 39 reg = <1>; 40 next-level-cache = <&L2>; 41 qcom,acc = <&acc1>; 42 qcom,saw = <&saw1>; 43 }; 44 45 L2: l2-cache { 46 compatible = "cache"; 47 cache-level = <2>; 48 }; 49 }; 50 51 thermal-zones { 52 sensor0-thermal { 53 polling-delay-passive = <0>; 54 polling-delay = <0>; 55 thermal-sensors = <&tsens 0>; 56 57 trips { 58 cpu-critical { 59 temperature = <105000>; 60 hysteresis = <2000>; 61 type = "critical"; 62 }; 63 64 cpu-hot { 65 temperature = <95000>; 66 hysteresis = <2000>; 67 type = "hot"; 68 }; 69 }; 70 }; 71 72 sensor1-thermal { 73 polling-delay-passive = <0>; 74 polling-delay = <0>; 75 thermal-sensors = <&tsens 1>; 76 77 trips { 78 cpu-critical { 79 temperature = <105000>; 80 hysteresis = <2000>; 81 type = "critical"; 82 }; 83 84 cpu-hot { 85 temperature = <95000>; 86 hysteresis = <2000>; 87 type = "hot"; 88 }; 89 }; 90 }; 91 92 sensor2-thermal { 93 polling-delay-passive = <0>; 94 polling-delay = <0>; 95 thermal-sensors = <&tsens 2>; 96 97 trips { 98 cpu-critical { 99 temperature = <105000>; 100 hysteresis = <2000>; 101 type = "critical"; 102 }; 103 104 cpu-hot { 105 temperature = <95000>; 106 hysteresis = <2000>; 107 type = "hot"; 108 }; 109 }; 110 }; 111 112 sensor3-thermal { 113 polling-delay-passive = <0>; 114 polling-delay = <0>; 115 thermal-sensors = <&tsens 3>; 116 117 trips { 118 cpu-critical { 119 temperature = <105000>; 120 hysteresis = <2000>; 121 type = "critical"; 122 }; 123 124 cpu-hot { 125 temperature = <95000>; 126 hysteresis = <2000>; 127 type = "hot"; 128 }; 129 }; 130 }; 131 132 sensor4-thermal { 133 polling-delay-passive = <0>; 134 polling-delay = <0>; 135 thermal-sensors = <&tsens 4>; 136 137 trips { 138 cpu-critical { 139 temperature = <105000>; 140 hysteresis = <2000>; 141 type = "critical"; 142 }; 143 144 cpu-hot { 145 temperature = <95000>; 146 hysteresis = <2000>; 147 type = "hot"; 148 }; 149 }; 150 }; 151 152 sensor5-thermal { 153 polling-delay-passive = <0>; 154 polling-delay = <0>; 155 thermal-sensors = <&tsens 5>; 156 157 trips { 158 cpu-critical { 159 temperature = <105000>; 160 hysteresis = <2000>; 161 type = "critical"; 162 }; 163 164 cpu-hot { 165 temperature = <95000>; 166 hysteresis = <2000>; 167 type = "hot"; 168 }; 169 }; 170 }; 171 172 sensor6-thermal { 173 polling-delay-passive = <0>; 174 polling-delay = <0>; 175 thermal-sensors = <&tsens 6>; 176 177 trips { 178 cpu-critical { 179 temperature = <105000>; 180 hysteresis = <2000>; 181 type = "critical"; 182 }; 183 184 cpu-hot { 185 temperature = <95000>; 186 hysteresis = <2000>; 187 type = "hot"; 188 }; 189 }; 190 }; 191 192 sensor7-thermal { 193 polling-delay-passive = <0>; 194 polling-delay = <0>; 195 thermal-sensors = <&tsens 7>; 196 197 trips { 198 cpu-critical { 199 temperature = <105000>; 200 hysteresis = <2000>; 201 type = "critical"; 202 }; 203 204 cpu-hot { 205 temperature = <95000>; 206 hysteresis = <2000>; 207 type = "hot"; 208 }; 209 }; 210 }; 211 212 sensor8-thermal { 213 polling-delay-passive = <0>; 214 polling-delay = <0>; 215 thermal-sensors = <&tsens 8>; 216 217 trips { 218 cpu-critical { 219 temperature = <105000>; 220 hysteresis = <2000>; 221 type = "critical"; 222 }; 223 224 cpu-hot { 225 temperature = <95000>; 226 hysteresis = <2000>; 227 type = "hot"; 228 }; 229 }; 230 }; 231 232 sensor9-thermal { 233 polling-delay-passive = <0>; 234 polling-delay = <0>; 235 thermal-sensors = <&tsens 9>; 236 237 trips { 238 cpu-critical { 239 temperature = <105000>; 240 hysteresis = <2000>; 241 type = "critical"; 242 }; 243 244 cpu-hot { 245 temperature = <95000>; 246 hysteresis = <2000>; 247 type = "hot"; 248 }; 249 }; 250 }; 251 252 sensor10-thermal { 253 polling-delay-passive = <0>; 254 polling-delay = <0>; 255 thermal-sensors = <&tsens 10>; 256 257 trips { 258 cpu-critical { 259 temperature = <105000>; 260 hysteresis = <2000>; 261 type = "critical"; 262 }; 263 264 cpu-hot { 265 temperature = <95000>; 266 hysteresis = <2000>; 267 type = "hot"; 268 }; 269 }; 270 }; 271 }; 272 273 memory { 274 device_type = "memory"; 275 reg = <0x0 0x0>; 276 }; 277 278 cpu-pmu { 279 compatible = "qcom,krait-pmu"; 280 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 281 IRQ_TYPE_LEVEL_HIGH)>; 282 }; 283 284 reserved-memory { 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges; 288 289 nss@40000000 { 290 reg = <0x40000000 0x1000000>; 291 no-map; 292 }; 293 294 smem: smem@41000000 { 295 compatible = "qcom,smem"; 296 reg = <0x41000000 0x200000>; 297 no-map; 298 299 hwlocks = <&sfpb_mutex 3>; 300 }; 301 }; 302 303 clocks { 304 cxo_board: cxo_board { 305 compatible = "fixed-clock"; 306 #clock-cells = <0>; 307 clock-frequency = <25000000>; 308 }; 309 310 pxo_board: pxo_board { 311 compatible = "fixed-clock"; 312 #clock-cells = <0>; 313 clock-frequency = <25000000>; 314 }; 315 316 sleep_clk: sleep_clk { 317 compatible = "fixed-clock"; 318 clock-frequency = <32768>; 319 #clock-cells = <0>; 320 }; 321 }; 322 323 firmware { 324 scm { 325 compatible = "qcom,scm-ipq806x", "qcom,scm"; 326 }; 327 }; 328 329 stmmac_axi_setup: stmmac-axi-config { 330 snps,wr_osr_lmt = <7>; 331 snps,rd_osr_lmt = <7>; 332 snps,blen = <16 0 0 0 0 0 0>; 333 }; 334 335 vsdcc_fixed: vsdcc-regulator { 336 compatible = "regulator-fixed"; 337 regulator-name = "SDCC Power"; 338 regulator-min-microvolt = <3300000>; 339 regulator-max-microvolt = <3300000>; 340 regulator-always-on; 341 }; 342 343 soc: soc { 344 #address-cells = <1>; 345 #size-cells = <1>; 346 ranges; 347 compatible = "simple-bus"; 348 349 rpm: rpm@108000 { 350 compatible = "qcom,rpm-ipq8064"; 351 reg = <0x00108000 0x1000>; 352 qcom,ipc = <&l2cc 0x8 2>; 353 354 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-names = "ack", "err", "wakeup"; 358 359 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 360 clock-names = "ram"; 361 362 rpmcc: clock-controller { 363 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; 364 #clock-cells = <1>; 365 }; 366 }; 367 368 qcom,ssbi@500000 { 369 compatible = "qcom,ssbi"; 370 reg = <0x00500000 0x1000>; 371 qcom,controller-type = "pmic-arbiter"; 372 }; 373 374 qfprom: qfprom@700000 { 375 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; 376 reg = <0x00700000 0x1000>; 377 #address-cells = <1>; 378 #size-cells = <1>; 379 speedbin_efuse: speedbin@c0 { 380 reg = <0xc0 0x4>; 381 }; 382 tsens_calib: calib@400 { 383 reg = <0x400 0xb>; 384 }; 385 tsens_calib_backup: calib_backup@410 { 386 reg = <0x410 0xb>; 387 }; 388 }; 389 390 qcom_pinmux: pinmux@800000 { 391 compatible = "qcom,ipq8064-pinctrl"; 392 reg = <0x00800000 0x4000>; 393 394 gpio-controller; 395 gpio-ranges = <&qcom_pinmux 0 0 69>; 396 #gpio-cells = <2>; 397 interrupt-controller; 398 #interrupt-cells = <2>; 399 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 400 401 pcie0_pins: pcie0_pinmux { 402 mux { 403 pins = "gpio3"; 404 function = "pcie1_rst"; 405 drive-strength = <12>; 406 bias-disable; 407 }; 408 }; 409 410 pcie1_pins: pcie1_pinmux { 411 mux { 412 pins = "gpio48"; 413 function = "pcie2_rst"; 414 drive-strength = <12>; 415 bias-disable; 416 }; 417 }; 418 419 pcie2_pins: pcie2_pinmux { 420 mux { 421 pins = "gpio63"; 422 function = "pcie3_rst"; 423 drive-strength = <12>; 424 bias-disable; 425 }; 426 }; 427 428 i2c4_pins: i2c4-default { 429 pins = "gpio12", "gpio13"; 430 function = "gsbi4"; 431 drive-strength = <12>; 432 bias-disable; 433 }; 434 435 spi_pins: spi_pins { 436 mux { 437 pins = "gpio18", "gpio19", "gpio21"; 438 function = "gsbi5"; 439 drive-strength = <10>; 440 bias-none; 441 }; 442 }; 443 444 leds_pins: leds_pins { 445 mux { 446 pins = "gpio7", "gpio8", "gpio9", 447 "gpio26", "gpio53"; 448 function = "gpio"; 449 drive-strength = <2>; 450 bias-pull-down; 451 output-low; 452 }; 453 }; 454 455 buttons_pins: buttons_pins { 456 mux { 457 pins = "gpio54"; 458 drive-strength = <2>; 459 bias-pull-up; 460 }; 461 }; 462 463 nand_pins: nand_pins { 464 mux { 465 pins = "gpio34", "gpio35", "gpio36", 466 "gpio37", "gpio38", "gpio39", 467 "gpio40", "gpio41", "gpio42", 468 "gpio43", "gpio44", "gpio45", 469 "gpio46", "gpio47"; 470 function = "nand"; 471 drive-strength = <10>; 472 bias-disable; 473 }; 474 475 pullups { 476 pins = "gpio39"; 477 function = "nand"; 478 drive-strength = <10>; 479 bias-pull-up; 480 }; 481 482 hold { 483 pins = "gpio40", "gpio41", "gpio42", 484 "gpio43", "gpio44", "gpio45", 485 "gpio46", "gpio47"; 486 function = "nand"; 487 drive-strength = <10>; 488 bias-bus-hold; 489 }; 490 }; 491 492 mdio0_pins: mdio0-pins { 493 mux { 494 pins = "gpio0", "gpio1"; 495 function = "mdio"; 496 drive-strength = <8>; 497 bias-disable; 498 }; 499 }; 500 501 rgmii2_pins: rgmii2-pins { 502 mux { 503 pins = "gpio27", "gpio28", "gpio29", 504 "gpio30", "gpio31", "gpio32", 505 "gpio51", "gpio52", "gpio59", 506 "gpio60", "gpio61", "gpio62"; 507 function = "rgmii2"; 508 drive-strength = <8>; 509 bias-disable; 510 }; 511 }; 512 }; 513 514 gcc: clock-controller@900000 { 515 compatible = "qcom,gcc-ipq8064", "syscon"; 516 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>; 517 clock-names = "pxo", "cxo", "pll4"; 518 reg = <0x00900000 0x4000>; 519 #clock-cells = <1>; 520 #reset-cells = <1>; 521 #power-domain-cells = <1>; 522 523 tsens: thermal-sensor@900000 { 524 compatible = "qcom,ipq8064-tsens"; 525 526 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 527 nvmem-cell-names = "calib", "calib_backup"; 528 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 529 interrupt-names = "uplow"; 530 531 #qcom,sensors = <11>; 532 #thermal-sensor-cells = <1>; 533 }; 534 }; 535 536 sfpb_mutex: hwlock@1200600 { 537 compatible = "qcom,sfpb-mutex"; 538 reg = <0x01200600 0x100>; 539 540 #hwlock-cells = <1>; 541 }; 542 543 intc: interrupt-controller@2000000 { 544 compatible = "qcom,msm-qgic2"; 545 interrupt-controller; 546 #interrupt-cells = <3>; 547 reg = <0x02000000 0x1000>, 548 <0x02002000 0x1000>; 549 }; 550 551 timer@200a000 { 552 compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", 553 "qcom,msm-timer"; 554 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | 555 IRQ_TYPE_EDGE_RISING)>, 556 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | 557 IRQ_TYPE_EDGE_RISING)>, 558 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | 559 IRQ_TYPE_EDGE_RISING)>, 560 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | 561 IRQ_TYPE_EDGE_RISING)>, 562 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | 563 IRQ_TYPE_EDGE_RISING)>; 564 reg = <0x0200a000 0x100>; 565 clock-frequency = <25000000>; 566 clocks = <&sleep_clk>; 567 clock-names = "sleep"; 568 cpu-offset = <0x80000>; 569 }; 570 571 l2cc: clock-controller@2011000 { 572 compatible = "qcom,kpss-gcc", "syscon"; 573 reg = <0x02011000 0x1000>; 574 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 575 clock-names = "pll8_vote", "pxo"; 576 clock-output-names = "acpu_l2_aux"; 577 }; 578 579 acc0: clock-controller@2088000 { 580 compatible = "qcom,kpss-acc-v1"; 581 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 582 }; 583 584 saw0: regulator@2089000 { 585 compatible = "qcom,saw2"; 586 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 587 regulator; 588 }; 589 590 acc1: clock-controller@2098000 { 591 compatible = "qcom,kpss-acc-v1"; 592 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 593 }; 594 595 saw1: regulator@2099000 { 596 compatible = "qcom,saw2"; 597 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 598 regulator; 599 }; 600 601 nss_common: syscon@03000000 { 602 compatible = "syscon"; 603 reg = <0x03000000 0x0000FFFF>; 604 }; 605 606 usb3_0: usb3@100f8800 { 607 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; 608 #address-cells = <1>; 609 #size-cells = <1>; 610 reg = <0x100f8800 0x8000>; 611 clocks = <&gcc USB30_0_MASTER_CLK>; 612 clock-names = "core"; 613 614 ranges; 615 616 resets = <&gcc USB30_0_MASTER_RESET>; 617 reset-names = "master"; 618 619 status = "disabled"; 620 621 dwc3_0: dwc3@10000000 { 622 compatible = "snps,dwc3"; 623 reg = <0x10000000 0xcd00>; 624 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 625 phys = <&hs_phy_0>, <&ss_phy_0>; 626 phy-names = "usb2-phy", "usb3-phy"; 627 dr_mode = "host"; 628 snps,dis_u3_susphy_quirk; 629 }; 630 }; 631 632 hs_phy_0: phy@100f8800 { 633 compatible = "qcom,ipq806x-usb-phy-hs"; 634 reg = <0x100f8800 0x30>; 635 clocks = <&gcc USB30_0_UTMI_CLK>; 636 clock-names = "ref"; 637 #phy-cells = <0>; 638 639 status = "disabled"; 640 }; 641 642 ss_phy_0: phy@100f8830 { 643 compatible = "qcom,ipq806x-usb-phy-ss"; 644 reg = <0x100f8830 0x30>; 645 clocks = <&gcc USB30_0_MASTER_CLK>; 646 clock-names = "ref"; 647 #phy-cells = <0>; 648 649 status = "disabled"; 650 }; 651 652 usb3_1: usb3@110f8800 { 653 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; 654 #address-cells = <1>; 655 #size-cells = <1>; 656 reg = <0x110f8800 0x8000>; 657 clocks = <&gcc USB30_1_MASTER_CLK>; 658 clock-names = "core"; 659 660 ranges; 661 662 resets = <&gcc USB30_1_MASTER_RESET>; 663 reset-names = "master"; 664 665 status = "disabled"; 666 667 dwc3_1: dwc3@11000000 { 668 compatible = "snps,dwc3"; 669 reg = <0x11000000 0xcd00>; 670 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 671 phys = <&hs_phy_1>, <&ss_phy_1>; 672 phy-names = "usb2-phy", "usb3-phy"; 673 dr_mode = "host"; 674 snps,dis_u3_susphy_quirk; 675 }; 676 }; 677 678 hs_phy_1: phy@110f8800 { 679 compatible = "qcom,ipq806x-usb-phy-hs"; 680 reg = <0x110f8800 0x30>; 681 clocks = <&gcc USB30_1_UTMI_CLK>; 682 clock-names = "ref"; 683 #phy-cells = <0>; 684 685 status = "disabled"; 686 }; 687 688 ss_phy_1: phy@110f8830 { 689 compatible = "qcom,ipq806x-usb-phy-ss"; 690 reg = <0x110f8830 0x30>; 691 clocks = <&gcc USB30_1_MASTER_CLK>; 692 clock-names = "ref"; 693 #phy-cells = <0>; 694 695 status = "disabled"; 696 }; 697 698 sdcc3bam: dma-controller@12182000 { 699 compatible = "qcom,bam-v1.3.0"; 700 reg = <0x12182000 0x8000>; 701 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&gcc SDC3_H_CLK>; 703 clock-names = "bam_clk"; 704 #dma-cells = <1>; 705 qcom,ee = <0>; 706 }; 707 708 sdcc1bam: dma-controller@12402000 { 709 compatible = "qcom,bam-v1.3.0"; 710 reg = <0x12402000 0x8000>; 711 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&gcc SDC1_H_CLK>; 713 clock-names = "bam_clk"; 714 #dma-cells = <1>; 715 qcom,ee = <0>; 716 }; 717 718 amba: amba { 719 compatible = "simple-bus"; 720 #address-cells = <1>; 721 #size-cells = <1>; 722 ranges; 723 724 sdcc3: mmc@12180000 { 725 compatible = "arm,pl18x", "arm,primecell"; 726 arm,primecell-periphid = <0x00051180>; 727 status = "disabled"; 728 reg = <0x12180000 0x2000>; 729 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 731 clock-names = "mclk", "apb_pclk"; 732 bus-width = <8>; 733 cap-sd-highspeed; 734 cap-mmc-highspeed; 735 max-frequency = <192000000>; 736 sd-uhs-sdr104; 737 sd-uhs-ddr50; 738 vqmmc-supply = <&vsdcc_fixed>; 739 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 740 dma-names = "tx", "rx"; 741 }; 742 743 sdcc1: mmc@12400000 { 744 status = "disabled"; 745 compatible = "arm,pl18x", "arm,primecell"; 746 arm,primecell-periphid = <0x00051180>; 747 reg = <0x12400000 0x2000>; 748 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 750 clock-names = "mclk", "apb_pclk"; 751 bus-width = <8>; 752 max-frequency = <96000000>; 753 non-removable; 754 cap-sd-highspeed; 755 cap-mmc-highspeed; 756 vmmc-supply = <&vsdcc_fixed>; 757 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 758 dma-names = "tx", "rx"; 759 }; 760 }; 761 762 gsbi1: gsbi@12440000 { 763 compatible = "qcom,gsbi-v1.0.0"; 764 reg = <0x12440000 0x100>; 765 cell-index = <1>; 766 clocks = <&gcc GSBI1_H_CLK>; 767 clock-names = "iface"; 768 #address-cells = <1>; 769 #size-cells = <1>; 770 ranges; 771 772 syscon-tcsr = <&tcsr>; 773 774 status = "disabled"; 775 776 gsbi1_serial: serial@12450000 { 777 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 778 reg = <0x12450000 0x100>, 779 <0x12400000 0x03>; 780 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 782 clock-names = "core", "iface"; 783 784 status = "disabled"; 785 }; 786 787 gsbi1_i2c: i2c@12460000 { 788 compatible = "qcom,i2c-qup-v1.1.1"; 789 reg = <0x12460000 0x1000>; 790 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 792 clock-names = "core", "iface"; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 796 status = "disabled"; 797 }; 798 }; 799 800 gsbi2: gsbi@12480000 { 801 compatible = "qcom,gsbi-v1.0.0"; 802 cell-index = <2>; 803 reg = <0x12480000 0x100>; 804 clocks = <&gcc GSBI2_H_CLK>; 805 clock-names = "iface"; 806 #address-cells = <1>; 807 #size-cells = <1>; 808 ranges; 809 status = "disabled"; 810 811 syscon-tcsr = <&tcsr>; 812 813 gsbi2_serial: serial@12490000 { 814 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 815 reg = <0x12490000 0x1000>, 816 <0x12480000 0x1000>; 817 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; 819 clock-names = "core", "iface"; 820 status = "disabled"; 821 }; 822 823 gsbi2_i2c: i2c@124a0000 { 824 compatible = "qcom,i2c-qup-v1.1.1"; 825 reg = <0x124a0000 0x1000>; 826 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 827 828 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 829 clock-names = "core", "iface"; 830 status = "disabled"; 831 832 #address-cells = <1>; 833 #size-cells = <0>; 834 }; 835 }; 836 837 gsbi4: gsbi@16300000 { 838 compatible = "qcom,gsbi-v1.0.0"; 839 cell-index = <4>; 840 reg = <0x16300000 0x100>; 841 clocks = <&gcc GSBI4_H_CLK>; 842 clock-names = "iface"; 843 #address-cells = <1>; 844 #size-cells = <1>; 845 ranges; 846 status = "disabled"; 847 848 syscon-tcsr = <&tcsr>; 849 850 gsbi4_serial: serial@16340000 { 851 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 852 reg = <0x16340000 0x1000>, 853 <0x16300000 0x1000>; 854 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 856 clock-names = "core", "iface"; 857 status = "disabled"; 858 }; 859 860 i2c@16380000 { 861 compatible = "qcom,i2c-qup-v1.1.1"; 862 reg = <0x16380000 0x1000>; 863 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 864 865 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; 866 clock-names = "core", "iface"; 867 status = "disabled"; 868 869 #address-cells = <1>; 870 #size-cells = <0>; 871 }; 872 }; 873 874 gsbi6: gsbi@16500000 { 875 compatible = "qcom,gsbi-v1.0.0"; 876 reg = <0x16500000 0x100>; 877 cell-index = <6>; 878 clocks = <&gcc GSBI6_H_CLK>; 879 clock-names = "iface"; 880 #address-cells = <1>; 881 #size-cells = <1>; 882 ranges; 883 884 syscon-tcsr = <&tcsr>; 885 886 status = "disabled"; 887 888 gsbi6_i2c: i2c@16580000 { 889 compatible = "qcom,i2c-qup-v1.1.1"; 890 reg = <0x16580000 0x1000>; 891 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 892 893 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 894 clock-names = "core", "iface"; 895 896 #address-cells = <1>; 897 #size-cells = <0>; 898 899 status = "disabled"; 900 }; 901 902 gsbi6_spi: spi@16580000 { 903 compatible = "qcom,spi-qup-v1.1.1"; 904 reg = <0x16580000 0x1000>; 905 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 906 907 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 908 clock-names = "core", "iface"; 909 910 #address-cells = <1>; 911 #size-cells = <0>; 912 913 status = "disabled"; 914 }; 915 }; 916 917 gsbi7: gsbi@16600000 { 918 status = "disabled"; 919 compatible = "qcom,gsbi-v1.0.0"; 920 cell-index = <7>; 921 reg = <0x16600000 0x100>; 922 clocks = <&gcc GSBI7_H_CLK>; 923 clock-names = "iface"; 924 #address-cells = <1>; 925 #size-cells = <1>; 926 ranges; 927 syscon-tcsr = <&tcsr>; 928 929 gsbi7_serial: serial@16640000 { 930 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 931 reg = <0x16640000 0x1000>, 932 <0x16600000 0x1000>; 933 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 935 clock-names = "core", "iface"; 936 status = "disabled"; 937 }; 938 939 gsbi7_i2c: i2c@16680000 { 940 compatible = "qcom,i2c-qup-v1.1.1"; 941 reg = <0x16680000 0x1000>; 942 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 943 944 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; 945 clock-names = "core", "iface"; 946 947 #address-cells = <1>; 948 #size-cells = <0>; 949 950 status = "disabled"; 951 }; 952 }; 953 954 adm_dma: dma-controller@18300000 { 955 compatible = "qcom,adm"; 956 reg = <0x18300000 0x100000>; 957 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 958 #dma-cells = <1>; 959 960 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; 961 clock-names = "core", "iface"; 962 963 resets = <&gcc ADM0_RESET>, 964 <&gcc ADM0_PBUS_RESET>, 965 <&gcc ADM0_C0_RESET>, 966 <&gcc ADM0_C1_RESET>, 967 <&gcc ADM0_C2_RESET>; 968 reset-names = "clk", "pbus", "c0", "c1", "c2"; 969 qcom,ee = <0>; 970 971 status = "disabled"; 972 }; 973 974 gsbi5: gsbi@1a200000 { 975 compatible = "qcom,gsbi-v1.0.0"; 976 cell-index = <5>; 977 reg = <0x1a200000 0x100>; 978 clocks = <&gcc GSBI5_H_CLK>; 979 clock-names = "iface"; 980 #address-cells = <1>; 981 982 #size-cells = <1>; 983 ranges; 984 status = "disabled"; 985 986 syscon-tcsr = <&tcsr>; 987 988 gsbi5_serial: serial@1a240000 { 989 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 990 reg = <0x1a240000 0x1000>, 991 <0x1a200000 0x1000>; 992 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 994 clock-names = "core", "iface"; 995 status = "disabled"; 996 }; 997 998 i2c@1a280000 { 999 compatible = "qcom,i2c-qup-v1.1.1"; 1000 reg = <0x1a280000 0x1000>; 1001 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1002 1003 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 1004 clock-names = "core", "iface"; 1005 status = "disabled"; 1006 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 }; 1010 1011 spi@1a280000 { 1012 compatible = "qcom,spi-qup-v1.1.1"; 1013 reg = <0x1a280000 0x1000>; 1014 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1015 1016 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 1017 clock-names = "core", "iface"; 1018 status = "disabled"; 1019 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 }; 1023 }; 1024 1025 tcsr: syscon@1a400000 { 1026 compatible = "qcom,tcsr-ipq8064", "syscon"; 1027 reg = <0x1a400000 0x100>; 1028 }; 1029 1030 rng@1a500000 { 1031 compatible = "qcom,prng"; 1032 reg = <0x1a500000 0x200>; 1033 clocks = <&gcc PRNG_CLK>; 1034 clock-names = "core"; 1035 }; 1036 1037 nand: nand-controller@1ac00000 { 1038 compatible = "qcom,ipq806x-nand"; 1039 reg = <0x1ac00000 0x800>; 1040 1041 pinctrl-0 = <&nand_pins>; 1042 pinctrl-names = "default"; 1043 1044 clocks = <&gcc EBI2_CLK>, 1045 <&gcc EBI2_AON_CLK>; 1046 clock-names = "core", "aon"; 1047 1048 dmas = <&adm_dma 3>; 1049 dma-names = "rxtx"; 1050 qcom,cmd-crci = <15>; 1051 qcom,data-crci = <3>; 1052 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 1056 status = "disabled"; 1057 }; 1058 1059 sata_phy: sata-phy@1b400000 { 1060 compatible = "qcom,ipq806x-sata-phy"; 1061 reg = <0x1b400000 0x200>; 1062 1063 clocks = <&gcc SATA_PHY_CFG_CLK>; 1064 clock-names = "cfg"; 1065 1066 #phy-cells = <0>; 1067 status = "disabled"; 1068 }; 1069 1070 pcie0: pci@1b500000 { 1071 compatible = "qcom,pcie-ipq8064"; 1072 reg = <0x1b500000 0x1000 1073 0x1b502000 0x80 1074 0x1b600000 0x100 1075 0x0ff00000 0x100000>; 1076 reg-names = "dbi", "elbi", "parf", "config"; 1077 device_type = "pci"; 1078 linux,pci-domain = <0>; 1079 bus-range = <0x00 0xff>; 1080 num-lanes = <1>; 1081 #address-cells = <3>; 1082 #size-cells = <2>; 1083 1084 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */ 1085 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ 1086 1087 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1088 interrupt-names = "msi"; 1089 #interrupt-cells = <1>; 1090 interrupt-map-mask = <0 0 0 0x7>; 1091 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1092 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1093 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1094 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1095 1096 clocks = <&gcc PCIE_A_CLK>, 1097 <&gcc PCIE_H_CLK>, 1098 <&gcc PCIE_PHY_CLK>, 1099 <&gcc PCIE_AUX_CLK>, 1100 <&gcc PCIE_ALT_REF_CLK>; 1101 clock-names = "core", "iface", "phy", "aux", "ref"; 1102 1103 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; 1104 assigned-clock-rates = <100000000>; 1105 1106 resets = <&gcc PCIE_ACLK_RESET>, 1107 <&gcc PCIE_HCLK_RESET>, 1108 <&gcc PCIE_POR_RESET>, 1109 <&gcc PCIE_PCI_RESET>, 1110 <&gcc PCIE_PHY_RESET>, 1111 <&gcc PCIE_EXT_RESET>; 1112 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1113 1114 pinctrl-0 = <&pcie0_pins>; 1115 pinctrl-names = "default"; 1116 1117 status = "disabled"; 1118 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; 1119 }; 1120 1121 pcie1: pci@1b700000 { 1122 compatible = "qcom,pcie-ipq8064"; 1123 reg = <0x1b700000 0x1000 1124 0x1b702000 0x80 1125 0x1b800000 0x100 1126 0x31f00000 0x100000>; 1127 reg-names = "dbi", "elbi", "parf", "config"; 1128 device_type = "pci"; 1129 linux,pci-domain = <1>; 1130 bus-range = <0x00 0xff>; 1131 num-lanes = <1>; 1132 #address-cells = <3>; 1133 #size-cells = <2>; 1134 1135 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */ 1136 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ 1137 1138 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1139 interrupt-names = "msi"; 1140 #interrupt-cells = <1>; 1141 interrupt-map-mask = <0 0 0 0x7>; 1142 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1143 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1144 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1145 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1146 1147 clocks = <&gcc PCIE_1_A_CLK>, 1148 <&gcc PCIE_1_H_CLK>, 1149 <&gcc PCIE_1_PHY_CLK>, 1150 <&gcc PCIE_1_AUX_CLK>, 1151 <&gcc PCIE_1_ALT_REF_CLK>; 1152 clock-names = "core", "iface", "phy", "aux", "ref"; 1153 1154 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; 1155 assigned-clock-rates = <100000000>; 1156 1157 resets = <&gcc PCIE_1_ACLK_RESET>, 1158 <&gcc PCIE_1_HCLK_RESET>, 1159 <&gcc PCIE_1_POR_RESET>, 1160 <&gcc PCIE_1_PCI_RESET>, 1161 <&gcc PCIE_1_PHY_RESET>, 1162 <&gcc PCIE_1_EXT_RESET>; 1163 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1164 1165 pinctrl-0 = <&pcie1_pins>; 1166 pinctrl-names = "default"; 1167 1168 status = "disabled"; 1169 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; 1170 }; 1171 1172 pcie2: pci@1b900000 { 1173 compatible = "qcom,pcie-ipq8064"; 1174 reg = <0x1b900000 0x1000 1175 0x1b902000 0x80 1176 0x1ba00000 0x100 1177 0x35f00000 0x100000>; 1178 reg-names = "dbi", "elbi", "parf", "config"; 1179 device_type = "pci"; 1180 linux,pci-domain = <2>; 1181 bus-range = <0x00 0xff>; 1182 num-lanes = <1>; 1183 #address-cells = <3>; 1184 #size-cells = <2>; 1185 1186 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */ 1187 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ 1188 1189 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1190 interrupt-names = "msi"; 1191 #interrupt-cells = <1>; 1192 interrupt-map-mask = <0 0 0 0x7>; 1193 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1194 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1195 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1196 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1197 1198 clocks = <&gcc PCIE_2_A_CLK>, 1199 <&gcc PCIE_2_H_CLK>, 1200 <&gcc PCIE_2_PHY_CLK>, 1201 <&gcc PCIE_2_AUX_CLK>, 1202 <&gcc PCIE_2_ALT_REF_CLK>; 1203 clock-names = "core", "iface", "phy", "aux", "ref"; 1204 1205 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; 1206 assigned-clock-rates = <100000000>; 1207 1208 resets = <&gcc PCIE_2_ACLK_RESET>, 1209 <&gcc PCIE_2_HCLK_RESET>, 1210 <&gcc PCIE_2_POR_RESET>, 1211 <&gcc PCIE_2_PCI_RESET>, 1212 <&gcc PCIE_2_PHY_RESET>, 1213 <&gcc PCIE_2_EXT_RESET>; 1214 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1215 1216 pinctrl-0 = <&pcie2_pins>; 1217 pinctrl-names = "default"; 1218 1219 status = "disabled"; 1220 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; 1221 }; 1222 1223 qsgmii_csr: syscon@1bb00000 { 1224 compatible = "syscon"; 1225 reg = <0x1bb00000 0x000001FF>; 1226 }; 1227 1228 lcc: clock-controller@28000000 { 1229 compatible = "qcom,lcc-ipq8064"; 1230 reg = <0x28000000 0x1000>; 1231 #clock-cells = <1>; 1232 #reset-cells = <1>; 1233 }; 1234 1235 lpass@28100000 { 1236 compatible = "qcom,lpass-cpu"; 1237 status = "disabled"; 1238 clocks = <&lcc AHBIX_CLK>, 1239 <&lcc MI2S_OSR_CLK>, 1240 <&lcc MI2S_BIT_CLK>; 1241 clock-names = "ahbix-clk", 1242 "mi2s-osr-clk", 1243 "mi2s-bit-clk"; 1244 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1245 interrupt-names = "lpass-irq-lpaif"; 1246 reg = <0x28100000 0x10000>; 1247 reg-names = "lpass-lpaif"; 1248 }; 1249 1250 sata: sata@29000000 { 1251 compatible = "qcom,ipq806x-ahci", "generic-ahci"; 1252 reg = <0x29000000 0x180>; 1253 1254 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1255 1256 clocks = <&gcc SFAB_SATA_S_H_CLK>, 1257 <&gcc SATA_H_CLK>, 1258 <&gcc SATA_A_CLK>, 1259 <&gcc SATA_RXOOB_CLK>, 1260 <&gcc SATA_PMALIVE_CLK>; 1261 clock-names = "slave_face", "iface", "core", 1262 "rxoob", "pmalive"; 1263 1264 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; 1265 assigned-clock-rates = <100000000>, <100000000>; 1266 1267 phys = <&sata_phy>; 1268 phy-names = "sata-phy"; 1269 status = "disabled"; 1270 }; 1271 1272 gmac0: ethernet@37000000 { 1273 device_type = "network"; 1274 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1275 reg = <0x37000000 0x200000>; 1276 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1277 interrupt-names = "macirq"; 1278 1279 snps,axi-config = <&stmmac_axi_setup>; 1280 snps,pbl = <32>; 1281 snps,aal; 1282 1283 qcom,nss-common = <&nss_common>; 1284 qcom,qsgmii-csr = <&qsgmii_csr>; 1285 1286 clocks = <&gcc GMAC_CORE1_CLK>; 1287 clock-names = "stmmaceth"; 1288 1289 resets = <&gcc GMAC_CORE1_RESET>, 1290 <&gcc GMAC_AHB_RESET>; 1291 reset-names = "stmmaceth", "ahb"; 1292 1293 status = "disabled"; 1294 }; 1295 1296 gmac1: ethernet@37200000 { 1297 device_type = "network"; 1298 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1299 reg = <0x37200000 0x200000>; 1300 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1301 interrupt-names = "macirq"; 1302 1303 snps,axi-config = <&stmmac_axi_setup>; 1304 snps,pbl = <32>; 1305 snps,aal; 1306 1307 qcom,nss-common = <&nss_common>; 1308 qcom,qsgmii-csr = <&qsgmii_csr>; 1309 1310 clocks = <&gcc GMAC_CORE2_CLK>; 1311 clock-names = "stmmaceth"; 1312 1313 resets = <&gcc GMAC_CORE2_RESET>, 1314 <&gcc GMAC_AHB_RESET>; 1315 reset-names = "stmmaceth", "ahb"; 1316 1317 status = "disabled"; 1318 }; 1319 1320 gmac2: ethernet@37400000 { 1321 device_type = "network"; 1322 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1323 reg = <0x37400000 0x200000>; 1324 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1325 interrupt-names = "macirq"; 1326 1327 snps,axi-config = <&stmmac_axi_setup>; 1328 snps,pbl = <32>; 1329 snps,aal; 1330 1331 qcom,nss-common = <&nss_common>; 1332 qcom,qsgmii-csr = <&qsgmii_csr>; 1333 1334 clocks = <&gcc GMAC_CORE3_CLK>; 1335 clock-names = "stmmaceth"; 1336 1337 resets = <&gcc GMAC_CORE3_RESET>, 1338 <&gcc GMAC_AHB_RESET>; 1339 reset-names = "stmmaceth", "ahb"; 1340 1341 status = "disabled"; 1342 }; 1343 1344 gmac3: ethernet@37600000 { 1345 device_type = "network"; 1346 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1347 reg = <0x37600000 0x200000>; 1348 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1349 interrupt-names = "macirq"; 1350 1351 snps,axi-config = <&stmmac_axi_setup>; 1352 snps,pbl = <32>; 1353 snps,aal; 1354 1355 qcom,nss-common = <&nss_common>; 1356 qcom,qsgmii-csr = <&qsgmii_csr>; 1357 1358 clocks = <&gcc GMAC_CORE4_CLK>; 1359 clock-names = "stmmaceth"; 1360 1361 resets = <&gcc GMAC_CORE4_RESET>, 1362 <&gcc GMAC_AHB_RESET>; 1363 reset-names = "stmmaceth", "ahb"; 1364 1365 status = "disabled"; 1366 }; 1367 }; 1368}; 1369