1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/qcom,gcc-msm8974.h>
10#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/power/qcom-rpmpd.h>
13#include <dt-bindings/reset/qcom,gcc-msm8974.h>
14
15/ {
16	#address-cells = <1>;
17	#size-cells = <1>;
18	interrupt-parent = <&intc>;
19
20	chosen { };
21
22	memory@0 {
23		device_type = "memory";
24		reg = <0x0 0x0>;
25	};
26
27	clocks {
28		xo_board: xo_board {
29			compatible = "fixed-clock";
30			#clock-cells = <0>;
31			clock-frequency = <19200000>;
32		};
33
34		sleep_clk: sleep_clk {
35			compatible = "fixed-clock";
36			#clock-cells = <0>;
37			clock-frequency = <32768>;
38		};
39	};
40
41	firmware {
42		scm {
43			compatible = "qcom,scm-msm8226", "qcom,scm";
44			clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
45			clock-names = "core", "bus", "iface";
46		};
47	};
48
49	reserved-memory {
50		#address-cells = <1>;
51		#size-cells = <1>;
52		ranges;
53
54		smem_region: smem@3000000 {
55			reg = <0x3000000 0x100000>;
56			no-map;
57		};
58
59		adsp_region: adsp@dc00000 {
60			reg = <0x0dc00000 0x1900000>;
61			no-map;
62		};
63	};
64
65	smd {
66		compatible = "qcom,smd";
67
68		rpm {
69			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
70			qcom,ipc = <&apcs 8 0>;
71			qcom,smd-edge = <15>;
72
73			rpm_requests: rpm-requests {
74				compatible = "qcom,rpm-msm8226";
75				qcom,smd-channels = "rpm_requests";
76
77				rpmcc: clock-controller {
78					compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc";
79					#clock-cells = <1>;
80					clocks = <&xo_board>;
81					clock-names = "xo";
82				};
83
84				rpmpd: power-controller {
85					compatible = "qcom,msm8226-rpmpd";
86					#power-domain-cells = <1>;
87					operating-points-v2 = <&rpmpd_opp_table>;
88
89					rpmpd_opp_table: opp-table {
90						compatible = "operating-points-v2";
91
92						rpmpd_opp_ret: opp1 {
93							opp-level = <1>;
94						};
95						rpmpd_opp_svs_krait: opp2 {
96							opp-level = <2>;
97						};
98						rpmpd_opp_svs_soc: opp3 {
99							opp-level = <3>;
100						};
101						rpmpd_opp_nom: opp4 {
102							opp-level = <4>;
103						};
104						rpmpd_opp_turbo: opp5 {
105							opp-level = <5>;
106						};
107						rpmpd_opp_super_turbo: opp6 {
108							opp-level = <6>;
109						};
110					};
111				};
112			};
113		};
114	};
115
116	smem {
117		compatible = "qcom,smem";
118
119		memory-region = <&smem_region>;
120		qcom,rpm-msg-ram = <&rpm_msg_ram>;
121
122		hwlocks = <&tcsr_mutex 3>;
123	};
124
125	smp2p-adsp {
126		compatible = "qcom,smp2p";
127		qcom,smem = <443>, <429>;
128
129		interrupt-parent = <&intc>;
130		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
131
132		qcom,ipc = <&apcs 8 10>;
133
134		qcom,local-pid = <0>;
135		qcom,remote-pid = <2>;
136
137		adsp_smp2p_out: master-kernel {
138			qcom,entry-name = "master-kernel";
139			#qcom,smem-state-cells = <1>;
140		};
141
142		adsp_smp2p_in: slave-kernel {
143			qcom,entry-name = "slave-kernel";
144
145			interrupt-controller;
146			#interrupt-cells = <2>;
147		};
148	};
149
150	soc: soc {
151		compatible = "simple-bus";
152		#address-cells = <1>;
153		#size-cells = <1>;
154		ranges;
155
156		intc: interrupt-controller@f9000000 {
157			compatible = "qcom,msm-qgic2";
158			reg = <0xf9000000 0x1000>,
159			      <0xf9002000 0x1000>;
160			interrupt-controller;
161			#interrupt-cells = <3>;
162		};
163
164		apcs: syscon@f9011000 {
165			compatible = "syscon";
166			reg = <0xf9011000 0x1000>;
167		};
168
169		sdhc_1: mmc@f9824900 {
170			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
171			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
172			reg-names = "hc", "core";
173			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
174				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
175			interrupt-names = "hc_irq", "pwr_irq";
176			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
177				 <&gcc GCC_SDCC1_APPS_CLK>,
178				 <&xo_board>;
179			clock-names = "iface", "core", "xo";
180			pinctrl-names = "default";
181			pinctrl-0 = <&sdhc1_default_state>;
182			status = "disabled";
183		};
184
185		sdhc_2: mmc@f98a4900 {
186			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
187			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
188			reg-names = "hc", "core";
189			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
190				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
191			interrupt-names = "hc_irq", "pwr_irq";
192			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
193				 <&gcc GCC_SDCC2_APPS_CLK>,
194				 <&xo_board>;
195			clock-names = "iface", "core", "xo";
196			pinctrl-names = "default";
197			pinctrl-0 = <&sdhc2_default_state>;
198			status = "disabled";
199		};
200
201		sdhc_3: mmc@f9864900 {
202			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
203			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
204			reg-names = "hc", "core";
205			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
206				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
207			interrupt-names = "hc_irq", "pwr_irq";
208			clocks = <&gcc GCC_SDCC3_AHB_CLK>,
209				 <&gcc GCC_SDCC3_APPS_CLK>,
210				 <&xo_board>;
211			clock-names = "iface", "core", "xo";
212			pinctrl-names = "default";
213			pinctrl-0 = <&sdhc3_default_state>;
214			status = "disabled";
215		};
216
217		blsp1_uart1: serial@f991d000 {
218			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
219			reg = <0xf991d000 0x1000>;
220			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
221			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
222			clock-names = "core", "iface";
223			status = "disabled";
224		};
225
226		blsp1_uart3: serial@f991f000 {
227			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
228			reg = <0xf991f000 0x1000>;
229			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
230			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
231			clock-names = "core", "iface";
232			status = "disabled";
233		};
234
235		blsp1_uart4: serial@f9920000 {
236			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
237			reg = <0xf9920000 0x1000>;
238			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
239			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
240			clock-names = "core", "iface";
241			status = "disabled";
242		};
243
244		blsp1_i2c1: i2c@f9923000 {
245			status = "disabled";
246			compatible = "qcom,i2c-qup-v2.1.1";
247			reg = <0xf9923000 0x1000>;
248			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
249			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
250			clock-names = "core", "iface";
251			pinctrl-names = "default";
252			pinctrl-0 = <&blsp1_i2c1_pins>;
253			#address-cells = <1>;
254			#size-cells = <0>;
255		};
256
257		blsp1_i2c2: i2c@f9924000 {
258			status = "disabled";
259			compatible = "qcom,i2c-qup-v2.1.1";
260			reg = <0xf9924000 0x1000>;
261			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
262			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
263			clock-names = "core", "iface";
264			pinctrl-names = "default";
265			pinctrl-0 = <&blsp1_i2c2_pins>;
266			#address-cells = <1>;
267			#size-cells = <0>;
268		};
269
270		blsp1_i2c3: i2c@f9925000 {
271			status = "disabled";
272			compatible = "qcom,i2c-qup-v2.1.1";
273			reg = <0xf9925000 0x1000>;
274			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
275			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
276			clock-names = "core", "iface";
277			pinctrl-names = "default";
278			pinctrl-0 = <&blsp1_i2c3_pins>;
279			#address-cells = <1>;
280			#size-cells = <0>;
281		};
282
283		blsp1_i2c4: i2c@f9926000 {
284			status = "disabled";
285			compatible = "qcom,i2c-qup-v2.1.1";
286			reg = <0xf9926000 0x1000>;
287			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
288			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
289			clock-names = "core", "iface";
290			pinctrl-names = "default";
291			pinctrl-0 = <&blsp1_i2c4_pins>;
292			#address-cells = <1>;
293			#size-cells = <0>;
294		};
295
296		blsp1_i2c5: i2c@f9927000 {
297			status = "disabled";
298			compatible = "qcom,i2c-qup-v2.1.1";
299			reg = <0xf9927000 0x1000>;
300			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
301			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
302			clock-names = "core", "iface";
303			pinctrl-names = "default";
304			pinctrl-0 = <&blsp1_i2c5_pins>;
305			#address-cells = <1>;
306			#size-cells = <0>;
307		};
308
309		cci: cci@fda0c000 {
310			compatible = "qcom,msm8226-cci";
311			#address-cells = <1>;
312			#size-cells = <0>;
313			reg = <0xfda0c000 0x1000>;
314			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
315			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
316				 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
317				 <&mmcc CAMSS_CCI_CCI_CLK>;
318			clock-names = "camss_top_ahb",
319				      "cci_ahb",
320				      "cci";
321
322			pinctrl-names = "default", "sleep";
323			pinctrl-0 = <&cci_default>;
324			pinctrl-1 = <&cci_sleep>;
325
326			status = "disabled";
327
328			cci_i2c0: i2c-bus@0 {
329				reg = <0>;
330				clock-frequency = <400000>;
331				#address-cells = <1>;
332				#size-cells = <0>;
333			};
334		};
335
336		usb: usb@f9a55000 {
337			compatible = "qcom,ci-hdrc";
338			reg = <0xf9a55000 0x200>,
339			      <0xf9a55200 0x200>;
340			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
341			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
342				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
343			clock-names = "iface", "core";
344			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
345			assigned-clock-rates = <75000000>;
346			resets = <&gcc GCC_USB_HS_BCR>;
347			reset-names = "core";
348			phy_type = "ulpi";
349			dr_mode = "otg";
350			hnp-disable;
351			srp-disable;
352			adp-disable;
353			ahb-burst-config = <0>;
354			phy-names = "usb-phy";
355			phys = <&usb_hs_phy>;
356			status = "disabled";
357			#reset-cells = <1>;
358
359			ulpi {
360				usb_hs_phy: phy {
361					compatible = "qcom,usb-hs-phy-msm8226",
362						     "qcom,usb-hs-phy";
363					#phy-cells = <0>;
364					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
365					clock-names = "ref", "sleep";
366					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
367					reset-names = "phy", "por";
368					qcom,init-seq = /bits/ 8 <0x0 0x44
369						0x1 0x68 0x2 0x24 0x3 0x13>;
370				};
371			};
372		};
373
374		gcc: clock-controller@fc400000 {
375			compatible = "qcom,gcc-msm8226";
376			reg = <0xfc400000 0x4000>;
377			#clock-cells = <1>;
378			#reset-cells = <1>;
379			#power-domain-cells = <1>;
380		};
381
382		mmcc: clock-controller@fd8c0000 {
383			compatible = "qcom,mmcc-msm8226";
384			reg = <0xfd8c0000 0x6000>;
385			#clock-cells = <1>;
386			#reset-cells = <1>;
387			#power-domain-cells = <1>;
388		};
389
390		tlmm: pinctrl@fd510000 {
391			compatible = "qcom,msm8226-pinctrl";
392			reg = <0xfd510000 0x4000>;
393			gpio-controller;
394			#gpio-cells = <2>;
395			gpio-ranges = <&tlmm 0 0 117>;
396			interrupt-controller;
397			#interrupt-cells = <2>;
398			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
399
400			blsp1_i2c1_pins: blsp1-i2c1-state {
401				pins = "gpio2", "gpio3";
402				function = "blsp_i2c1";
403				drive-strength = <2>;
404				bias-disable;
405			};
406
407			blsp1_i2c2_pins: blsp1-i2c2-state {
408				pins = "gpio6", "gpio7";
409				function = "blsp_i2c2";
410				drive-strength = <2>;
411				bias-disable;
412			};
413
414			blsp1_i2c3_pins: blsp1-i2c3-state {
415				pins = "gpio10", "gpio11";
416				function = "blsp_i2c3";
417				drive-strength = <2>;
418				bias-disable;
419			};
420
421			blsp1_i2c4_pins: blsp1-i2c4-state {
422				pins = "gpio14", "gpio15";
423				function = "blsp_i2c4";
424				drive-strength = <2>;
425				bias-disable;
426			};
427
428			blsp1_i2c5_pins: blsp1-i2c5-state {
429				pins = "gpio18", "gpio19";
430				function = "blsp_i2c5";
431				drive-strength = <2>;
432				bias-disable;
433			};
434
435			cci_default: cci-default-state {
436				pins = "gpio29", "gpio30";
437				function = "cci_i2c0";
438
439				drive-strength = <2>;
440				bias-disable;
441			};
442
443			cci_sleep: cci-sleep-state {
444				pins = "gpio29", "gpio30";
445				function = "gpio";
446
447				drive-strength = <2>;
448				bias-disable;
449			};
450
451			sdhc1_default_state: sdhc1-default-state {
452				clk-pins {
453					pins = "sdc1_clk";
454					drive-strength = <10>;
455					bias-disable;
456				};
457
458				cmd-data-pins {
459					pins = "sdc1_cmd", "sdc1_data";
460					drive-strength = <10>;
461					bias-pull-up;
462				};
463			};
464
465			sdhc2_default_state: sdhc2-default-state {
466				clk-pins {
467					pins = "sdc2_clk";
468					drive-strength = <10>;
469					bias-disable;
470				};
471
472				cmd-data-pins {
473					pins = "sdc2_cmd", "sdc2_data";
474					drive-strength = <10>;
475					bias-pull-up;
476				};
477			};
478
479			sdhc3_default_state: sdhc3-default-state {
480				clk-pins {
481					pins = "gpio44";
482					function = "sdc3";
483					drive-strength = <8>;
484					bias-disable;
485				};
486
487				cmd-pins {
488					pins = "gpio43";
489					function = "sdc3";
490					drive-strength = <8>;
491					bias-pull-up;
492				};
493
494				data-pins {
495					pins = "gpio39", "gpio40", "gpio41", "gpio42";
496					function = "sdc3";
497					drive-strength = <8>;
498					bias-pull-up;
499				};
500			};
501		};
502
503		restart@fc4ab000 {
504			compatible = "qcom,pshold";
505			reg = <0xfc4ab000 0x4>;
506		};
507
508		spmi_bus: spmi@fc4cf000 {
509			compatible = "qcom,spmi-pmic-arb";
510			reg-names = "core", "intr", "cnfg";
511			reg = <0xfc4cf000 0x1000>,
512			      <0xfc4cb000 0x1000>,
513			      <0xfc4ca000 0x1000>;
514			interrupt-names = "periph_irq";
515			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
516			qcom,ee = <0>;
517			qcom,channel = <0>;
518			#address-cells = <2>;
519			#size-cells = <0>;
520			interrupt-controller;
521			#interrupt-cells = <4>;
522		};
523
524		rng@f9bff000 {
525			compatible = "qcom,prng";
526			reg = <0xf9bff000 0x200>;
527			clocks = <&gcc GCC_PRNG_AHB_CLK>;
528			clock-names = "core";
529		};
530
531		timer@f9020000 {
532			compatible = "arm,armv7-timer-mem";
533			reg = <0xf9020000 0x1000>;
534			#address-cells = <1>;
535			#size-cells = <1>;
536			ranges;
537
538			frame@f9021000 {
539				frame-number = <0>;
540				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
541					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
542				reg = <0xf9021000 0x1000>,
543				      <0xf9022000 0x1000>;
544			};
545
546			frame@f9023000 {
547				frame-number = <1>;
548				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
549				reg = <0xf9023000 0x1000>;
550				status = "disabled";
551			};
552
553			frame@f9024000 {
554				frame-number = <2>;
555				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
556				reg = <0xf9024000 0x1000>;
557				status = "disabled";
558			};
559
560			frame@f9025000 {
561				frame-number = <3>;
562				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
563				reg = <0xf9025000 0x1000>;
564				status = "disabled";
565			};
566
567			frame@f9026000 {
568				frame-number = <4>;
569				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
570				reg = <0xf9026000 0x1000>;
571				status = "disabled";
572			};
573
574			frame@f9027000 {
575				frame-number = <5>;
576				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
577				reg = <0xf9027000 0x1000>;
578				status = "disabled";
579			};
580
581			frame@f9028000 {
582				frame-number = <6>;
583				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
584				reg = <0xf9028000 0x1000>;
585				status = "disabled";
586			};
587		};
588
589		rpm_msg_ram: sram@fc428000 {
590			compatible = "qcom,rpm-msg-ram";
591			reg = <0xfc428000 0x4000>;
592		};
593
594		tcsr_mutex: hwlock@fd484000 {
595			compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
596			reg = <0xfd484000 0x1000>;
597			#hwlock-cells = <1>;
598		};
599
600		adsp: remoteproc@fe200000 {
601			compatible = "qcom,msm8226-adsp-pil";
602			reg = <0xfe200000 0x100>;
603
604			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
605					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
606					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
607					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
608					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
609			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
610
611			power-domains = <&rpmpd MSM8226_VDDCX>;
612			power-domain-names = "cx";
613
614			clocks = <&xo_board>;
615			clock-names = "xo";
616
617			memory-region = <&adsp_region>;
618
619			qcom,smem-states = <&adsp_smp2p_out 0>;
620			qcom,smem-state-names = "stop";
621
622			status = "disabled";
623
624			smd-edge {
625				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
626
627				qcom,ipc = <&apcs 8 8>;
628				qcom,smd-edge = <1>;
629
630				label = "lpass";
631			};
632		};
633	};
634
635	timer {
636		compatible = "arm,armv7-timer";
637		interrupts = <GIC_PPI 2
638				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
639			     <GIC_PPI 3
640				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
641			     <GIC_PPI 4
642				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
643			     <GIC_PPI 1
644				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
645	};
646};
647