1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Record and handle CPU attributes.
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 */
7 #include <asm/arch_timer.h>
8 #include <asm/cache.h>
9 #include <asm/cpu.h>
10 #include <asm/cputype.h>
11 #include <asm/cpufeature.h>
12 #include <asm/fpsimd.h>
13
14 #include <linux/bitops.h>
15 #include <linux/bug.h>
16 #include <linux/compat.h>
17 #include <linux/elf.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/personality.h>
21 #include <linux/preempt.h>
22 #include <linux/printk.h>
23 #include <linux/seq_file.h>
24 #include <linux/sched.h>
25 #include <linux/smp.h>
26 #include <linux/delay.h>
27
28 /*
29 * In case the boot CPU is hotpluggable, we record its initial state and
30 * current state separately. Certain system registers may contain different
31 * values depending on configuration at or after reset.
32 */
33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
34 static struct cpuinfo_arm64 boot_cpu_data;
35
icache_policy_str(int l1ip)36 static inline const char *icache_policy_str(int l1ip)
37 {
38 switch (l1ip) {
39 case CTR_EL0_L1Ip_VPIPT:
40 return "VPIPT";
41 case CTR_EL0_L1Ip_VIPT:
42 return "VIPT";
43 case CTR_EL0_L1Ip_PIPT:
44 return "PIPT";
45 default:
46 return "RESERVED/UNKNOWN";
47 }
48 }
49
50 unsigned long __icache_flags;
51
52 static const char *const hwcap_str[] = {
53 [KERNEL_HWCAP_FP] = "fp",
54 [KERNEL_HWCAP_ASIMD] = "asimd",
55 [KERNEL_HWCAP_EVTSTRM] = "evtstrm",
56 [KERNEL_HWCAP_AES] = "aes",
57 [KERNEL_HWCAP_PMULL] = "pmull",
58 [KERNEL_HWCAP_SHA1] = "sha1",
59 [KERNEL_HWCAP_SHA2] = "sha2",
60 [KERNEL_HWCAP_CRC32] = "crc32",
61 [KERNEL_HWCAP_ATOMICS] = "atomics",
62 [KERNEL_HWCAP_FPHP] = "fphp",
63 [KERNEL_HWCAP_ASIMDHP] = "asimdhp",
64 [KERNEL_HWCAP_CPUID] = "cpuid",
65 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm",
66 [KERNEL_HWCAP_JSCVT] = "jscvt",
67 [KERNEL_HWCAP_FCMA] = "fcma",
68 [KERNEL_HWCAP_LRCPC] = "lrcpc",
69 [KERNEL_HWCAP_DCPOP] = "dcpop",
70 [KERNEL_HWCAP_SHA3] = "sha3",
71 [KERNEL_HWCAP_SM3] = "sm3",
72 [KERNEL_HWCAP_SM4] = "sm4",
73 [KERNEL_HWCAP_ASIMDDP] = "asimddp",
74 [KERNEL_HWCAP_SHA512] = "sha512",
75 [KERNEL_HWCAP_SVE] = "sve",
76 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm",
77 [KERNEL_HWCAP_DIT] = "dit",
78 [KERNEL_HWCAP_USCAT] = "uscat",
79 [KERNEL_HWCAP_ILRCPC] = "ilrcpc",
80 [KERNEL_HWCAP_FLAGM] = "flagm",
81 [KERNEL_HWCAP_SSBS] = "ssbs",
82 [KERNEL_HWCAP_SB] = "sb",
83 [KERNEL_HWCAP_PACA] = "paca",
84 [KERNEL_HWCAP_PACG] = "pacg",
85 [KERNEL_HWCAP_DCPODP] = "dcpodp",
86 [KERNEL_HWCAP_SVE2] = "sve2",
87 [KERNEL_HWCAP_SVEAES] = "sveaes",
88 [KERNEL_HWCAP_SVEPMULL] = "svepmull",
89 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm",
90 [KERNEL_HWCAP_SVESHA3] = "svesha3",
91 [KERNEL_HWCAP_SVESM4] = "svesm4",
92 [KERNEL_HWCAP_FLAGM2] = "flagm2",
93 [KERNEL_HWCAP_FRINT] = "frint",
94 [KERNEL_HWCAP_SVEI8MM] = "svei8mm",
95 [KERNEL_HWCAP_SVEF32MM] = "svef32mm",
96 [KERNEL_HWCAP_SVEF64MM] = "svef64mm",
97 [KERNEL_HWCAP_SVEBF16] = "svebf16",
98 [KERNEL_HWCAP_I8MM] = "i8mm",
99 [KERNEL_HWCAP_BF16] = "bf16",
100 [KERNEL_HWCAP_DGH] = "dgh",
101 [KERNEL_HWCAP_RNG] = "rng",
102 [KERNEL_HWCAP_BTI] = "bti",
103 [KERNEL_HWCAP_MTE] = "mte",
104 [KERNEL_HWCAP_ECV] = "ecv",
105 [KERNEL_HWCAP_AFP] = "afp",
106 [KERNEL_HWCAP_RPRES] = "rpres",
107 [KERNEL_HWCAP_MTE3] = "mte3",
108 [KERNEL_HWCAP_SME] = "sme",
109 [KERNEL_HWCAP_SME_I16I64] = "smei16i64",
110 [KERNEL_HWCAP_SME_F64F64] = "smef64f64",
111 [KERNEL_HWCAP_SME_I8I32] = "smei8i32",
112 [KERNEL_HWCAP_SME_F16F32] = "smef16f32",
113 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32",
114 [KERNEL_HWCAP_SME_F32F32] = "smef32f32",
115 [KERNEL_HWCAP_SME_FA64] = "smefa64",
116 [KERNEL_HWCAP_WFXT] = "wfxt",
117 [KERNEL_HWCAP_EBF16] = "ebf16",
118 [KERNEL_HWCAP_SVE_EBF16] = "sveebf16",
119 [KERNEL_HWCAP_CSSC] = "cssc",
120 [KERNEL_HWCAP_RPRFM] = "rprfm",
121 [KERNEL_HWCAP_SVE2P1] = "sve2p1",
122 [KERNEL_HWCAP_SME2] = "sme2",
123 [KERNEL_HWCAP_SME2P1] = "sme2p1",
124 [KERNEL_HWCAP_SME_I16I32] = "smei16i32",
125 [KERNEL_HWCAP_SME_BI32I32] = "smebi32i32",
126 [KERNEL_HWCAP_SME_B16B16] = "smeb16b16",
127 [KERNEL_HWCAP_SME_F16F16] = "smef16f16",
128 };
129
130 #ifdef CONFIG_COMPAT
131 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x)
132 static const char *const compat_hwcap_str[] = {
133 [COMPAT_KERNEL_HWCAP(SWP)] = "swp",
134 [COMPAT_KERNEL_HWCAP(HALF)] = "half",
135 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb",
136 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */
137 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
138 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */
139 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp",
140 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp",
141 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */
142 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */
143 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */
144 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */
145 [COMPAT_KERNEL_HWCAP(NEON)] = "neon",
146 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3",
147 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */
148 [COMPAT_KERNEL_HWCAP(TLS)] = "tls",
149 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4",
150 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva",
151 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt",
152 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */
153 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae",
154 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm",
155 [COMPAT_KERNEL_HWCAP(FPHP)] = "fphp",
156 [COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp",
157 [COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp",
158 [COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm",
159 [COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16",
160 [COMPAT_KERNEL_HWCAP(I8MM)] = "i8mm",
161 };
162
163 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
164 static const char *const compat_hwcap2_str[] = {
165 [COMPAT_KERNEL_HWCAP2(AES)] = "aes",
166 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull",
167 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1",
168 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2",
169 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32",
170 [COMPAT_KERNEL_HWCAP2(SB)] = "sb",
171 [COMPAT_KERNEL_HWCAP2(SSBS)] = "ssbs",
172 };
173 #endif /* CONFIG_COMPAT */
174
c_show(struct seq_file * m,void * v)175 static int c_show(struct seq_file *m, void *v)
176 {
177 int i, j;
178 bool compat = personality(current->personality) == PER_LINUX32;
179
180 for_each_online_cpu(i) {
181 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
182 u32 midr = cpuinfo->reg_midr;
183
184 /*
185 * glibc reads /proc/cpuinfo to determine the number of
186 * online processors, looking for lines beginning with
187 * "processor". Give glibc what it expects.
188 */
189 seq_printf(m, "processor\t: %d\n", i);
190 if (compat)
191 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
192 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
193
194 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
195 loops_per_jiffy / (500000UL/HZ),
196 loops_per_jiffy / (5000UL/HZ) % 100);
197
198 /*
199 * Dump out the common processor features in a single line.
200 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
201 * rather than attempting to parse this, but there's a body of
202 * software which does already (at least for 32-bit).
203 */
204 seq_puts(m, "Features\t:");
205 if (compat) {
206 #ifdef CONFIG_COMPAT
207 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
208 if (compat_elf_hwcap & (1 << j)) {
209 /*
210 * Warn once if any feature should not
211 * have been present on arm64 platform.
212 */
213 if (WARN_ON_ONCE(!compat_hwcap_str[j]))
214 continue;
215
216 seq_printf(m, " %s", compat_hwcap_str[j]);
217 }
218 }
219
220 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
221 if (compat_elf_hwcap2 & (1 << j))
222 seq_printf(m, " %s", compat_hwcap2_str[j]);
223 #endif /* CONFIG_COMPAT */
224 } else {
225 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
226 if (cpu_have_feature(j))
227 seq_printf(m, " %s", hwcap_str[j]);
228 }
229 seq_puts(m, "\n");
230
231 seq_printf(m, "CPU implementer\t: 0x%02x\n",
232 MIDR_IMPLEMENTOR(midr));
233 seq_printf(m, "CPU architecture: 8\n");
234 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
235 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
236 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
237 }
238
239 return 0;
240 }
241
c_start(struct seq_file * m,loff_t * pos)242 static void *c_start(struct seq_file *m, loff_t *pos)
243 {
244 return *pos < 1 ? (void *)1 : NULL;
245 }
246
c_next(struct seq_file * m,void * v,loff_t * pos)247 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
248 {
249 ++*pos;
250 return NULL;
251 }
252
c_stop(struct seq_file * m,void * v)253 static void c_stop(struct seq_file *m, void *v)
254 {
255 }
256
257 const struct seq_operations cpuinfo_op = {
258 .start = c_start,
259 .next = c_next,
260 .stop = c_stop,
261 .show = c_show
262 };
263
264
265 static struct kobj_type cpuregs_kobj_type = {
266 .sysfs_ops = &kobj_sysfs_ops,
267 };
268
269 /*
270 * The ARM ARM uses the phrase "32-bit register" to describe a register
271 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
272 * no statement is made as to whether the upper 32 bits will or will not
273 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
274 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
275 *
276 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
277 * registers, we expose them both as 64 bit values to cater for possible
278 * future expansion without an ABI break.
279 */
280 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
281 #define CPUREGS_ATTR_RO(_name, _field) \
282 static ssize_t _name##_show(struct kobject *kobj, \
283 struct kobj_attribute *attr, char *buf) \
284 { \
285 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
286 \
287 if (info->reg_midr) \
288 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
289 else \
290 return 0; \
291 } \
292 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
293
294 CPUREGS_ATTR_RO(midr_el1, midr);
295 CPUREGS_ATTR_RO(revidr_el1, revidr);
296 CPUREGS_ATTR_RO(smidr_el1, smidr);
297
298 static struct attribute *cpuregs_id_attrs[] = {
299 &cpuregs_attr_midr_el1.attr,
300 &cpuregs_attr_revidr_el1.attr,
301 NULL
302 };
303
304 static const struct attribute_group cpuregs_attr_group = {
305 .attrs = cpuregs_id_attrs,
306 .name = "identification"
307 };
308
309 static struct attribute *sme_cpuregs_id_attrs[] = {
310 &cpuregs_attr_smidr_el1.attr,
311 NULL
312 };
313
314 static const struct attribute_group sme_cpuregs_attr_group = {
315 .attrs = sme_cpuregs_id_attrs,
316 .name = "identification"
317 };
318
cpuid_cpu_online(unsigned int cpu)319 static int cpuid_cpu_online(unsigned int cpu)
320 {
321 int rc;
322 struct device *dev;
323 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
324
325 dev = get_cpu_device(cpu);
326 if (!dev) {
327 rc = -ENODEV;
328 goto out;
329 }
330 rc = kobject_add(&info->kobj, &dev->kobj, "regs");
331 if (rc)
332 goto out;
333 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
334 if (rc)
335 kobject_del(&info->kobj);
336 if (system_supports_sme())
337 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group);
338 out:
339 return rc;
340 }
341
cpuid_cpu_offline(unsigned int cpu)342 static int cpuid_cpu_offline(unsigned int cpu)
343 {
344 struct device *dev;
345 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
346
347 dev = get_cpu_device(cpu);
348 if (!dev)
349 return -ENODEV;
350 if (info->kobj.parent) {
351 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
352 kobject_del(&info->kobj);
353 }
354
355 return 0;
356 }
357
cpuinfo_regs_init(void)358 static int __init cpuinfo_regs_init(void)
359 {
360 int cpu, ret;
361
362 for_each_possible_cpu(cpu) {
363 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
364
365 kobject_init(&info->kobj, &cpuregs_kobj_type);
366 }
367
368 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
369 cpuid_cpu_online, cpuid_cpu_offline);
370 if (ret < 0) {
371 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
372 return ret;
373 }
374 return 0;
375 }
376 device_initcall(cpuinfo_regs_init);
377
cpuinfo_detect_icache_policy(struct cpuinfo_arm64 * info)378 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
379 {
380 unsigned int cpu = smp_processor_id();
381 u32 l1ip = CTR_L1IP(info->reg_ctr);
382
383 switch (l1ip) {
384 case CTR_EL0_L1Ip_PIPT:
385 break;
386 case CTR_EL0_L1Ip_VPIPT:
387 set_bit(ICACHEF_VPIPT, &__icache_flags);
388 break;
389 case CTR_EL0_L1Ip_VIPT:
390 default:
391 /* Assume aliasing */
392 set_bit(ICACHEF_ALIASING, &__icache_flags);
393 break;
394 }
395
396 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu);
397 }
398
__cpuinfo_store_cpu_32bit(struct cpuinfo_32bit * info)399 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
400 {
401 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
402 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
403 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
404 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
405 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
406 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
407 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
408 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
409 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
410 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
411 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
412 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
413 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
414 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
415 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
416 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
417 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
418 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
419
420 info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
421 info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
422 info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
423 }
424
__cpuinfo_store_cpu(struct cpuinfo_arm64 * info)425 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
426 {
427 info->reg_cntfrq = arch_timer_get_cntfrq();
428 /*
429 * Use the effective value of the CTR_EL0 than the raw value
430 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted
431 * with the CLIDR_EL1 fields to avoid triggering false warnings
432 * when there is a mismatch across the CPUs. Keep track of the
433 * effective value of the CTR_EL0 in our internal records for
434 * accurate sanity check and feature enablement.
435 */
436 info->reg_ctr = read_cpuid_effective_cachetype();
437 info->reg_dczid = read_cpuid(DCZID_EL0);
438 info->reg_midr = read_cpuid_id();
439 info->reg_revidr = read_cpuid(REVIDR_EL1);
440
441 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
442 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
443 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
444 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
445 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
446 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
447 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
448 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
449 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
450 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
451 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
452 info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1);
453
454 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
455 info->reg_gmid = read_cpuid(GMID_EL1);
456
457 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
458 __cpuinfo_store_cpu_32bit(&info->aarch32);
459
460 cpuinfo_detect_icache_policy(info);
461 }
462
cpuinfo_store_cpu(void)463 void cpuinfo_store_cpu(void)
464 {
465 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
466 __cpuinfo_store_cpu(info);
467 update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
468 }
469
cpuinfo_store_boot_cpu(void)470 void __init cpuinfo_store_boot_cpu(void)
471 {
472 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
473 __cpuinfo_store_cpu(info);
474
475 boot_cpu_data = *info;
476 init_cpu_features(&boot_cpu_data);
477 }
478