1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
16
17 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
18
19 #include "common.h"
20 #include "clk-regmap.h"
21 #include "clk-regmap-divider.h"
22 #include "clk-alpha-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "reset.h"
26 #include "gdsc.h"
27
28 enum {
29 P_XO,
30 P_GPLL0,
31 P_GPLL0_DIV,
32 P_MMPLL0_OUT_EVEN,
33 P_MMPLL1_OUT_EVEN,
34 P_MMPLL3_OUT_EVEN,
35 P_MMPLL4_OUT_EVEN,
36 P_MMPLL5_OUT_EVEN,
37 P_MMPLL6_OUT_EVEN,
38 P_MMPLL7_OUT_EVEN,
39 P_MMPLL10_OUT_EVEN,
40 P_DSI0PLL,
41 P_DSI1PLL,
42 P_DSI0PLL_BYTE,
43 P_DSI1PLL_BYTE,
44 P_HDMIPLL,
45 P_DPVCO,
46 P_DPLINK,
47 };
48
49 static struct clk_fixed_factor gpll0_div = {
50 .mult = 1,
51 .div = 2,
52 .hw.init = &(struct clk_init_data){
53 .name = "mmss_gpll0_div",
54 .parent_data = &(const struct clk_parent_data){
55 .fw_name = "gpll0"
56 },
57 .num_parents = 1,
58 .ops = &clk_fixed_factor_ops,
59 },
60 };
61
62 static const struct clk_div_table post_div_table_fabia_even[] = {
63 { 0x0, 1 },
64 { 0x1, 2 },
65 { 0x3, 4 },
66 { 0x7, 8 },
67 { }
68 };
69
70 static struct clk_alpha_pll mmpll0 = {
71 .offset = 0xc000,
72 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
73 .clkr = {
74 .enable_reg = 0x1e0,
75 .enable_mask = BIT(0),
76 .hw.init = &(struct clk_init_data){
77 .name = "mmpll0",
78 .parent_data = &(const struct clk_parent_data){
79 .fw_name = "xo"
80 },
81 .num_parents = 1,
82 .ops = &clk_alpha_pll_fixed_fabia_ops,
83 },
84 },
85 };
86
87 static struct clk_alpha_pll_postdiv mmpll0_out_even = {
88 .offset = 0xc000,
89 .post_div_shift = 8,
90 .post_div_table = post_div_table_fabia_even,
91 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
92 .width = 4,
93 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
94 .clkr.hw.init = &(struct clk_init_data){
95 .name = "mmpll0_out_even",
96 .parent_hws = (const struct clk_hw *[]){ &mmpll0.clkr.hw },
97 .num_parents = 1,
98 .ops = &clk_alpha_pll_postdiv_fabia_ops,
99 },
100 };
101
102 static struct clk_alpha_pll mmpll1 = {
103 .offset = 0xc050,
104 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
105 .clkr = {
106 .enable_reg = 0x1e0,
107 .enable_mask = BIT(1),
108 .hw.init = &(struct clk_init_data){
109 .name = "mmpll1",
110 .parent_data = &(const struct clk_parent_data){
111 .fw_name = "xo"
112 },
113 .num_parents = 1,
114 .ops = &clk_alpha_pll_fixed_fabia_ops,
115 },
116 },
117 };
118
119 static struct clk_alpha_pll_postdiv mmpll1_out_even = {
120 .offset = 0xc050,
121 .post_div_shift = 8,
122 .post_div_table = post_div_table_fabia_even,
123 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
124 .width = 4,
125 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
126 .clkr.hw.init = &(struct clk_init_data){
127 .name = "mmpll1_out_even",
128 .parent_hws = (const struct clk_hw *[]){ &mmpll1.clkr.hw },
129 .num_parents = 1,
130 .ops = &clk_alpha_pll_postdiv_fabia_ops,
131 },
132 };
133
134 static struct clk_alpha_pll mmpll3 = {
135 .offset = 0x0,
136 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
137 .clkr.hw.init = &(struct clk_init_data){
138 .name = "mmpll3",
139 .parent_data = &(const struct clk_parent_data){
140 .fw_name = "xo"
141 },
142 .num_parents = 1,
143 .ops = &clk_alpha_pll_fixed_fabia_ops,
144 },
145 };
146
147 static struct clk_alpha_pll_postdiv mmpll3_out_even = {
148 .offset = 0x0,
149 .post_div_shift = 8,
150 .post_div_table = post_div_table_fabia_even,
151 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
152 .width = 4,
153 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
154 .clkr.hw.init = &(struct clk_init_data){
155 .name = "mmpll3_out_even",
156 .parent_hws = (const struct clk_hw *[]){ &mmpll3.clkr.hw },
157 .num_parents = 1,
158 .ops = &clk_alpha_pll_postdiv_fabia_ops,
159 },
160 };
161
162 static struct clk_alpha_pll mmpll4 = {
163 .offset = 0x50,
164 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
165 .clkr.hw.init = &(struct clk_init_data){
166 .name = "mmpll4",
167 .parent_data = &(const struct clk_parent_data){
168 .fw_name = "xo"
169 },
170 .num_parents = 1,
171 .ops = &clk_alpha_pll_fixed_fabia_ops,
172 },
173 };
174
175 static struct clk_alpha_pll_postdiv mmpll4_out_even = {
176 .offset = 0x50,
177 .post_div_shift = 8,
178 .post_div_table = post_div_table_fabia_even,
179 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
180 .width = 4,
181 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
182 .clkr.hw.init = &(struct clk_init_data){
183 .name = "mmpll4_out_even",
184 .parent_hws = (const struct clk_hw *[]){ &mmpll4.clkr.hw },
185 .num_parents = 1,
186 .ops = &clk_alpha_pll_postdiv_fabia_ops,
187 },
188 };
189
190 static struct clk_alpha_pll mmpll5 = {
191 .offset = 0xa0,
192 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
193 .clkr.hw.init = &(struct clk_init_data){
194 .name = "mmpll5",
195 .parent_data = &(const struct clk_parent_data){
196 .fw_name = "xo"
197 },
198 .num_parents = 1,
199 .ops = &clk_alpha_pll_fixed_fabia_ops,
200 },
201 };
202
203 static struct clk_alpha_pll_postdiv mmpll5_out_even = {
204 .offset = 0xa0,
205 .post_div_shift = 8,
206 .post_div_table = post_div_table_fabia_even,
207 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
208 .width = 4,
209 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
210 .clkr.hw.init = &(struct clk_init_data){
211 .name = "mmpll5_out_even",
212 .parent_hws = (const struct clk_hw *[]){ &mmpll5.clkr.hw },
213 .num_parents = 1,
214 .ops = &clk_alpha_pll_postdiv_fabia_ops,
215 },
216 };
217
218 static struct clk_alpha_pll mmpll6 = {
219 .offset = 0xf0,
220 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
221 .clkr.hw.init = &(struct clk_init_data){
222 .name = "mmpll6",
223 .parent_data = &(const struct clk_parent_data){
224 .fw_name = "xo"
225 },
226 .num_parents = 1,
227 .ops = &clk_alpha_pll_fixed_fabia_ops,
228 },
229 };
230
231 static struct clk_alpha_pll_postdiv mmpll6_out_even = {
232 .offset = 0xf0,
233 .post_div_shift = 8,
234 .post_div_table = post_div_table_fabia_even,
235 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
236 .width = 4,
237 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
238 .clkr.hw.init = &(struct clk_init_data){
239 .name = "mmpll6_out_even",
240 .parent_hws = (const struct clk_hw *[]){ &mmpll6.clkr.hw },
241 .num_parents = 1,
242 .ops = &clk_alpha_pll_postdiv_fabia_ops,
243 },
244 };
245
246 static struct clk_alpha_pll mmpll7 = {
247 .offset = 0x140,
248 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
249 .clkr.hw.init = &(struct clk_init_data){
250 .name = "mmpll7",
251 .parent_data = &(const struct clk_parent_data){
252 .fw_name = "xo"
253 },
254 .num_parents = 1,
255 .ops = &clk_alpha_pll_fixed_fabia_ops,
256 },
257 };
258
259 static struct clk_alpha_pll_postdiv mmpll7_out_even = {
260 .offset = 0x140,
261 .post_div_shift = 8,
262 .post_div_table = post_div_table_fabia_even,
263 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
264 .width = 4,
265 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
266 .clkr.hw.init = &(struct clk_init_data){
267 .name = "mmpll7_out_even",
268 .parent_hws = (const struct clk_hw *[]){ &mmpll7.clkr.hw },
269 .num_parents = 1,
270 .ops = &clk_alpha_pll_postdiv_fabia_ops,
271 },
272 };
273
274 static struct clk_alpha_pll mmpll10 = {
275 .offset = 0x190,
276 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
277 .clkr.hw.init = &(struct clk_init_data){
278 .name = "mmpll10",
279 .parent_data = &(const struct clk_parent_data){
280 .fw_name = "xo"
281 },
282 .num_parents = 1,
283 .ops = &clk_alpha_pll_fixed_fabia_ops,
284 },
285 };
286
287 static struct clk_alpha_pll_postdiv mmpll10_out_even = {
288 .offset = 0x190,
289 .post_div_shift = 8,
290 .post_div_table = post_div_table_fabia_even,
291 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
292 .width = 4,
293 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
294 .clkr.hw.init = &(struct clk_init_data){
295 .name = "mmpll10_out_even",
296 .parent_hws = (const struct clk_hw *[]){ &mmpll10.clkr.hw },
297 .num_parents = 1,
298 .ops = &clk_alpha_pll_postdiv_fabia_ops,
299 },
300 };
301
302 static const struct parent_map mmss_xo_hdmi_map[] = {
303 { P_XO, 0 },
304 { P_HDMIPLL, 1 },
305 };
306
307 static const struct clk_parent_data mmss_xo_hdmi[] = {
308 { .fw_name = "xo" },
309 { .fw_name = "hdmipll" },
310 };
311
312 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
313 { P_XO, 0 },
314 { P_DSI0PLL, 1 },
315 { P_DSI1PLL, 2 },
316 };
317
318 static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
319 { .fw_name = "xo" },
320 { .fw_name = "dsi0dsi" },
321 { .fw_name = "dsi1dsi" },
322 };
323
324 static const struct parent_map mmss_xo_dsibyte_map[] = {
325 { P_XO, 0 },
326 { P_DSI0PLL_BYTE, 1 },
327 { P_DSI1PLL_BYTE, 2 },
328 };
329
330 static const struct clk_parent_data mmss_xo_dsibyte[] = {
331 { .fw_name = "xo" },
332 { .fw_name = "dsi0byte" },
333 { .fw_name = "dsi1byte" },
334 };
335
336 static const struct parent_map mmss_xo_dp_map[] = {
337 { P_XO, 0 },
338 { P_DPLINK, 1 },
339 { P_DPVCO, 2 },
340 };
341
342 static const struct clk_parent_data mmss_xo_dp[] = {
343 { .fw_name = "xo" },
344 { .fw_name = "dplink" },
345 { .fw_name = "dpvco" },
346 };
347
348 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
349 { P_XO, 0 },
350 { P_GPLL0, 5 },
351 { P_GPLL0_DIV, 6 },
352 };
353
354 static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
355 { .fw_name = "xo" },
356 { .fw_name = "gpll0" },
357 { .hw = &gpll0_div.hw },
358 };
359
360 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
361 { P_XO, 0 },
362 { P_MMPLL0_OUT_EVEN, 1 },
363 { P_GPLL0, 5 },
364 { P_GPLL0_DIV, 6 },
365 };
366
367 static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
368 { .fw_name = "xo" },
369 { .hw = &mmpll0_out_even.clkr.hw },
370 { .fw_name = "gpll0" },
371 { .hw = &gpll0_div.hw },
372 };
373
374 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
375 { P_XO, 0 },
376 { P_MMPLL0_OUT_EVEN, 1 },
377 { P_MMPLL1_OUT_EVEN, 2 },
378 { P_GPLL0, 5 },
379 { P_GPLL0_DIV, 6 },
380 };
381
382 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
383 { .fw_name = "xo" },
384 { .hw = &mmpll0_out_even.clkr.hw },
385 { .hw = &mmpll1_out_even.clkr.hw },
386 { .fw_name = "gpll0" },
387 { .hw = &gpll0_div.hw },
388 };
389
390 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
391 { P_XO, 0 },
392 { P_MMPLL0_OUT_EVEN, 1 },
393 { P_MMPLL5_OUT_EVEN, 2 },
394 { P_GPLL0, 5 },
395 { P_GPLL0_DIV, 6 },
396 };
397
398 static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
399 { .fw_name = "xo" },
400 { .hw = &mmpll0_out_even.clkr.hw },
401 { .hw = &mmpll5_out_even.clkr.hw },
402 { .fw_name = "gpll0" },
403 { .hw = &gpll0_div.hw },
404 };
405
406 static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
407 { P_XO, 0 },
408 { P_MMPLL0_OUT_EVEN, 1 },
409 { P_MMPLL3_OUT_EVEN, 3 },
410 { P_MMPLL6_OUT_EVEN, 4 },
411 { P_GPLL0, 5 },
412 { P_GPLL0_DIV, 6 },
413 };
414
415 static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = {
416 { .fw_name = "xo" },
417 { .hw = &mmpll0_out_even.clkr.hw },
418 { .hw = &mmpll3_out_even.clkr.hw },
419 { .hw = &mmpll6_out_even.clkr.hw },
420 { .fw_name = "gpll0" },
421 { .hw = &gpll0_div.hw },
422 };
423
424 static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
425 { P_XO, 0 },
426 { P_MMPLL4_OUT_EVEN, 1 },
427 { P_MMPLL7_OUT_EVEN, 2 },
428 { P_MMPLL10_OUT_EVEN, 3 },
429 { P_GPLL0, 5 },
430 { P_GPLL0_DIV, 6 },
431 };
432
433 static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
434 { .fw_name = "xo" },
435 { .hw = &mmpll4_out_even.clkr.hw },
436 { .hw = &mmpll7_out_even.clkr.hw },
437 { .hw = &mmpll10_out_even.clkr.hw },
438 { .fw_name = "gpll0" },
439 { .hw = &gpll0_div.hw },
440 };
441
442 static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
443 { P_XO, 0 },
444 { P_MMPLL0_OUT_EVEN, 1 },
445 { P_MMPLL7_OUT_EVEN, 2 },
446 { P_MMPLL10_OUT_EVEN, 3 },
447 { P_GPLL0, 5 },
448 { P_GPLL0_DIV, 6 },
449 };
450
451 static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = {
452 { .fw_name = "xo" },
453 { .hw = &mmpll0_out_even.clkr.hw },
454 { .hw = &mmpll7_out_even.clkr.hw },
455 { .hw = &mmpll10_out_even.clkr.hw },
456 { .fw_name = "gpll0" },
457 { .hw = &gpll0_div.hw },
458 };
459
460 static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
461 { P_XO, 0 },
462 { P_MMPLL0_OUT_EVEN, 1 },
463 { P_MMPLL4_OUT_EVEN, 2 },
464 { P_MMPLL7_OUT_EVEN, 3 },
465 { P_MMPLL10_OUT_EVEN, 4 },
466 { P_GPLL0, 5 },
467 { P_GPLL0_DIV, 6 },
468 };
469
470 static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
471 { .fw_name = "xo" },
472 { .hw = &mmpll0_out_even.clkr.hw },
473 { .hw = &mmpll4_out_even.clkr.hw },
474 { .hw = &mmpll7_out_even.clkr.hw },
475 { .hw = &mmpll10_out_even.clkr.hw },
476 { .fw_name = "gpll0" },
477 { .hw = &gpll0_div.hw },
478 };
479
480 static struct clk_rcg2 byte0_clk_src = {
481 .cmd_rcgr = 0x2120,
482 .hid_width = 5,
483 .parent_map = mmss_xo_dsibyte_map,
484 .clkr.hw.init = &(struct clk_init_data){
485 .name = "byte0_clk_src",
486 .parent_data = mmss_xo_dsibyte,
487 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
488 .ops = &clk_byte2_ops,
489 .flags = CLK_SET_RATE_PARENT,
490 },
491 };
492
493 static struct clk_rcg2 byte1_clk_src = {
494 .cmd_rcgr = 0x2140,
495 .hid_width = 5,
496 .parent_map = mmss_xo_dsibyte_map,
497 .clkr.hw.init = &(struct clk_init_data){
498 .name = "byte1_clk_src",
499 .parent_data = mmss_xo_dsibyte,
500 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
501 .ops = &clk_byte2_ops,
502 .flags = CLK_SET_RATE_PARENT,
503 },
504 };
505
506 static const struct freq_tbl ftbl_cci_clk_src[] = {
507 F(37500000, P_GPLL0, 16, 0, 0),
508 F(50000000, P_GPLL0, 12, 0, 0),
509 F(100000000, P_GPLL0, 6, 0, 0),
510 { }
511 };
512
513 static struct clk_rcg2 cci_clk_src = {
514 .cmd_rcgr = 0x3300,
515 .hid_width = 5,
516 .parent_map = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map,
517 .freq_tbl = ftbl_cci_clk_src,
518 .clkr.hw.init = &(struct clk_init_data){
519 .name = "cci_clk_src",
520 .parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div,
521 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div),
522 .ops = &clk_rcg2_ops,
523 },
524 };
525
526 static const struct freq_tbl ftbl_cpp_clk_src[] = {
527 F(100000000, P_GPLL0, 6, 0, 0),
528 F(200000000, P_GPLL0, 3, 0, 0),
529 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
530 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
531 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
532 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
533 F(600000000, P_GPLL0, 1, 0, 0),
534 { }
535 };
536
537 static struct clk_rcg2 cpp_clk_src = {
538 .cmd_rcgr = 0x3640,
539 .hid_width = 5,
540 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
541 .freq_tbl = ftbl_cpp_clk_src,
542 .clkr.hw.init = &(struct clk_init_data){
543 .name = "cpp_clk_src",
544 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
545 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
546 .ops = &clk_rcg2_ops,
547 },
548 };
549
550 static const struct freq_tbl ftbl_csi_clk_src[] = {
551 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
552 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
553 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
554 F(300000000, P_GPLL0, 2, 0, 0),
555 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
556 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
557 { }
558 };
559
560 static struct clk_rcg2 csi0_clk_src = {
561 .cmd_rcgr = 0x3090,
562 .hid_width = 5,
563 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
564 .freq_tbl = ftbl_csi_clk_src,
565 .clkr.hw.init = &(struct clk_init_data){
566 .name = "csi0_clk_src",
567 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
568 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
569 .ops = &clk_rcg2_ops,
570 },
571 };
572
573 static struct clk_rcg2 csi1_clk_src = {
574 .cmd_rcgr = 0x3100,
575 .hid_width = 5,
576 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
577 .freq_tbl = ftbl_csi_clk_src,
578 .clkr.hw.init = &(struct clk_init_data){
579 .name = "csi1_clk_src",
580 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
581 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
582 .ops = &clk_rcg2_ops,
583 },
584 };
585
586 static struct clk_rcg2 csi2_clk_src = {
587 .cmd_rcgr = 0x3160,
588 .hid_width = 5,
589 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
590 .freq_tbl = ftbl_csi_clk_src,
591 .clkr.hw.init = &(struct clk_init_data){
592 .name = "csi2_clk_src",
593 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
594 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
595 .ops = &clk_rcg2_ops,
596 },
597 };
598
599 static struct clk_rcg2 csi3_clk_src = {
600 .cmd_rcgr = 0x31c0,
601 .hid_width = 5,
602 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
603 .freq_tbl = ftbl_csi_clk_src,
604 .clkr.hw.init = &(struct clk_init_data){
605 .name = "csi3_clk_src",
606 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
607 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
608 .ops = &clk_rcg2_ops,
609 },
610 };
611
612 static const struct freq_tbl ftbl_csiphy_clk_src[] = {
613 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
614 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
615 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
616 F(300000000, P_GPLL0, 2, 0, 0),
617 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
618 { }
619 };
620
621 static struct clk_rcg2 csiphy_clk_src = {
622 .cmd_rcgr = 0x3800,
623 .hid_width = 5,
624 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
625 .freq_tbl = ftbl_csiphy_clk_src,
626 .clkr.hw.init = &(struct clk_init_data){
627 .name = "csiphy_clk_src",
628 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
629 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
630 .ops = &clk_rcg2_ops,
631 },
632 };
633
634 static const struct freq_tbl ftbl_csiphytimer_clk_src[] = {
635 F(200000000, P_GPLL0, 3, 0, 0),
636 F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
637 { }
638 };
639
640 static struct clk_rcg2 csi0phytimer_clk_src = {
641 .cmd_rcgr = 0x3000,
642 .hid_width = 5,
643 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
644 .freq_tbl = ftbl_csiphytimer_clk_src,
645 .clkr.hw.init = &(struct clk_init_data){
646 .name = "csi0phytimer_clk_src",
647 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
648 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
649 .ops = &clk_rcg2_ops,
650 },
651 };
652
653 static struct clk_rcg2 csi1phytimer_clk_src = {
654 .cmd_rcgr = 0x3030,
655 .hid_width = 5,
656 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
657 .freq_tbl = ftbl_csiphytimer_clk_src,
658 .clkr.hw.init = &(struct clk_init_data){
659 .name = "csi1phytimer_clk_src",
660 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
661 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
662 .ops = &clk_rcg2_ops,
663 },
664 };
665
666 static struct clk_rcg2 csi2phytimer_clk_src = {
667 .cmd_rcgr = 0x3060,
668 .hid_width = 5,
669 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
670 .freq_tbl = ftbl_csiphytimer_clk_src,
671 .clkr.hw.init = &(struct clk_init_data){
672 .name = "csi2phytimer_clk_src",
673 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
674 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
675 .ops = &clk_rcg2_ops,
676 },
677 };
678
679 static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
680 F(19200000, P_XO, 1, 0, 0),
681 { }
682 };
683
684 static struct clk_rcg2 dp_aux_clk_src = {
685 .cmd_rcgr = 0x2260,
686 .hid_width = 5,
687 .parent_map = mmss_xo_gpll0_gpll0_div_map,
688 .freq_tbl = ftbl_dp_aux_clk_src,
689 .clkr.hw.init = &(struct clk_init_data){
690 .name = "dp_aux_clk_src",
691 .parent_data = mmss_xo_gpll0_gpll0_div,
692 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
693 .ops = &clk_rcg2_ops,
694 },
695 };
696
697 static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
698 F(101250, P_DPLINK, 1, 5, 16),
699 F(168750, P_DPLINK, 1, 5, 16),
700 F(337500, P_DPLINK, 1, 5, 16),
701 { }
702 };
703
704 static struct clk_rcg2 dp_crypto_clk_src = {
705 .cmd_rcgr = 0x2220,
706 .hid_width = 5,
707 .parent_map = mmss_xo_dp_map,
708 .freq_tbl = ftbl_dp_crypto_clk_src,
709 .clkr.hw.init = &(struct clk_init_data){
710 .name = "dp_crypto_clk_src",
711 .parent_data = mmss_xo_dp,
712 .num_parents = ARRAY_SIZE(mmss_xo_dp),
713 .ops = &clk_rcg2_ops,
714 },
715 };
716
717 static const struct freq_tbl ftbl_dp_link_clk_src[] = {
718 F(162000, P_DPLINK, 2, 0, 0),
719 F(270000, P_DPLINK, 2, 0, 0),
720 F(540000, P_DPLINK, 2, 0, 0),
721 { }
722 };
723
724 static struct clk_rcg2 dp_link_clk_src = {
725 .cmd_rcgr = 0x2200,
726 .hid_width = 5,
727 .parent_map = mmss_xo_dp_map,
728 .freq_tbl = ftbl_dp_link_clk_src,
729 .clkr.hw.init = &(struct clk_init_data){
730 .name = "dp_link_clk_src",
731 .parent_data = mmss_xo_dp,
732 .num_parents = ARRAY_SIZE(mmss_xo_dp),
733 .ops = &clk_rcg2_ops,
734 },
735 };
736
737 static const struct freq_tbl ftbl_dp_pixel_clk_src[] = {
738 F(154000000, P_DPVCO, 1, 0, 0),
739 F(337500000, P_DPVCO, 2, 0, 0),
740 F(675000000, P_DPVCO, 2, 0, 0),
741 { }
742 };
743
744 static struct clk_rcg2 dp_pixel_clk_src = {
745 .cmd_rcgr = 0x2240,
746 .hid_width = 5,
747 .parent_map = mmss_xo_dp_map,
748 .freq_tbl = ftbl_dp_pixel_clk_src,
749 .clkr.hw.init = &(struct clk_init_data){
750 .name = "dp_pixel_clk_src",
751 .parent_data = mmss_xo_dp,
752 .num_parents = ARRAY_SIZE(mmss_xo_dp),
753 .ops = &clk_rcg2_ops,
754 },
755 };
756
757 static const struct freq_tbl ftbl_esc_clk_src[] = {
758 F(19200000, P_XO, 1, 0, 0),
759 { }
760 };
761
762 static struct clk_rcg2 esc0_clk_src = {
763 .cmd_rcgr = 0x2160,
764 .hid_width = 5,
765 .parent_map = mmss_xo_dsibyte_map,
766 .freq_tbl = ftbl_esc_clk_src,
767 .clkr.hw.init = &(struct clk_init_data){
768 .name = "esc0_clk_src",
769 .parent_data = mmss_xo_dsibyte,
770 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
771 .ops = &clk_rcg2_ops,
772 },
773 };
774
775 static struct clk_rcg2 esc1_clk_src = {
776 .cmd_rcgr = 0x2180,
777 .hid_width = 5,
778 .parent_map = mmss_xo_dsibyte_map,
779 .freq_tbl = ftbl_esc_clk_src,
780 .clkr.hw.init = &(struct clk_init_data){
781 .name = "esc1_clk_src",
782 .parent_data = mmss_xo_dsibyte,
783 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
784 .ops = &clk_rcg2_ops,
785 },
786 };
787
788 static const struct freq_tbl ftbl_extpclk_clk_src[] = {
789 { .src = P_HDMIPLL },
790 { }
791 };
792
793 static struct clk_rcg2 extpclk_clk_src = {
794 .cmd_rcgr = 0x2060,
795 .hid_width = 5,
796 .parent_map = mmss_xo_hdmi_map,
797 .freq_tbl = ftbl_extpclk_clk_src,
798 .clkr.hw.init = &(struct clk_init_data){
799 .name = "extpclk_clk_src",
800 .parent_data = mmss_xo_hdmi,
801 .num_parents = ARRAY_SIZE(mmss_xo_hdmi),
802 .ops = &clk_byte_ops,
803 .flags = CLK_SET_RATE_PARENT,
804 },
805 };
806
807 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
808 F(100000000, P_GPLL0, 6, 0, 0),
809 F(200000000, P_GPLL0, 3, 0, 0),
810 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
811 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
812 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
813 { }
814 };
815
816 static struct clk_rcg2 fd_core_clk_src = {
817 .cmd_rcgr = 0x3b00,
818 .hid_width = 5,
819 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
820 .freq_tbl = ftbl_fd_core_clk_src,
821 .clkr.hw.init = &(struct clk_init_data){
822 .name = "fd_core_clk_src",
823 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
824 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
825 .ops = &clk_rcg2_ops,
826 },
827 };
828
829 static const struct freq_tbl ftbl_hdmi_clk_src[] = {
830 F(19200000, P_XO, 1, 0, 0),
831 { }
832 };
833
834 static struct clk_rcg2 hdmi_clk_src = {
835 .cmd_rcgr = 0x2100,
836 .hid_width = 5,
837 .parent_map = mmss_xo_gpll0_gpll0_div_map,
838 .freq_tbl = ftbl_hdmi_clk_src,
839 .clkr.hw.init = &(struct clk_init_data){
840 .name = "hdmi_clk_src",
841 .parent_data = mmss_xo_gpll0_gpll0_div,
842 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
843 .ops = &clk_rcg2_ops,
844 },
845 };
846
847 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
848 F(75000000, P_GPLL0, 8, 0, 0),
849 F(150000000, P_GPLL0, 4, 0, 0),
850 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
851 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
852 { }
853 };
854
855 static struct clk_rcg2 jpeg0_clk_src = {
856 .cmd_rcgr = 0x3500,
857 .hid_width = 5,
858 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
859 .freq_tbl = ftbl_jpeg0_clk_src,
860 .clkr.hw.init = &(struct clk_init_data){
861 .name = "jpeg0_clk_src",
862 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
863 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
864 .ops = &clk_rcg2_ops,
865 },
866 };
867
868 static const struct freq_tbl ftbl_maxi_clk_src[] = {
869 F(19200000, P_XO, 1, 0, 0),
870 F(75000000, P_GPLL0_DIV, 4, 0, 0),
871 F(171428571, P_GPLL0, 3.5, 0, 0),
872 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
873 F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
874 { }
875 };
876
877 static struct clk_rcg2 maxi_clk_src = {
878 .cmd_rcgr = 0xf020,
879 .hid_width = 5,
880 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
881 .freq_tbl = ftbl_maxi_clk_src,
882 .clkr.hw.init = &(struct clk_init_data){
883 .name = "maxi_clk_src",
884 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
885 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
886 .ops = &clk_rcg2_ops,
887 },
888 };
889
890 static const struct freq_tbl ftbl_mclk_clk_src[] = {
891 F(4800000, P_XO, 4, 0, 0),
892 F(6000000, P_GPLL0_DIV, 10, 1, 5),
893 F(8000000, P_GPLL0_DIV, 1, 2, 75),
894 F(9600000, P_XO, 2, 0, 0),
895 F(16666667, P_GPLL0_DIV, 2, 1, 9),
896 F(19200000, P_XO, 1, 0, 0),
897 F(24000000, P_GPLL0_DIV, 1, 2, 25),
898 F(33333333, P_GPLL0_DIV, 1, 2, 9),
899 F(48000000, P_GPLL0, 1, 2, 25),
900 F(66666667, P_GPLL0, 1, 2, 9),
901 { }
902 };
903
904 static struct clk_rcg2 mclk0_clk_src = {
905 .cmd_rcgr = 0x3360,
906 .hid_width = 5,
907 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
908 .freq_tbl = ftbl_mclk_clk_src,
909 .clkr.hw.init = &(struct clk_init_data){
910 .name = "mclk0_clk_src",
911 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
912 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
913 .ops = &clk_rcg2_ops,
914 },
915 };
916
917 static struct clk_rcg2 mclk1_clk_src = {
918 .cmd_rcgr = 0x3390,
919 .hid_width = 5,
920 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
921 .freq_tbl = ftbl_mclk_clk_src,
922 .clkr.hw.init = &(struct clk_init_data){
923 .name = "mclk1_clk_src",
924 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
925 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
926 .ops = &clk_rcg2_ops,
927 },
928 };
929
930 static struct clk_rcg2 mclk2_clk_src = {
931 .cmd_rcgr = 0x33c0,
932 .hid_width = 5,
933 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
934 .freq_tbl = ftbl_mclk_clk_src,
935 .clkr.hw.init = &(struct clk_init_data){
936 .name = "mclk2_clk_src",
937 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
938 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
939 .ops = &clk_rcg2_ops,
940 },
941 };
942
943 static struct clk_rcg2 mclk3_clk_src = {
944 .cmd_rcgr = 0x33f0,
945 .hid_width = 5,
946 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
947 .freq_tbl = ftbl_mclk_clk_src,
948 .clkr.hw.init = &(struct clk_init_data){
949 .name = "mclk3_clk_src",
950 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
951 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
952 .ops = &clk_rcg2_ops,
953 },
954 };
955
956 static const struct freq_tbl ftbl_mdp_clk_src[] = {
957 F(85714286, P_GPLL0, 7, 0, 0),
958 F(100000000, P_GPLL0, 6, 0, 0),
959 F(150000000, P_GPLL0, 4, 0, 0),
960 F(171428571, P_GPLL0, 3.5, 0, 0),
961 F(200000000, P_GPLL0, 3, 0, 0),
962 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
963 F(300000000, P_GPLL0, 2, 0, 0),
964 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
965 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
966 { }
967 };
968
969 static struct clk_rcg2 mdp_clk_src = {
970 .cmd_rcgr = 0x2040,
971 .hid_width = 5,
972 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
973 .freq_tbl = ftbl_mdp_clk_src,
974 .clkr.hw.init = &(struct clk_init_data){
975 .name = "mdp_clk_src",
976 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
977 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
978 .ops = &clk_rcg2_ops,
979 },
980 };
981
982 static const struct freq_tbl ftbl_vsync_clk_src[] = {
983 F(19200000, P_XO, 1, 0, 0),
984 { }
985 };
986
987 static struct clk_rcg2 vsync_clk_src = {
988 .cmd_rcgr = 0x2080,
989 .hid_width = 5,
990 .parent_map = mmss_xo_gpll0_gpll0_div_map,
991 .freq_tbl = ftbl_vsync_clk_src,
992 .clkr.hw.init = &(struct clk_init_data){
993 .name = "vsync_clk_src",
994 .parent_data = mmss_xo_gpll0_gpll0_div,
995 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
996 .ops = &clk_rcg2_ops,
997 },
998 };
999
1000 static const struct freq_tbl ftbl_ahb_clk_src[] = {
1001 F(19200000, P_XO, 1, 0, 0),
1002 F(40000000, P_GPLL0, 15, 0, 0),
1003 F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
1004 { }
1005 };
1006
1007 static struct clk_rcg2 ahb_clk_src = {
1008 .cmd_rcgr = 0x5000,
1009 .hid_width = 5,
1010 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
1011 .freq_tbl = ftbl_ahb_clk_src,
1012 .clkr.hw.init = &(struct clk_init_data){
1013 .name = "ahb_clk_src",
1014 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
1015 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
1016 .ops = &clk_rcg2_ops,
1017 },
1018 };
1019
1020 static const struct freq_tbl ftbl_axi_clk_src[] = {
1021 F(75000000, P_GPLL0, 8, 0, 0),
1022 F(171428571, P_GPLL0, 3.5, 0, 0),
1023 F(240000000, P_GPLL0, 2.5, 0, 0),
1024 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1025 F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1026 { }
1027 };
1028
1029 /* RO to linux */
1030 static struct clk_rcg2 axi_clk_src = {
1031 .cmd_rcgr = 0xd000,
1032 .hid_width = 5,
1033 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
1034 .freq_tbl = ftbl_axi_clk_src,
1035 .clkr.hw.init = &(struct clk_init_data){
1036 .name = "axi_clk_src",
1037 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
1038 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
1039 .ops = &clk_rcg2_ops,
1040 },
1041 };
1042
1043 static struct clk_rcg2 pclk0_clk_src = {
1044 .cmd_rcgr = 0x2000,
1045 .mnd_width = 8,
1046 .hid_width = 5,
1047 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1048 .clkr.hw.init = &(struct clk_init_data){
1049 .name = "pclk0_clk_src",
1050 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1051 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
1052 .ops = &clk_pixel_ops,
1053 .flags = CLK_SET_RATE_PARENT,
1054 },
1055 };
1056
1057 static struct clk_rcg2 pclk1_clk_src = {
1058 .cmd_rcgr = 0x2020,
1059 .mnd_width = 8,
1060 .hid_width = 5,
1061 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1062 .clkr.hw.init = &(struct clk_init_data){
1063 .name = "pclk1_clk_src",
1064 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1065 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
1066 .ops = &clk_pixel_ops,
1067 .flags = CLK_SET_RATE_PARENT,
1068 },
1069 };
1070
1071 static const struct freq_tbl ftbl_rot_clk_src[] = {
1072 F(171428571, P_GPLL0, 3.5, 0, 0),
1073 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1074 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1075 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1076 { }
1077 };
1078
1079 static struct clk_rcg2 rot_clk_src = {
1080 .cmd_rcgr = 0x21a0,
1081 .hid_width = 5,
1082 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
1083 .freq_tbl = ftbl_rot_clk_src,
1084 .clkr.hw.init = &(struct clk_init_data){
1085 .name = "rot_clk_src",
1086 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
1087 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
1088 .ops = &clk_rcg2_ops,
1089 },
1090 };
1091
1092 static const struct freq_tbl ftbl_video_core_clk_src[] = {
1093 F(200000000, P_GPLL0, 3, 0, 0),
1094 F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1095 F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1096 F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1097 F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1098 { }
1099 };
1100
1101 static struct clk_rcg2 video_core_clk_src = {
1102 .cmd_rcgr = 0x1000,
1103 .hid_width = 5,
1104 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1105 .freq_tbl = ftbl_video_core_clk_src,
1106 .clkr.hw.init = &(struct clk_init_data){
1107 .name = "video_core_clk_src",
1108 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1109 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1110 .ops = &clk_rcg2_ops,
1111 },
1112 };
1113
1114 static struct clk_rcg2 video_subcore0_clk_src = {
1115 .cmd_rcgr = 0x1060,
1116 .hid_width = 5,
1117 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1118 .freq_tbl = ftbl_video_core_clk_src,
1119 .clkr.hw.init = &(struct clk_init_data){
1120 .name = "video_subcore0_clk_src",
1121 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1122 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1123 .ops = &clk_rcg2_ops,
1124 },
1125 };
1126
1127 static struct clk_rcg2 video_subcore1_clk_src = {
1128 .cmd_rcgr = 0x1080,
1129 .hid_width = 5,
1130 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1131 .freq_tbl = ftbl_video_core_clk_src,
1132 .clkr.hw.init = &(struct clk_init_data){
1133 .name = "video_subcore1_clk_src",
1134 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1135 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1136 .ops = &clk_rcg2_ops,
1137 },
1138 };
1139
1140 static const struct freq_tbl ftbl_vfe_clk_src[] = {
1141 F(200000000, P_GPLL0, 3, 0, 0),
1142 F(300000000, P_GPLL0, 2, 0, 0),
1143 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1144 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1145 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1146 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1147 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1148 F(600000000, P_GPLL0, 1, 0, 0),
1149 { }
1150 };
1151
1152 static struct clk_rcg2 vfe0_clk_src = {
1153 .cmd_rcgr = 0x3600,
1154 .hid_width = 5,
1155 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1156 .freq_tbl = ftbl_vfe_clk_src,
1157 .clkr.hw.init = &(struct clk_init_data){
1158 .name = "vfe0_clk_src",
1159 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1160 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
1161 .ops = &clk_rcg2_ops,
1162 },
1163 };
1164
1165 static struct clk_rcg2 vfe1_clk_src = {
1166 .cmd_rcgr = 0x3620,
1167 .hid_width = 5,
1168 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1169 .freq_tbl = ftbl_vfe_clk_src,
1170 .clkr.hw.init = &(struct clk_init_data){
1171 .name = "vfe1_clk_src",
1172 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1173 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
1174 .ops = &clk_rcg2_ops,
1175 },
1176 };
1177
1178 static struct clk_branch misc_ahb_clk = {
1179 .halt_reg = 0x328,
1180 .hwcg_reg = 0x328,
1181 .hwcg_bit = 1,
1182 .clkr = {
1183 .enable_reg = 0x328,
1184 .enable_mask = BIT(0),
1185 .hw.init = &(struct clk_init_data){
1186 .name = "misc_ahb_clk",
1187 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1188 .num_parents = 1,
1189 .ops = &clk_branch2_ops,
1190 .flags = CLK_SET_RATE_PARENT,
1191 },
1192 },
1193 };
1194
1195 static struct clk_branch video_core_clk = {
1196 .halt_reg = 0x1028,
1197 .clkr = {
1198 .enable_reg = 0x1028,
1199 .enable_mask = BIT(0),
1200 .hw.init = &(struct clk_init_data){
1201 .name = "video_core_clk",
1202 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
1203 .num_parents = 1,
1204 .ops = &clk_branch2_ops,
1205 .flags = CLK_SET_RATE_PARENT,
1206 },
1207 },
1208 };
1209
1210 static struct clk_branch video_ahb_clk = {
1211 .halt_reg = 0x1030,
1212 .hwcg_reg = 0x1030,
1213 .hwcg_bit = 1,
1214 .clkr = {
1215 .enable_reg = 0x1030,
1216 .enable_mask = BIT(0),
1217 .hw.init = &(struct clk_init_data){
1218 .name = "video_ahb_clk",
1219 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1220 .num_parents = 1,
1221 .ops = &clk_branch2_ops,
1222 .flags = CLK_SET_RATE_PARENT,
1223 },
1224 },
1225 };
1226
1227 static struct clk_branch video_axi_clk = {
1228 .halt_reg = 0x1034,
1229 .clkr = {
1230 .enable_reg = 0x1034,
1231 .enable_mask = BIT(0),
1232 .hw.init = &(struct clk_init_data){
1233 .name = "video_axi_clk",
1234 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1235 .num_parents = 1,
1236 .ops = &clk_branch2_ops,
1237 },
1238 },
1239 };
1240
1241 static struct clk_branch video_maxi_clk = {
1242 .halt_reg = 0x1038,
1243 .clkr = {
1244 .enable_reg = 0x1038,
1245 .enable_mask = BIT(0),
1246 .hw.init = &(struct clk_init_data){
1247 .name = "video_maxi_clk",
1248 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
1249 .num_parents = 1,
1250 .ops = &clk_branch2_ops,
1251 .flags = CLK_SET_RATE_PARENT,
1252 },
1253 },
1254 };
1255
1256 static struct clk_branch video_subcore0_clk = {
1257 .halt_reg = 0x1048,
1258 .clkr = {
1259 .enable_reg = 0x1048,
1260 .enable_mask = BIT(0),
1261 .hw.init = &(struct clk_init_data){
1262 .name = "video_subcore0_clk",
1263 .parent_hws = (const struct clk_hw *[]){ &video_subcore0_clk_src.clkr.hw },
1264 .num_parents = 1,
1265 .ops = &clk_branch2_ops,
1266 .flags = CLK_SET_RATE_PARENT,
1267 },
1268 },
1269 };
1270
1271 static struct clk_branch video_subcore1_clk = {
1272 .halt_reg = 0x104c,
1273 .clkr = {
1274 .enable_reg = 0x104c,
1275 .enable_mask = BIT(0),
1276 .hw.init = &(struct clk_init_data){
1277 .name = "video_subcore1_clk",
1278 .parent_hws = (const struct clk_hw *[]){ &video_subcore1_clk_src.clkr.hw },
1279 .num_parents = 1,
1280 .ops = &clk_branch2_ops,
1281 .flags = CLK_SET_RATE_PARENT,
1282 },
1283 },
1284 };
1285
1286 static struct clk_branch mdss_ahb_clk = {
1287 .halt_reg = 0x2308,
1288 .hwcg_reg = 0x2308,
1289 .hwcg_bit = 1,
1290 .clkr = {
1291 .enable_reg = 0x2308,
1292 .enable_mask = BIT(0),
1293 .hw.init = &(struct clk_init_data){
1294 .name = "mdss_ahb_clk",
1295 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1296 .num_parents = 1,
1297 .ops = &clk_branch2_ops,
1298 .flags = CLK_SET_RATE_PARENT,
1299 },
1300 },
1301 };
1302
1303 static struct clk_branch mdss_hdmi_dp_ahb_clk = {
1304 .halt_reg = 0x230c,
1305 .clkr = {
1306 .enable_reg = 0x230c,
1307 .enable_mask = BIT(0),
1308 .hw.init = &(struct clk_init_data){
1309 .name = "mdss_hdmi_dp_ahb_clk",
1310 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1311 .num_parents = 1,
1312 .ops = &clk_branch2_ops,
1313 .flags = CLK_SET_RATE_PARENT,
1314 },
1315 },
1316 };
1317
1318 static struct clk_branch mdss_axi_clk = {
1319 .halt_reg = 0x2310,
1320 .clkr = {
1321 .enable_reg = 0x2310,
1322 .enable_mask = BIT(0),
1323 .hw.init = &(struct clk_init_data){
1324 .name = "mdss_axi_clk",
1325 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1326 .num_parents = 1,
1327 .ops = &clk_branch2_ops,
1328 },
1329 },
1330 };
1331
1332 static struct clk_branch mdss_pclk0_clk = {
1333 .halt_reg = 0x2314,
1334 .clkr = {
1335 .enable_reg = 0x2314,
1336 .enable_mask = BIT(0),
1337 .hw.init = &(struct clk_init_data){
1338 .name = "mdss_pclk0_clk",
1339 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
1340 .num_parents = 1,
1341 .ops = &clk_branch2_ops,
1342 .flags = CLK_SET_RATE_PARENT,
1343 },
1344 },
1345 };
1346
1347 static struct clk_branch mdss_pclk1_clk = {
1348 .halt_reg = 0x2318,
1349 .clkr = {
1350 .enable_reg = 0x2318,
1351 .enable_mask = BIT(0),
1352 .hw.init = &(struct clk_init_data){
1353 .name = "mdss_pclk1_clk",
1354 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
1355 .num_parents = 1,
1356 .ops = &clk_branch2_ops,
1357 .flags = CLK_SET_RATE_PARENT,
1358 },
1359 },
1360 };
1361
1362 static struct clk_branch mdss_mdp_clk = {
1363 .halt_reg = 0x231c,
1364 .clkr = {
1365 .enable_reg = 0x231c,
1366 .enable_mask = BIT(0),
1367 .hw.init = &(struct clk_init_data){
1368 .name = "mdss_mdp_clk",
1369 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1370 .num_parents = 1,
1371 .ops = &clk_branch2_ops,
1372 .flags = CLK_SET_RATE_PARENT,
1373 },
1374 },
1375 };
1376
1377 static struct clk_branch mdss_mdp_lut_clk = {
1378 .halt_reg = 0x2320,
1379 .clkr = {
1380 .enable_reg = 0x2320,
1381 .enable_mask = BIT(0),
1382 .hw.init = &(struct clk_init_data){
1383 .name = "mdss_mdp_lut_clk",
1384 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1385 .num_parents = 1,
1386 .ops = &clk_branch2_ops,
1387 .flags = CLK_SET_RATE_PARENT,
1388 },
1389 },
1390 };
1391
1392 static struct clk_branch mdss_extpclk_clk = {
1393 .halt_reg = 0x2324,
1394 .clkr = {
1395 .enable_reg = 0x2324,
1396 .enable_mask = BIT(0),
1397 .hw.init = &(struct clk_init_data){
1398 .name = "mdss_extpclk_clk",
1399 .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1400 .num_parents = 1,
1401 .ops = &clk_branch2_ops,
1402 .flags = CLK_SET_RATE_PARENT,
1403 },
1404 },
1405 };
1406
1407 static struct clk_branch mdss_vsync_clk = {
1408 .halt_reg = 0x2328,
1409 .clkr = {
1410 .enable_reg = 0x2328,
1411 .enable_mask = BIT(0),
1412 .hw.init = &(struct clk_init_data){
1413 .name = "mdss_vsync_clk",
1414 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
1415 .num_parents = 1,
1416 .ops = &clk_branch2_ops,
1417 .flags = CLK_SET_RATE_PARENT,
1418 },
1419 },
1420 };
1421
1422 static struct clk_branch mdss_hdmi_clk = {
1423 .halt_reg = 0x2338,
1424 .clkr = {
1425 .enable_reg = 0x2338,
1426 .enable_mask = BIT(0),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "mdss_hdmi_clk",
1429 .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1430 .num_parents = 1,
1431 .ops = &clk_branch2_ops,
1432 .flags = CLK_SET_RATE_PARENT,
1433 },
1434 },
1435 };
1436
1437 static struct clk_branch mdss_byte0_clk = {
1438 .halt_reg = 0x233c,
1439 .clkr = {
1440 .enable_reg = 0x233c,
1441 .enable_mask = BIT(0),
1442 .hw.init = &(struct clk_init_data){
1443 .name = "mdss_byte0_clk",
1444 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1445 .num_parents = 1,
1446 .ops = &clk_branch2_ops,
1447 .flags = CLK_SET_RATE_PARENT,
1448 },
1449 },
1450 };
1451
1452 static struct clk_branch mdss_byte1_clk = {
1453 .halt_reg = 0x2340,
1454 .clkr = {
1455 .enable_reg = 0x2340,
1456 .enable_mask = BIT(0),
1457 .hw.init = &(struct clk_init_data){
1458 .name = "mdss_byte1_clk",
1459 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1460 .num_parents = 1,
1461 .ops = &clk_branch2_ops,
1462 .flags = CLK_SET_RATE_PARENT,
1463 },
1464 },
1465 };
1466
1467 static struct clk_branch mdss_esc0_clk = {
1468 .halt_reg = 0x2344,
1469 .clkr = {
1470 .enable_reg = 0x2344,
1471 .enable_mask = BIT(0),
1472 .hw.init = &(struct clk_init_data){
1473 .name = "mdss_esc0_clk",
1474 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1475 .num_parents = 1,
1476 .ops = &clk_branch2_ops,
1477 .flags = CLK_SET_RATE_PARENT,
1478 },
1479 },
1480 };
1481
1482 static struct clk_branch mdss_esc1_clk = {
1483 .halt_reg = 0x2348,
1484 .clkr = {
1485 .enable_reg = 0x2348,
1486 .enable_mask = BIT(0),
1487 .hw.init = &(struct clk_init_data){
1488 .name = "mdss_esc1_clk",
1489 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1490 .num_parents = 1,
1491 .ops = &clk_branch2_ops,
1492 .flags = CLK_SET_RATE_PARENT,
1493 },
1494 },
1495 };
1496
1497 static struct clk_branch mdss_rot_clk = {
1498 .halt_reg = 0x2350,
1499 .clkr = {
1500 .enable_reg = 0x2350,
1501 .enable_mask = BIT(0),
1502 .hw.init = &(struct clk_init_data){
1503 .name = "mdss_rot_clk",
1504 .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
1505 .num_parents = 1,
1506 .ops = &clk_branch2_ops,
1507 .flags = CLK_SET_RATE_PARENT,
1508 },
1509 },
1510 };
1511
1512 static struct clk_branch mdss_dp_link_clk = {
1513 .halt_reg = 0x2354,
1514 .clkr = {
1515 .enable_reg = 0x2354,
1516 .enable_mask = BIT(0),
1517 .hw.init = &(struct clk_init_data){
1518 .name = "mdss_dp_link_clk",
1519 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1520 .num_parents = 1,
1521 .ops = &clk_branch2_ops,
1522 .flags = CLK_SET_RATE_PARENT,
1523 },
1524 },
1525 };
1526
1527 static struct clk_branch mdss_dp_link_intf_clk = {
1528 .halt_reg = 0x2358,
1529 .clkr = {
1530 .enable_reg = 0x2358,
1531 .enable_mask = BIT(0),
1532 .hw.init = &(struct clk_init_data){
1533 .name = "mdss_dp_link_intf_clk",
1534 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1535 .num_parents = 1,
1536 .ops = &clk_branch2_ops,
1537 .flags = CLK_SET_RATE_PARENT,
1538 },
1539 },
1540 };
1541
1542 static struct clk_branch mdss_dp_crypto_clk = {
1543 .halt_reg = 0x235c,
1544 .clkr = {
1545 .enable_reg = 0x235c,
1546 .enable_mask = BIT(0),
1547 .hw.init = &(struct clk_init_data){
1548 .name = "mdss_dp_crypto_clk",
1549 .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
1550 .num_parents = 1,
1551 .ops = &clk_branch2_ops,
1552 .flags = CLK_SET_RATE_PARENT,
1553 },
1554 },
1555 };
1556
1557 static struct clk_branch mdss_dp_pixel_clk = {
1558 .halt_reg = 0x2360,
1559 .clkr = {
1560 .enable_reg = 0x2360,
1561 .enable_mask = BIT(0),
1562 .hw.init = &(struct clk_init_data){
1563 .name = "mdss_dp_pixel_clk",
1564 .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
1565 .num_parents = 1,
1566 .ops = &clk_branch2_ops,
1567 .flags = CLK_SET_RATE_PARENT,
1568 },
1569 },
1570 };
1571
1572 static struct clk_branch mdss_dp_aux_clk = {
1573 .halt_reg = 0x2364,
1574 .clkr = {
1575 .enable_reg = 0x2364,
1576 .enable_mask = BIT(0),
1577 .hw.init = &(struct clk_init_data){
1578 .name = "mdss_dp_aux_clk",
1579 .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
1580 .num_parents = 1,
1581 .ops = &clk_branch2_ops,
1582 .flags = CLK_SET_RATE_PARENT,
1583 },
1584 },
1585 };
1586
1587 static struct clk_branch mdss_byte0_intf_clk = {
1588 .halt_reg = 0x2374,
1589 .clkr = {
1590 .enable_reg = 0x2374,
1591 .enable_mask = BIT(0),
1592 .hw.init = &(struct clk_init_data){
1593 .name = "mdss_byte0_intf_clk",
1594 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1595 .num_parents = 1,
1596 .ops = &clk_branch2_ops,
1597 .flags = CLK_SET_RATE_PARENT,
1598 },
1599 },
1600 };
1601
1602 static struct clk_branch mdss_byte1_intf_clk = {
1603 .halt_reg = 0x2378,
1604 .clkr = {
1605 .enable_reg = 0x2378,
1606 .enable_mask = BIT(0),
1607 .hw.init = &(struct clk_init_data){
1608 .name = "mdss_byte1_intf_clk",
1609 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1610 .num_parents = 1,
1611 .ops = &clk_branch2_ops,
1612 .flags = CLK_SET_RATE_PARENT,
1613 },
1614 },
1615 };
1616
1617 static struct clk_branch camss_csi0phytimer_clk = {
1618 .halt_reg = 0x3024,
1619 .clkr = {
1620 .enable_reg = 0x3024,
1621 .enable_mask = BIT(0),
1622 .hw.init = &(struct clk_init_data){
1623 .name = "camss_csi0phytimer_clk",
1624 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1625 .num_parents = 1,
1626 .ops = &clk_branch2_ops,
1627 .flags = CLK_SET_RATE_PARENT,
1628 },
1629 },
1630 };
1631
1632 static struct clk_branch camss_csi1phytimer_clk = {
1633 .halt_reg = 0x3054,
1634 .clkr = {
1635 .enable_reg = 0x3054,
1636 .enable_mask = BIT(0),
1637 .hw.init = &(struct clk_init_data){
1638 .name = "camss_csi1phytimer_clk",
1639 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1640 .num_parents = 1,
1641 .ops = &clk_branch2_ops,
1642 .flags = CLK_SET_RATE_PARENT,
1643 },
1644 },
1645 };
1646
1647 static struct clk_branch camss_csi2phytimer_clk = {
1648 .halt_reg = 0x3084,
1649 .clkr = {
1650 .enable_reg = 0x3084,
1651 .enable_mask = BIT(0),
1652 .hw.init = &(struct clk_init_data){
1653 .name = "camss_csi2phytimer_clk",
1654 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1655 .num_parents = 1,
1656 .ops = &clk_branch2_ops,
1657 .flags = CLK_SET_RATE_PARENT,
1658 },
1659 },
1660 };
1661
1662 static struct clk_branch camss_csi0_clk = {
1663 .halt_reg = 0x30b4,
1664 .clkr = {
1665 .enable_reg = 0x30b4,
1666 .enable_mask = BIT(0),
1667 .hw.init = &(struct clk_init_data){
1668 .name = "camss_csi0_clk",
1669 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1670 .num_parents = 1,
1671 .ops = &clk_branch2_ops,
1672 .flags = CLK_SET_RATE_PARENT,
1673 },
1674 },
1675 };
1676
1677 static struct clk_branch camss_csi0_ahb_clk = {
1678 .halt_reg = 0x30bc,
1679 .clkr = {
1680 .enable_reg = 0x30bc,
1681 .enable_mask = BIT(0),
1682 .hw.init = &(struct clk_init_data){
1683 .name = "camss_csi0_ahb_clk",
1684 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1685 .num_parents = 1,
1686 .ops = &clk_branch2_ops,
1687 .flags = CLK_SET_RATE_PARENT,
1688 },
1689 },
1690 };
1691
1692 static struct clk_branch camss_csi0rdi_clk = {
1693 .halt_reg = 0x30d4,
1694 .clkr = {
1695 .enable_reg = 0x30d4,
1696 .enable_mask = BIT(0),
1697 .hw.init = &(struct clk_init_data){
1698 .name = "camss_csi0rdi_clk",
1699 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1700 .num_parents = 1,
1701 .ops = &clk_branch2_ops,
1702 .flags = CLK_SET_RATE_PARENT,
1703 },
1704 },
1705 };
1706
1707 static struct clk_branch camss_csi0pix_clk = {
1708 .halt_reg = 0x30e4,
1709 .clkr = {
1710 .enable_reg = 0x30e4,
1711 .enable_mask = BIT(0),
1712 .hw.init = &(struct clk_init_data){
1713 .name = "camss_csi0pix_clk",
1714 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1715 .num_parents = 1,
1716 .ops = &clk_branch2_ops,
1717 .flags = CLK_SET_RATE_PARENT,
1718 },
1719 },
1720 };
1721
1722 static struct clk_branch camss_csi1_clk = {
1723 .halt_reg = 0x3124,
1724 .clkr = {
1725 .enable_reg = 0x3124,
1726 .enable_mask = BIT(0),
1727 .hw.init = &(struct clk_init_data){
1728 .name = "camss_csi1_clk",
1729 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1730 .num_parents = 1,
1731 .ops = &clk_branch2_ops,
1732 .flags = CLK_SET_RATE_PARENT,
1733 },
1734 },
1735 };
1736
1737 static struct clk_branch camss_csi1_ahb_clk = {
1738 .halt_reg = 0x3128,
1739 .clkr = {
1740 .enable_reg = 0x3128,
1741 .enable_mask = BIT(0),
1742 .hw.init = &(struct clk_init_data){
1743 .name = "camss_csi1_ahb_clk",
1744 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1745 .num_parents = 1,
1746 .ops = &clk_branch2_ops,
1747 .flags = CLK_SET_RATE_PARENT,
1748 },
1749 },
1750 };
1751
1752 static struct clk_branch camss_csi1rdi_clk = {
1753 .halt_reg = 0x3144,
1754 .clkr = {
1755 .enable_reg = 0x3144,
1756 .enable_mask = BIT(0),
1757 .hw.init = &(struct clk_init_data){
1758 .name = "camss_csi1rdi_clk",
1759 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1760 .num_parents = 1,
1761 .ops = &clk_branch2_ops,
1762 .flags = CLK_SET_RATE_PARENT,
1763 },
1764 },
1765 };
1766
1767 static struct clk_branch camss_csi1pix_clk = {
1768 .halt_reg = 0x3154,
1769 .clkr = {
1770 .enable_reg = 0x3154,
1771 .enable_mask = BIT(0),
1772 .hw.init = &(struct clk_init_data){
1773 .name = "camss_csi1pix_clk",
1774 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1775 .num_parents = 1,
1776 .ops = &clk_branch2_ops,
1777 .flags = CLK_SET_RATE_PARENT,
1778 },
1779 },
1780 };
1781
1782 static struct clk_branch camss_csi2_clk = {
1783 .halt_reg = 0x3184,
1784 .clkr = {
1785 .enable_reg = 0x3184,
1786 .enable_mask = BIT(0),
1787 .hw.init = &(struct clk_init_data){
1788 .name = "camss_csi2_clk",
1789 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1790 .num_parents = 1,
1791 .ops = &clk_branch2_ops,
1792 .flags = CLK_SET_RATE_PARENT,
1793 },
1794 },
1795 };
1796
1797 static struct clk_branch camss_csi2_ahb_clk = {
1798 .halt_reg = 0x3188,
1799 .clkr = {
1800 .enable_reg = 0x3188,
1801 .enable_mask = BIT(0),
1802 .hw.init = &(struct clk_init_data){
1803 .name = "camss_csi2_ahb_clk",
1804 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1805 .num_parents = 1,
1806 .ops = &clk_branch2_ops,
1807 .flags = CLK_SET_RATE_PARENT,
1808 },
1809 },
1810 };
1811
1812 static struct clk_branch camss_csi2rdi_clk = {
1813 .halt_reg = 0x31a4,
1814 .clkr = {
1815 .enable_reg = 0x31a4,
1816 .enable_mask = BIT(0),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "camss_csi2rdi_clk",
1819 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1820 .num_parents = 1,
1821 .ops = &clk_branch2_ops,
1822 .flags = CLK_SET_RATE_PARENT,
1823 },
1824 },
1825 };
1826
1827 static struct clk_branch camss_csi2pix_clk = {
1828 .halt_reg = 0x31b4,
1829 .clkr = {
1830 .enable_reg = 0x31b4,
1831 .enable_mask = BIT(0),
1832 .hw.init = &(struct clk_init_data){
1833 .name = "camss_csi2pix_clk",
1834 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1835 .num_parents = 1,
1836 .ops = &clk_branch2_ops,
1837 .flags = CLK_SET_RATE_PARENT,
1838 },
1839 },
1840 };
1841
1842 static struct clk_branch camss_csi3_clk = {
1843 .halt_reg = 0x31e4,
1844 .clkr = {
1845 .enable_reg = 0x31e4,
1846 .enable_mask = BIT(0),
1847 .hw.init = &(struct clk_init_data){
1848 .name = "camss_csi3_clk",
1849 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1850 .num_parents = 1,
1851 .ops = &clk_branch2_ops,
1852 .flags = CLK_SET_RATE_PARENT,
1853 },
1854 },
1855 };
1856
1857 static struct clk_branch camss_csi3_ahb_clk = {
1858 .halt_reg = 0x31e8,
1859 .clkr = {
1860 .enable_reg = 0x31e8,
1861 .enable_mask = BIT(0),
1862 .hw.init = &(struct clk_init_data){
1863 .name = "camss_csi3_ahb_clk",
1864 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1865 .num_parents = 1,
1866 .ops = &clk_branch2_ops,
1867 .flags = CLK_SET_RATE_PARENT,
1868 },
1869 },
1870 };
1871
1872 static struct clk_branch camss_csi3rdi_clk = {
1873 .halt_reg = 0x3204,
1874 .clkr = {
1875 .enable_reg = 0x3204,
1876 .enable_mask = BIT(0),
1877 .hw.init = &(struct clk_init_data){
1878 .name = "camss_csi3rdi_clk",
1879 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1880 .num_parents = 1,
1881 .ops = &clk_branch2_ops,
1882 .flags = CLK_SET_RATE_PARENT,
1883 },
1884 },
1885 };
1886
1887 static struct clk_branch camss_csi3pix_clk = {
1888 .halt_reg = 0x3214,
1889 .clkr = {
1890 .enable_reg = 0x3214,
1891 .enable_mask = BIT(0),
1892 .hw.init = &(struct clk_init_data){
1893 .name = "camss_csi3pix_clk",
1894 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1895 .num_parents = 1,
1896 .ops = &clk_branch2_ops,
1897 .flags = CLK_SET_RATE_PARENT,
1898 },
1899 },
1900 };
1901
1902 static struct clk_branch camss_ispif_ahb_clk = {
1903 .halt_reg = 0x3224,
1904 .clkr = {
1905 .enable_reg = 0x3224,
1906 .enable_mask = BIT(0),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "camss_ispif_ahb_clk",
1909 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1910 .num_parents = 1,
1911 .ops = &clk_branch2_ops,
1912 .flags = CLK_SET_RATE_PARENT,
1913 },
1914 },
1915 };
1916
1917 static struct clk_branch camss_cci_clk = {
1918 .halt_reg = 0x3344,
1919 .clkr = {
1920 .enable_reg = 0x3344,
1921 .enable_mask = BIT(0),
1922 .hw.init = &(struct clk_init_data){
1923 .name = "camss_cci_clk",
1924 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1925 .num_parents = 1,
1926 .ops = &clk_branch2_ops,
1927 .flags = CLK_SET_RATE_PARENT,
1928 },
1929 },
1930 };
1931
1932 static struct clk_branch camss_cci_ahb_clk = {
1933 .halt_reg = 0x3348,
1934 .clkr = {
1935 .enable_reg = 0x3348,
1936 .enable_mask = BIT(0),
1937 .hw.init = &(struct clk_init_data){
1938 .name = "camss_cci_ahb_clk",
1939 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1940 .num_parents = 1,
1941 .ops = &clk_branch2_ops,
1942 .flags = CLK_SET_RATE_PARENT,
1943 },
1944 },
1945 };
1946
1947 static struct clk_branch camss_mclk0_clk = {
1948 .halt_reg = 0x3384,
1949 .clkr = {
1950 .enable_reg = 0x3384,
1951 .enable_mask = BIT(0),
1952 .hw.init = &(struct clk_init_data){
1953 .name = "camss_mclk0_clk",
1954 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1955 .num_parents = 1,
1956 .ops = &clk_branch2_ops,
1957 .flags = CLK_SET_RATE_PARENT,
1958 },
1959 },
1960 };
1961
1962 static struct clk_branch camss_mclk1_clk = {
1963 .halt_reg = 0x33b4,
1964 .clkr = {
1965 .enable_reg = 0x33b4,
1966 .enable_mask = BIT(0),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "camss_mclk1_clk",
1969 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1970 .num_parents = 1,
1971 .ops = &clk_branch2_ops,
1972 .flags = CLK_SET_RATE_PARENT,
1973 },
1974 },
1975 };
1976
1977 static struct clk_branch camss_mclk2_clk = {
1978 .halt_reg = 0x33e4,
1979 .clkr = {
1980 .enable_reg = 0x33e4,
1981 .enable_mask = BIT(0),
1982 .hw.init = &(struct clk_init_data){
1983 .name = "camss_mclk2_clk",
1984 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1985 .num_parents = 1,
1986 .ops = &clk_branch2_ops,
1987 .flags = CLK_SET_RATE_PARENT,
1988 },
1989 },
1990 };
1991
1992 static struct clk_branch camss_mclk3_clk = {
1993 .halt_reg = 0x3414,
1994 .clkr = {
1995 .enable_reg = 0x3414,
1996 .enable_mask = BIT(0),
1997 .hw.init = &(struct clk_init_data){
1998 .name = "camss_mclk3_clk",
1999 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
2000 .num_parents = 1,
2001 .ops = &clk_branch2_ops,
2002 .flags = CLK_SET_RATE_PARENT,
2003 },
2004 },
2005 };
2006
2007 static struct clk_branch camss_top_ahb_clk = {
2008 .halt_reg = 0x3484,
2009 .clkr = {
2010 .enable_reg = 0x3484,
2011 .enable_mask = BIT(0),
2012 .hw.init = &(struct clk_init_data){
2013 .name = "camss_top_ahb_clk",
2014 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2015 .num_parents = 1,
2016 .ops = &clk_branch2_ops,
2017 .flags = CLK_SET_RATE_PARENT,
2018 },
2019 },
2020 };
2021
2022 static struct clk_branch camss_ahb_clk = {
2023 .halt_reg = 0x348c,
2024 .clkr = {
2025 .enable_reg = 0x348c,
2026 .enable_mask = BIT(0),
2027 .hw.init = &(struct clk_init_data){
2028 .name = "camss_ahb_clk",
2029 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2030 .num_parents = 1,
2031 .ops = &clk_branch2_ops,
2032 .flags = CLK_SET_RATE_PARENT,
2033 },
2034 },
2035 };
2036
2037 static struct clk_branch camss_micro_ahb_clk = {
2038 .halt_reg = 0x3494,
2039 .clkr = {
2040 .enable_reg = 0x3494,
2041 .enable_mask = BIT(0),
2042 .hw.init = &(struct clk_init_data){
2043 .name = "camss_micro_ahb_clk",
2044 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2045 .num_parents = 1,
2046 .ops = &clk_branch2_ops,
2047 .flags = CLK_SET_RATE_PARENT,
2048 },
2049 },
2050 };
2051
2052 static struct clk_branch camss_jpeg0_clk = {
2053 .halt_reg = 0x35a8,
2054 .clkr = {
2055 .enable_reg = 0x35a8,
2056 .enable_mask = BIT(0),
2057 .hw.init = &(struct clk_init_data){
2058 .name = "camss_jpeg0_clk",
2059 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
2060 .num_parents = 1,
2061 .ops = &clk_branch2_ops,
2062 .flags = CLK_SET_RATE_PARENT,
2063 },
2064 },
2065 };
2066
2067 static struct clk_branch camss_jpeg_ahb_clk = {
2068 .halt_reg = 0x35b4,
2069 .clkr = {
2070 .enable_reg = 0x35b4,
2071 .enable_mask = BIT(0),
2072 .hw.init = &(struct clk_init_data){
2073 .name = "camss_jpeg_ahb_clk",
2074 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2075 .num_parents = 1,
2076 .ops = &clk_branch2_ops,
2077 .flags = CLK_SET_RATE_PARENT,
2078 },
2079 },
2080 };
2081
2082 static struct clk_branch camss_jpeg_axi_clk = {
2083 .halt_reg = 0x35b8,
2084 .clkr = {
2085 .enable_reg = 0x35b8,
2086 .enable_mask = BIT(0),
2087 .hw.init = &(struct clk_init_data){
2088 .name = "camss_jpeg_axi_clk",
2089 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2090 .num_parents = 1,
2091 .ops = &clk_branch2_ops,
2092 },
2093 },
2094 };
2095
2096 static struct clk_branch camss_vfe0_ahb_clk = {
2097 .halt_reg = 0x3668,
2098 .clkr = {
2099 .enable_reg = 0x3668,
2100 .enable_mask = BIT(0),
2101 .hw.init = &(struct clk_init_data){
2102 .name = "camss_vfe0_ahb_clk",
2103 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2104 .num_parents = 1,
2105 .ops = &clk_branch2_ops,
2106 .flags = CLK_SET_RATE_PARENT,
2107 },
2108 },
2109 };
2110
2111 static struct clk_branch camss_vfe1_ahb_clk = {
2112 .halt_reg = 0x3678,
2113 .clkr = {
2114 .enable_reg = 0x3678,
2115 .enable_mask = BIT(0),
2116 .hw.init = &(struct clk_init_data){
2117 .name = "camss_vfe1_ahb_clk",
2118 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2119 .num_parents = 1,
2120 .ops = &clk_branch2_ops,
2121 .flags = CLK_SET_RATE_PARENT,
2122 },
2123 },
2124 };
2125
2126 static struct clk_branch camss_vfe0_clk = {
2127 .halt_reg = 0x36a8,
2128 .clkr = {
2129 .enable_reg = 0x36a8,
2130 .enable_mask = BIT(0),
2131 .hw.init = &(struct clk_init_data){
2132 .name = "camss_vfe0_clk",
2133 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2134 .num_parents = 1,
2135 .ops = &clk_branch2_ops,
2136 .flags = CLK_SET_RATE_PARENT,
2137 },
2138 },
2139 };
2140
2141 static struct clk_branch camss_vfe1_clk = {
2142 .halt_reg = 0x36ac,
2143 .clkr = {
2144 .enable_reg = 0x36ac,
2145 .enable_mask = BIT(0),
2146 .hw.init = &(struct clk_init_data){
2147 .name = "camss_vfe1_clk",
2148 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2149 .num_parents = 1,
2150 .ops = &clk_branch2_ops,
2151 .flags = CLK_SET_RATE_PARENT,
2152 },
2153 },
2154 };
2155
2156 static struct clk_branch camss_cpp_clk = {
2157 .halt_reg = 0x36b0,
2158 .clkr = {
2159 .enable_reg = 0x36b0,
2160 .enable_mask = BIT(0),
2161 .hw.init = &(struct clk_init_data){
2162 .name = "camss_cpp_clk",
2163 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
2164 .num_parents = 1,
2165 .ops = &clk_branch2_ops,
2166 .flags = CLK_SET_RATE_PARENT,
2167 },
2168 },
2169 };
2170
2171 static struct clk_branch camss_cpp_ahb_clk = {
2172 .halt_reg = 0x36b4,
2173 .clkr = {
2174 .enable_reg = 0x36b4,
2175 .enable_mask = BIT(0),
2176 .hw.init = &(struct clk_init_data){
2177 .name = "camss_cpp_ahb_clk",
2178 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2179 .num_parents = 1,
2180 .ops = &clk_branch2_ops,
2181 .flags = CLK_SET_RATE_PARENT,
2182 },
2183 },
2184 };
2185
2186 static struct clk_branch camss_vfe_vbif_ahb_clk = {
2187 .halt_reg = 0x36b8,
2188 .clkr = {
2189 .enable_reg = 0x36b8,
2190 .enable_mask = BIT(0),
2191 .hw.init = &(struct clk_init_data){
2192 .name = "camss_vfe_vbif_ahb_clk",
2193 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2194 .num_parents = 1,
2195 .ops = &clk_branch2_ops,
2196 .flags = CLK_SET_RATE_PARENT,
2197 },
2198 },
2199 };
2200
2201 static struct clk_branch camss_vfe_vbif_axi_clk = {
2202 .halt_reg = 0x36bc,
2203 .clkr = {
2204 .enable_reg = 0x36bc,
2205 .enable_mask = BIT(0),
2206 .hw.init = &(struct clk_init_data){
2207 .name = "camss_vfe_vbif_axi_clk",
2208 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2209 .num_parents = 1,
2210 .ops = &clk_branch2_ops,
2211 },
2212 },
2213 };
2214
2215 static struct clk_branch camss_cpp_axi_clk = {
2216 .halt_reg = 0x36c4,
2217 .clkr = {
2218 .enable_reg = 0x36c4,
2219 .enable_mask = BIT(0),
2220 .hw.init = &(struct clk_init_data){
2221 .name = "camss_cpp_axi_clk",
2222 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2223 .num_parents = 1,
2224 .ops = &clk_branch2_ops,
2225 },
2226 },
2227 };
2228
2229 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2230 .halt_reg = 0x36c8,
2231 .clkr = {
2232 .enable_reg = 0x36c8,
2233 .enable_mask = BIT(0),
2234 .hw.init = &(struct clk_init_data){
2235 .name = "camss_cpp_vbif_ahb_clk",
2236 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2237 .num_parents = 1,
2238 .ops = &clk_branch2_ops,
2239 .flags = CLK_SET_RATE_PARENT,
2240 },
2241 },
2242 };
2243
2244 static struct clk_branch camss_csi_vfe0_clk = {
2245 .halt_reg = 0x3704,
2246 .clkr = {
2247 .enable_reg = 0x3704,
2248 .enable_mask = BIT(0),
2249 .hw.init = &(struct clk_init_data){
2250 .name = "camss_csi_vfe0_clk",
2251 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2252 .num_parents = 1,
2253 .ops = &clk_branch2_ops,
2254 .flags = CLK_SET_RATE_PARENT,
2255 },
2256 },
2257 };
2258
2259 static struct clk_branch camss_csi_vfe1_clk = {
2260 .halt_reg = 0x3714,
2261 .clkr = {
2262 .enable_reg = 0x3714,
2263 .enable_mask = BIT(0),
2264 .hw.init = &(struct clk_init_data){
2265 .name = "camss_csi_vfe1_clk",
2266 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2267 .num_parents = 1,
2268 .ops = &clk_branch2_ops,
2269 .flags = CLK_SET_RATE_PARENT,
2270 },
2271 },
2272 };
2273
2274 static struct clk_branch camss_vfe0_stream_clk = {
2275 .halt_reg = 0x3720,
2276 .clkr = {
2277 .enable_reg = 0x3720,
2278 .enable_mask = BIT(0),
2279 .hw.init = &(struct clk_init_data){
2280 .name = "camss_vfe0_stream_clk",
2281 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2282 .num_parents = 1,
2283 .ops = &clk_branch2_ops,
2284 .flags = CLK_SET_RATE_PARENT,
2285 },
2286 },
2287 };
2288
2289 static struct clk_branch camss_vfe1_stream_clk = {
2290 .halt_reg = 0x3724,
2291 .clkr = {
2292 .enable_reg = 0x3724,
2293 .enable_mask = BIT(0),
2294 .hw.init = &(struct clk_init_data){
2295 .name = "camss_vfe1_stream_clk",
2296 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2297 .num_parents = 1,
2298 .ops = &clk_branch2_ops,
2299 .flags = CLK_SET_RATE_PARENT,
2300 },
2301 },
2302 };
2303
2304 static struct clk_branch camss_cphy_csid0_clk = {
2305 .halt_reg = 0x3730,
2306 .clkr = {
2307 .enable_reg = 0x3730,
2308 .enable_mask = BIT(0),
2309 .hw.init = &(struct clk_init_data){
2310 .name = "camss_cphy_csid0_clk",
2311 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2312 .num_parents = 1,
2313 .ops = &clk_branch2_ops,
2314 .flags = CLK_SET_RATE_PARENT,
2315 },
2316 },
2317 };
2318
2319 static struct clk_branch camss_cphy_csid1_clk = {
2320 .halt_reg = 0x3734,
2321 .clkr = {
2322 .enable_reg = 0x3734,
2323 .enable_mask = BIT(0),
2324 .hw.init = &(struct clk_init_data){
2325 .name = "camss_cphy_csid1_clk",
2326 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2327 .num_parents = 1,
2328 .ops = &clk_branch2_ops,
2329 .flags = CLK_SET_RATE_PARENT,
2330 },
2331 },
2332 };
2333
2334 static struct clk_branch camss_cphy_csid2_clk = {
2335 .halt_reg = 0x3738,
2336 .clkr = {
2337 .enable_reg = 0x3738,
2338 .enable_mask = BIT(0),
2339 .hw.init = &(struct clk_init_data){
2340 .name = "camss_cphy_csid2_clk",
2341 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2342 .num_parents = 1,
2343 .ops = &clk_branch2_ops,
2344 .flags = CLK_SET_RATE_PARENT,
2345 },
2346 },
2347 };
2348
2349 static struct clk_branch camss_cphy_csid3_clk = {
2350 .halt_reg = 0x373c,
2351 .clkr = {
2352 .enable_reg = 0x373c,
2353 .enable_mask = BIT(0),
2354 .hw.init = &(struct clk_init_data){
2355 .name = "camss_cphy_csid3_clk",
2356 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2357 .num_parents = 1,
2358 .ops = &clk_branch2_ops,
2359 .flags = CLK_SET_RATE_PARENT,
2360 },
2361 },
2362 };
2363
2364 static struct clk_branch camss_csiphy0_clk = {
2365 .halt_reg = 0x3740,
2366 .clkr = {
2367 .enable_reg = 0x3740,
2368 .enable_mask = BIT(0),
2369 .hw.init = &(struct clk_init_data){
2370 .name = "camss_csiphy0_clk",
2371 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2372 .num_parents = 1,
2373 .ops = &clk_branch2_ops,
2374 .flags = CLK_SET_RATE_PARENT,
2375 },
2376 },
2377 };
2378
2379 static struct clk_branch camss_csiphy1_clk = {
2380 .halt_reg = 0x3744,
2381 .clkr = {
2382 .enable_reg = 0x3744,
2383 .enable_mask = BIT(0),
2384 .hw.init = &(struct clk_init_data){
2385 .name = "camss_csiphy1_clk",
2386 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2387 .num_parents = 1,
2388 .ops = &clk_branch2_ops,
2389 .flags = CLK_SET_RATE_PARENT,
2390 },
2391 },
2392 };
2393
2394 static struct clk_branch camss_csiphy2_clk = {
2395 .halt_reg = 0x3748,
2396 .clkr = {
2397 .enable_reg = 0x3748,
2398 .enable_mask = BIT(0),
2399 .hw.init = &(struct clk_init_data){
2400 .name = "camss_csiphy2_clk",
2401 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2402 .num_parents = 1,
2403 .ops = &clk_branch2_ops,
2404 .flags = CLK_SET_RATE_PARENT,
2405 },
2406 },
2407 };
2408
2409 static struct clk_branch fd_core_clk = {
2410 .halt_reg = 0x3b68,
2411 .clkr = {
2412 .enable_reg = 0x3b68,
2413 .enable_mask = BIT(0),
2414 .hw.init = &(struct clk_init_data){
2415 .name = "fd_core_clk",
2416 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2417 .num_parents = 1,
2418 .ops = &clk_branch2_ops,
2419 .flags = CLK_SET_RATE_PARENT,
2420 },
2421 },
2422 };
2423
2424 static struct clk_branch fd_core_uar_clk = {
2425 .halt_reg = 0x3b6c,
2426 .clkr = {
2427 .enable_reg = 0x3b6c,
2428 .enable_mask = BIT(0),
2429 .hw.init = &(struct clk_init_data){
2430 .name = "fd_core_uar_clk",
2431 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2432 .num_parents = 1,
2433 .ops = &clk_branch2_ops,
2434 .flags = CLK_SET_RATE_PARENT,
2435 },
2436 },
2437 };
2438
2439 static struct clk_branch fd_ahb_clk = {
2440 .halt_reg = 0x3b74,
2441 .clkr = {
2442 .enable_reg = 0x3b74,
2443 .enable_mask = BIT(0),
2444 .hw.init = &(struct clk_init_data){
2445 .name = "fd_ahb_clk",
2446 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2447 .num_parents = 1,
2448 .ops = &clk_branch2_ops,
2449 .flags = CLK_SET_RATE_PARENT,
2450 },
2451 },
2452 };
2453
2454 static struct clk_branch mnoc_ahb_clk = {
2455 .halt_reg = 0x5024,
2456 .clkr = {
2457 .enable_reg = 0x5024,
2458 .enable_mask = BIT(0),
2459 .hw.init = &(struct clk_init_data){
2460 .name = "mnoc_ahb_clk",
2461 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2462 .num_parents = 1,
2463 .ops = &clk_branch2_ops,
2464 .flags = CLK_SET_RATE_PARENT,
2465 },
2466 },
2467 };
2468
2469 static struct clk_branch bimc_smmu_ahb_clk = {
2470 .halt_reg = 0xe004,
2471 .hwcg_reg = 0xe004,
2472 .hwcg_bit = 1,
2473 .clkr = {
2474 .enable_reg = 0xe004,
2475 .enable_mask = BIT(0),
2476 .hw.init = &(struct clk_init_data){
2477 .name = "bimc_smmu_ahb_clk",
2478 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2479 .num_parents = 1,
2480 .ops = &clk_branch2_ops,
2481 .flags = CLK_SET_RATE_PARENT,
2482 },
2483 },
2484 };
2485
2486 static struct clk_branch bimc_smmu_axi_clk = {
2487 .halt_reg = 0xe008,
2488 .hwcg_reg = 0xe008,
2489 .hwcg_bit = 1,
2490 .clkr = {
2491 .enable_reg = 0xe008,
2492 .enable_mask = BIT(0),
2493 .hw.init = &(struct clk_init_data){
2494 .name = "bimc_smmu_axi_clk",
2495 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2496 .num_parents = 1,
2497 .ops = &clk_branch2_ops,
2498 },
2499 },
2500 };
2501
2502 static struct clk_branch mnoc_maxi_clk = {
2503 .halt_reg = 0xf004,
2504 .clkr = {
2505 .enable_reg = 0xf004,
2506 .enable_mask = BIT(0),
2507 .hw.init = &(struct clk_init_data){
2508 .name = "mnoc_maxi_clk",
2509 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2510 .num_parents = 1,
2511 .ops = &clk_branch2_ops,
2512 .flags = CLK_SET_RATE_PARENT,
2513 },
2514 },
2515 };
2516
2517 static struct clk_branch vmem_maxi_clk = {
2518 .halt_reg = 0xf064,
2519 .clkr = {
2520 .enable_reg = 0xf064,
2521 .enable_mask = BIT(0),
2522 .hw.init = &(struct clk_init_data){
2523 .name = "vmem_maxi_clk",
2524 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2525 .num_parents = 1,
2526 .ops = &clk_branch2_ops,
2527 .flags = CLK_SET_RATE_PARENT,
2528 },
2529 },
2530 };
2531
2532 static struct clk_branch vmem_ahb_clk = {
2533 .halt_reg = 0xf068,
2534 .clkr = {
2535 .enable_reg = 0xf068,
2536 .enable_mask = BIT(0),
2537 .hw.init = &(struct clk_init_data){
2538 .name = "vmem_ahb_clk",
2539 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2540 .num_parents = 1,
2541 .ops = &clk_branch2_ops,
2542 .flags = CLK_SET_RATE_PARENT,
2543 },
2544 },
2545 };
2546
2547 static struct clk_hw *mmcc_msm8998_hws[] = {
2548 &gpll0_div.hw,
2549 };
2550
2551 static struct gdsc video_top_gdsc = {
2552 .gdscr = 0x1024,
2553 .pd = {
2554 .name = "video_top",
2555 },
2556 .pwrsts = PWRSTS_OFF_ON,
2557 };
2558
2559 static struct gdsc video_subcore0_gdsc = {
2560 .gdscr = 0x1040,
2561 .pd = {
2562 .name = "video_subcore0",
2563 },
2564 .parent = &video_top_gdsc.pd,
2565 .pwrsts = PWRSTS_OFF_ON,
2566 };
2567
2568 static struct gdsc video_subcore1_gdsc = {
2569 .gdscr = 0x1044,
2570 .pd = {
2571 .name = "video_subcore1",
2572 },
2573 .parent = &video_top_gdsc.pd,
2574 .pwrsts = PWRSTS_OFF_ON,
2575 };
2576
2577 static struct gdsc mdss_gdsc = {
2578 .gdscr = 0x2304,
2579 .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2580 .cxc_count = 4,
2581 .pd = {
2582 .name = "mdss",
2583 },
2584 .pwrsts = PWRSTS_OFF_ON,
2585 };
2586
2587 static struct gdsc camss_top_gdsc = {
2588 .gdscr = 0x34a0,
2589 .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2590 0x35a8, 0x3868 },
2591 .cxc_count = 7,
2592 .pd = {
2593 .name = "camss_top",
2594 },
2595 .pwrsts = PWRSTS_OFF_ON,
2596 };
2597
2598 static struct gdsc camss_vfe0_gdsc = {
2599 .gdscr = 0x3664,
2600 .pd = {
2601 .name = "camss_vfe0",
2602 },
2603 .parent = &camss_top_gdsc.pd,
2604 .pwrsts = PWRSTS_OFF_ON,
2605 };
2606
2607 static struct gdsc camss_vfe1_gdsc = {
2608 .gdscr = 0x3674,
2609 .pd = {
2610 .name = "camss_vfe1_gdsc",
2611 },
2612 .parent = &camss_top_gdsc.pd,
2613 .pwrsts = PWRSTS_OFF_ON,
2614 };
2615
2616 static struct gdsc camss_cpp_gdsc = {
2617 .gdscr = 0x36d4,
2618 .pd = {
2619 .name = "camss_cpp",
2620 },
2621 .parent = &camss_top_gdsc.pd,
2622 .pwrsts = PWRSTS_OFF_ON,
2623 };
2624
2625 static struct gdsc bimc_smmu_gdsc = {
2626 .gdscr = 0xe020,
2627 .gds_hw_ctrl = 0xe024,
2628 .pd = {
2629 .name = "bimc_smmu",
2630 },
2631 .pwrsts = PWRSTS_OFF_ON,
2632 .flags = HW_CTRL | ALWAYS_ON,
2633 };
2634
2635 static struct clk_regmap *mmcc_msm8998_clocks[] = {
2636 [MMPLL0] = &mmpll0.clkr,
2637 [MMPLL0_OUT_EVEN] = &mmpll0_out_even.clkr,
2638 [MMPLL1] = &mmpll1.clkr,
2639 [MMPLL1_OUT_EVEN] = &mmpll1_out_even.clkr,
2640 [MMPLL3] = &mmpll3.clkr,
2641 [MMPLL3_OUT_EVEN] = &mmpll3_out_even.clkr,
2642 [MMPLL4] = &mmpll4.clkr,
2643 [MMPLL4_OUT_EVEN] = &mmpll4_out_even.clkr,
2644 [MMPLL5] = &mmpll5.clkr,
2645 [MMPLL5_OUT_EVEN] = &mmpll5_out_even.clkr,
2646 [MMPLL6] = &mmpll6.clkr,
2647 [MMPLL6_OUT_EVEN] = &mmpll6_out_even.clkr,
2648 [MMPLL7] = &mmpll7.clkr,
2649 [MMPLL7_OUT_EVEN] = &mmpll7_out_even.clkr,
2650 [MMPLL10] = &mmpll10.clkr,
2651 [MMPLL10_OUT_EVEN] = &mmpll10_out_even.clkr,
2652 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2653 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2654 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2655 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2656 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2657 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2658 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2659 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2660 [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
2661 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2662 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2663 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2664 [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
2665 [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
2666 [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
2667 [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
2668 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2669 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2670 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2671 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2672 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2673 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2674 [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
2675 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2676 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2677 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2678 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2679 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2680 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2681 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2682 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2683 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2684 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2685 [ROT_CLK_SRC] = &rot_clk_src.clkr,
2686 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2687 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
2688 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
2689 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2690 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2691 [MISC_AHB_CLK] = &misc_ahb_clk.clkr,
2692 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
2693 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
2694 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
2695 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
2696 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
2697 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
2698 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2699 [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
2700 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2701 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2702 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2703 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2704 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2705 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2706 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2707 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2708 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2709 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2710 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2711 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2712 [MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
2713 [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
2714 [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
2715 [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
2716 [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
2717 [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
2718 [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
2719 [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
2720 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
2721 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
2722 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
2723 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2724 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2725 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2726 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2727 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2728 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2729 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2730 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2731 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2732 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2733 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2734 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2735 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2736 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2737 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2738 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2739 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2740 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
2741 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
2742 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2743 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2744 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2745 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2746 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2747 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2748 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2749 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
2750 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
2751 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
2752 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
2753 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
2754 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
2755 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
2756 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
2757 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
2758 [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
2759 [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
2760 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
2761 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
2762 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2763 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2764 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
2765 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
2766 [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
2767 [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
2768 [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
2769 [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
2770 [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
2771 [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
2772 [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
2773 [FD_CORE_CLK] = &fd_core_clk.clkr,
2774 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2775 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
2776 [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
2777 [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
2778 [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
2779 [MNOC_MAXI_CLK] = &mnoc_maxi_clk.clkr,
2780 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
2781 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
2782 };
2783
2784 static struct gdsc *mmcc_msm8998_gdscs[] = {
2785 [VIDEO_TOP_GDSC] = &video_top_gdsc,
2786 [VIDEO_SUBCORE0_GDSC] = &video_subcore0_gdsc,
2787 [VIDEO_SUBCORE1_GDSC] = &video_subcore1_gdsc,
2788 [MDSS_GDSC] = &mdss_gdsc,
2789 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2790 [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
2791 [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
2792 [CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
2793 [BIMC_SMMU_GDSC] = &bimc_smmu_gdsc,
2794 };
2795
2796 static const struct qcom_reset_map mmcc_msm8998_resets[] = {
2797 [SPDM_BCR] = { 0x200 },
2798 [SPDM_RM_BCR] = { 0x300 },
2799 [MISC_BCR] = { 0x320 },
2800 [VIDEO_TOP_BCR] = { 0x1020 },
2801 [THROTTLE_VIDEO_BCR] = { 0x1180 },
2802 [MDSS_BCR] = { 0x2300 },
2803 [THROTTLE_MDSS_BCR] = { 0x2460 },
2804 [CAMSS_PHY0_BCR] = { 0x3020 },
2805 [CAMSS_PHY1_BCR] = { 0x3050 },
2806 [CAMSS_PHY2_BCR] = { 0x3080 },
2807 [CAMSS_CSI0_BCR] = { 0x30b0 },
2808 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2809 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2810 [CAMSS_CSI1_BCR] = { 0x3120 },
2811 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
2812 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
2813 [CAMSS_CSI2_BCR] = { 0x3180 },
2814 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2815 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2816 [CAMSS_CSI3_BCR] = { 0x31e0 },
2817 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
2818 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
2819 [CAMSS_ISPIF_BCR] = { 0x3220 },
2820 [CAMSS_CCI_BCR] = { 0x3340 },
2821 [CAMSS_TOP_BCR] = { 0x3480 },
2822 [CAMSS_AHB_BCR] = { 0x3488 },
2823 [CAMSS_MICRO_BCR] = { 0x3490 },
2824 [CAMSS_JPEG_BCR] = { 0x35a0 },
2825 [CAMSS_VFE0_BCR] = { 0x3660 },
2826 [CAMSS_VFE1_BCR] = { 0x3670 },
2827 [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2828 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2829 [CAMSS_CPP_BCR] = { 0x36d0 },
2830 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2831 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2832 [CAMSS_FD_BCR] = { 0x3b60 },
2833 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
2834 [MNOCAHB_BCR] = { 0x5020 },
2835 [MNOCAXI_BCR] = { 0xd020 },
2836 [BMIC_SMMU_BCR] = { 0xe000 },
2837 [MNOC_MAXI_BCR] = { 0xf000 },
2838 [VMEM_BCR] = { 0xf060 },
2839 [BTO_BCR] = { 0x10004 },
2840 };
2841
2842 static const struct regmap_config mmcc_msm8998_regmap_config = {
2843 .reg_bits = 32,
2844 .reg_stride = 4,
2845 .val_bits = 32,
2846 .max_register = 0x10004,
2847 .fast_io = true,
2848 };
2849
2850 static const struct qcom_cc_desc mmcc_msm8998_desc = {
2851 .config = &mmcc_msm8998_regmap_config,
2852 .clks = mmcc_msm8998_clocks,
2853 .num_clks = ARRAY_SIZE(mmcc_msm8998_clocks),
2854 .resets = mmcc_msm8998_resets,
2855 .num_resets = ARRAY_SIZE(mmcc_msm8998_resets),
2856 .gdscs = mmcc_msm8998_gdscs,
2857 .num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),
2858 .clk_hws = mmcc_msm8998_hws,
2859 .num_clk_hws = ARRAY_SIZE(mmcc_msm8998_hws),
2860 };
2861
2862 static const struct of_device_id mmcc_msm8998_match_table[] = {
2863 { .compatible = "qcom,mmcc-msm8998" },
2864 { }
2865 };
2866 MODULE_DEVICE_TABLE(of, mmcc_msm8998_match_table);
2867
mmcc_msm8998_probe(struct platform_device * pdev)2868 static int mmcc_msm8998_probe(struct platform_device *pdev)
2869 {
2870 struct regmap *regmap;
2871
2872 regmap = qcom_cc_map(pdev, &mmcc_msm8998_desc);
2873 if (IS_ERR(regmap))
2874 return PTR_ERR(regmap);
2875
2876 return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap);
2877 }
2878
2879 static struct platform_driver mmcc_msm8998_driver = {
2880 .probe = mmcc_msm8998_probe,
2881 .driver = {
2882 .name = "mmcc-msm8998",
2883 .of_match_table = mmcc_msm8998_match_table,
2884 },
2885 };
2886 module_platform_driver(mmcc_msm8998_driver);
2887
2888 MODULE_DESCRIPTION("QCOM MMCC MSM8998 Driver");
2889 MODULE_LICENSE("GPL v2");
2890