1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include <drm/drm_cache.h>
29 #include "amdgpu.h"
30 #include "gmc_v8_0.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_amdkfd.h"
33 #include "amdgpu_gem.h"
34
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
37
38 #include "bif/bif_5_0_d.h"
39 #include "bif/bif_5_0_sh_mask.h"
40
41 #include "oss/oss_3_0_d.h"
42 #include "oss/oss_3_0_sh_mask.h"
43
44 #include "dce/dce_10_0_d.h"
45 #include "dce/dce_10_0_sh_mask.h"
46
47 #include "vid.h"
48 #include "vi.h"
49
50 #include "amdgpu_atombios.h"
51
52 #include "ivsrcid/ivsrcid_vislands30.h"
53
54 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
55 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
56 static int gmc_v8_0_wait_for_idle(void *handle);
57
58 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
59 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
60 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
61 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
62 MODULE_FIRMWARE("amdgpu/polaris12_32_mc.bin");
63 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin");
64 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin");
65 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin");
66
67 static const u32 golden_settings_tonga_a11[] =
68 {
69 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
70 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
71 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
72 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
73 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
74 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
75 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
76 };
77
78 static const u32 tonga_mgcg_cgcg_init[] =
79 {
80 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
81 };
82
83 static const u32 golden_settings_fiji_a10[] =
84 {
85 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
86 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
87 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
88 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
89 };
90
91 static const u32 fiji_mgcg_cgcg_init[] =
92 {
93 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
94 };
95
96 static const u32 golden_settings_polaris11_a11[] =
97 {
98 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
99 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
100 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
101 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
102 };
103
104 static const u32 golden_settings_polaris10_a11[] =
105 {
106 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
107 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
108 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
109 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
110 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
111 };
112
113 static const u32 cz_mgcg_cgcg_init[] =
114 {
115 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
116 };
117
118 static const u32 stoney_mgcg_cgcg_init[] =
119 {
120 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
121 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
122 };
123
124 static const u32 golden_settings_stoney_common[] =
125 {
126 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
127 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
128 };
129
gmc_v8_0_init_golden_registers(struct amdgpu_device * adev)130 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
131 {
132 switch (adev->asic_type) {
133 case CHIP_FIJI:
134 amdgpu_device_program_register_sequence(adev,
135 fiji_mgcg_cgcg_init,
136 ARRAY_SIZE(fiji_mgcg_cgcg_init));
137 amdgpu_device_program_register_sequence(adev,
138 golden_settings_fiji_a10,
139 ARRAY_SIZE(golden_settings_fiji_a10));
140 break;
141 case CHIP_TONGA:
142 amdgpu_device_program_register_sequence(adev,
143 tonga_mgcg_cgcg_init,
144 ARRAY_SIZE(tonga_mgcg_cgcg_init));
145 amdgpu_device_program_register_sequence(adev,
146 golden_settings_tonga_a11,
147 ARRAY_SIZE(golden_settings_tonga_a11));
148 break;
149 case CHIP_POLARIS11:
150 case CHIP_POLARIS12:
151 case CHIP_VEGAM:
152 amdgpu_device_program_register_sequence(adev,
153 golden_settings_polaris11_a11,
154 ARRAY_SIZE(golden_settings_polaris11_a11));
155 break;
156 case CHIP_POLARIS10:
157 amdgpu_device_program_register_sequence(adev,
158 golden_settings_polaris10_a11,
159 ARRAY_SIZE(golden_settings_polaris10_a11));
160 break;
161 case CHIP_CARRIZO:
162 amdgpu_device_program_register_sequence(adev,
163 cz_mgcg_cgcg_init,
164 ARRAY_SIZE(cz_mgcg_cgcg_init));
165 break;
166 case CHIP_STONEY:
167 amdgpu_device_program_register_sequence(adev,
168 stoney_mgcg_cgcg_init,
169 ARRAY_SIZE(stoney_mgcg_cgcg_init));
170 amdgpu_device_program_register_sequence(adev,
171 golden_settings_stoney_common,
172 ARRAY_SIZE(golden_settings_stoney_common));
173 break;
174 default:
175 break;
176 }
177 }
178
gmc_v8_0_mc_stop(struct amdgpu_device * adev)179 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
180 {
181 u32 blackout;
182
183 gmc_v8_0_wait_for_idle(adev);
184
185 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
186 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
187 /* Block CPU access */
188 WREG32(mmBIF_FB_EN, 0);
189 /* blackout the MC */
190 blackout = REG_SET_FIELD(blackout,
191 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
192 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
193 }
194 /* wait for the MC to settle */
195 udelay(100);
196 }
197
gmc_v8_0_mc_resume(struct amdgpu_device * adev)198 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
199 {
200 u32 tmp;
201
202 /* unblackout the MC */
203 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
204 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
205 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
206 /* allow CPU access */
207 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
208 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
209 WREG32(mmBIF_FB_EN, tmp);
210 }
211
212 /**
213 * gmc_v8_0_init_microcode - load ucode images from disk
214 *
215 * @adev: amdgpu_device pointer
216 *
217 * Use the firmware interface to load the ucode images into
218 * the driver (not loaded into hw).
219 * Returns 0 on success, error on failure.
220 */
gmc_v8_0_init_microcode(struct amdgpu_device * adev)221 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
222 {
223 const char *chip_name;
224 char fw_name[30];
225 int err;
226
227 DRM_DEBUG("\n");
228
229 switch (adev->asic_type) {
230 case CHIP_TONGA:
231 chip_name = "tonga";
232 break;
233 case CHIP_POLARIS11:
234 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
235 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
236 chip_name = "polaris11_k";
237 else
238 chip_name = "polaris11";
239 break;
240 case CHIP_POLARIS10:
241 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))
242 chip_name = "polaris10_k";
243 else
244 chip_name = "polaris10";
245 break;
246 case CHIP_POLARIS12:
247 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
248 chip_name = "polaris12_k";
249 } else {
250 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159);
251 /* Polaris12 32bit ASIC needs a special MC firmware */
252 if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40)
253 chip_name = "polaris12_32";
254 else
255 chip_name = "polaris12";
256 }
257 break;
258 case CHIP_FIJI:
259 case CHIP_CARRIZO:
260 case CHIP_STONEY:
261 case CHIP_VEGAM:
262 return 0;
263 default: BUG();
264 }
265
266 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
267 err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name);
268 if (err) {
269 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
270 amdgpu_ucode_release(&adev->gmc.fw);
271 }
272 return err;
273 }
274
275 /**
276 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
277 *
278 * @adev: amdgpu_device pointer
279 *
280 * Load the GDDR MC ucode into the hw (VI).
281 * Returns 0 on success, error on failure.
282 */
gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device * adev)283 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
284 {
285 const struct mc_firmware_header_v1_0 *hdr;
286 const __le32 *fw_data = NULL;
287 const __le32 *io_mc_regs = NULL;
288 u32 running;
289 int i, ucode_size, regs_size;
290
291 /* Skip MC ucode loading on SR-IOV capable boards.
292 * vbios does this for us in asic_init in that case.
293 * Skip MC ucode loading on VF, because hypervisor will do that
294 * for this adaptor.
295 */
296 if (amdgpu_sriov_bios(adev))
297 return 0;
298
299 if (!adev->gmc.fw)
300 return -EINVAL;
301
302 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
303 amdgpu_ucode_print_mc_hdr(&hdr->header);
304
305 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
306 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
307 io_mc_regs = (const __le32 *)
308 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
309 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
310 fw_data = (const __le32 *)
311 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
312
313 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
314
315 if (running == 0) {
316 /* reset the engine and set to writable */
317 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
318 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
319
320 /* load mc io regs */
321 for (i = 0; i < regs_size; i++) {
322 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
323 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
324 }
325 /* load the MC ucode */
326 for (i = 0; i < ucode_size; i++)
327 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
328
329 /* put the engine back into the active state */
330 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
331 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
332 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
333
334 /* wait for training to complete */
335 for (i = 0; i < adev->usec_timeout; i++) {
336 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
337 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
338 break;
339 udelay(1);
340 }
341 for (i = 0; i < adev->usec_timeout; i++) {
342 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
343 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
344 break;
345 udelay(1);
346 }
347 }
348
349 return 0;
350 }
351
gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device * adev)352 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
353 {
354 const struct mc_firmware_header_v1_0 *hdr;
355 const __le32 *fw_data = NULL;
356 const __le32 *io_mc_regs = NULL;
357 u32 data;
358 int i, ucode_size, regs_size;
359
360 /* Skip MC ucode loading on SR-IOV capable boards.
361 * vbios does this for us in asic_init in that case.
362 * Skip MC ucode loading on VF, because hypervisor will do that
363 * for this adaptor.
364 */
365 if (amdgpu_sriov_bios(adev))
366 return 0;
367
368 if (!adev->gmc.fw)
369 return -EINVAL;
370
371 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
372 amdgpu_ucode_print_mc_hdr(&hdr->header);
373
374 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
375 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
376 io_mc_regs = (const __le32 *)
377 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
378 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
379 fw_data = (const __le32 *)
380 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
381
382 data = RREG32(mmMC_SEQ_MISC0);
383 data &= ~(0x40);
384 WREG32(mmMC_SEQ_MISC0, data);
385
386 /* load mc io regs */
387 for (i = 0; i < regs_size; i++) {
388 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
389 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
390 }
391
392 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
393 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
394
395 /* load the MC ucode */
396 for (i = 0; i < ucode_size; i++)
397 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
398
399 /* put the engine back into the active state */
400 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
401 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
402 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
403
404 /* wait for training to complete */
405 for (i = 0; i < adev->usec_timeout; i++) {
406 data = RREG32(mmMC_SEQ_MISC0);
407 if (data & 0x80)
408 break;
409 udelay(1);
410 }
411
412 return 0;
413 }
414
gmc_v8_0_vram_gtt_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)415 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
416 struct amdgpu_gmc *mc)
417 {
418 u64 base = 0;
419
420 if (!amdgpu_sriov_vf(adev))
421 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
422 base <<= 24;
423
424 amdgpu_gmc_vram_location(adev, mc, base);
425 amdgpu_gmc_gart_location(adev, mc);
426 }
427
428 /**
429 * gmc_v8_0_mc_program - program the GPU memory controller
430 *
431 * @adev: amdgpu_device pointer
432 *
433 * Set the location of vram, gart, and AGP in the GPU's
434 * physical address space (VI).
435 */
gmc_v8_0_mc_program(struct amdgpu_device * adev)436 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
437 {
438 u32 tmp;
439 int i, j;
440
441 /* Initialize HDP */
442 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
443 WREG32((0xb05 + j), 0x00000000);
444 WREG32((0xb06 + j), 0x00000000);
445 WREG32((0xb07 + j), 0x00000000);
446 WREG32((0xb08 + j), 0x00000000);
447 WREG32((0xb09 + j), 0x00000000);
448 }
449 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
450
451 if (gmc_v8_0_wait_for_idle((void *)adev)) {
452 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
453 }
454 if (adev->mode_info.num_crtc) {
455 /* Lockout access through VGA aperture*/
456 tmp = RREG32(mmVGA_HDP_CONTROL);
457 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
458 WREG32(mmVGA_HDP_CONTROL, tmp);
459
460 /* disable VGA render */
461 tmp = RREG32(mmVGA_RENDER_CONTROL);
462 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
463 WREG32(mmVGA_RENDER_CONTROL, tmp);
464 }
465 /* Update configuration */
466 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
467 adev->gmc.vram_start >> 12);
468 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
469 adev->gmc.vram_end >> 12);
470 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
471 adev->mem_scratch.gpu_addr >> 12);
472
473 if (amdgpu_sriov_vf(adev)) {
474 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
475 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
476 WREG32(mmMC_VM_FB_LOCATION, tmp);
477 /* XXX double check these! */
478 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
479 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
480 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
481 }
482
483 WREG32(mmMC_VM_AGP_BASE, 0);
484 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
485 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
486 if (gmc_v8_0_wait_for_idle((void *)adev)) {
487 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
488 }
489
490 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
491
492 tmp = RREG32(mmHDP_MISC_CNTL);
493 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
494 WREG32(mmHDP_MISC_CNTL, tmp);
495
496 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
497 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
498 }
499
500 /**
501 * gmc_v8_0_mc_init - initialize the memory controller driver params
502 *
503 * @adev: amdgpu_device pointer
504 *
505 * Look up the amount of vram, vram width, and decide how to place
506 * vram and gart within the GPU's physical address space (VI).
507 * Returns 0 for success.
508 */
gmc_v8_0_mc_init(struct amdgpu_device * adev)509 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
510 {
511 int r;
512 u32 tmp;
513
514 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
515 if (!adev->gmc.vram_width) {
516 int chansize, numchan;
517
518 /* Get VRAM informations */
519 tmp = RREG32(mmMC_ARB_RAMCFG);
520 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
521 chansize = 64;
522 } else {
523 chansize = 32;
524 }
525 tmp = RREG32(mmMC_SHARED_CHMAP);
526 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
527 case 0:
528 default:
529 numchan = 1;
530 break;
531 case 1:
532 numchan = 2;
533 break;
534 case 2:
535 numchan = 4;
536 break;
537 case 3:
538 numchan = 8;
539 break;
540 case 4:
541 numchan = 3;
542 break;
543 case 5:
544 numchan = 6;
545 break;
546 case 6:
547 numchan = 10;
548 break;
549 case 7:
550 numchan = 12;
551 break;
552 case 8:
553 numchan = 16;
554 break;
555 }
556 adev->gmc.vram_width = numchan * chansize;
557 }
558 /* size in MB on si */
559 tmp = RREG32(mmCONFIG_MEMSIZE);
560 /* some boards may have garbage in the upper 16 bits */
561 if (tmp & 0xffff0000) {
562 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
563 if (tmp & 0xffff)
564 tmp &= 0xffff;
565 }
566 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;
567 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
568
569 if (!(adev->flags & AMD_IS_APU)) {
570 r = amdgpu_device_resize_fb_bar(adev);
571 if (r)
572 return r;
573 }
574 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
575 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
576
577 #ifdef CONFIG_X86_64
578 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
579 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
580 adev->gmc.aper_size = adev->gmc.real_vram_size;
581 }
582 #endif
583
584 adev->gmc.visible_vram_size = adev->gmc.aper_size;
585
586 /* set the gart size */
587 if (amdgpu_gart_size == -1) {
588 switch (adev->asic_type) {
589 case CHIP_POLARIS10: /* all engines support GPUVM */
590 case CHIP_POLARIS11: /* all engines support GPUVM */
591 case CHIP_POLARIS12: /* all engines support GPUVM */
592 case CHIP_VEGAM: /* all engines support GPUVM */
593 default:
594 adev->gmc.gart_size = 256ULL << 20;
595 break;
596 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */
597 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */
598 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
599 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */
600 adev->gmc.gart_size = 1024ULL << 20;
601 break;
602 }
603 } else {
604 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
605 }
606
607 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
608 gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
609
610 return 0;
611 }
612
613 /**
614 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
615 *
616 * @adev: amdgpu_device pointer
617 * @pasid: pasid to be flush
618 * @flush_type: type of flush
619 * @all_hub: flush all hubs
620 *
621 * Flush the TLB for the requested pasid.
622 */
gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device * adev,uint16_t pasid,uint32_t flush_type,bool all_hub)623 static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
624 uint16_t pasid, uint32_t flush_type,
625 bool all_hub)
626 {
627 int vmid;
628 unsigned int tmp;
629
630 if (amdgpu_in_reset(adev))
631 return -EIO;
632
633 for (vmid = 1; vmid < 16; vmid++) {
634
635 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
636 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
637 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
638 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
639 RREG32(mmVM_INVALIDATE_RESPONSE);
640 break;
641 }
642 }
643
644 return 0;
645
646 }
647
648 /*
649 * GART
650 * VMID 0 is the physical GPU addresses as used by the kernel.
651 * VMIDs 1-15 are used for userspace clients and are handled
652 * by the amdgpu vm/hsa code.
653 */
654
655 /**
656 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
657 *
658 * @adev: amdgpu_device pointer
659 * @vmid: vm instance to flush
660 * @vmhub: which hub to flush
661 * @flush_type: type of flush
662 *
663 * Flush the TLB for the requested page table (VI).
664 */
gmc_v8_0_flush_gpu_tlb(struct amdgpu_device * adev,uint32_t vmid,uint32_t vmhub,uint32_t flush_type)665 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
666 uint32_t vmhub, uint32_t flush_type)
667 {
668 /* bits 0-15 are the VM contexts0-15 */
669 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
670 }
671
gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)672 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
673 unsigned vmid, uint64_t pd_addr)
674 {
675 uint32_t reg;
676
677 if (vmid < 8)
678 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
679 else
680 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
681 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
682
683 /* bits 0-15 are the VM contexts0-15 */
684 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
685
686 return pd_addr;
687 }
688
gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring * ring,unsigned vmid,unsigned pasid)689 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
690 unsigned pasid)
691 {
692 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
693 }
694
695 /*
696 * PTE format on VI:
697 * 63:40 reserved
698 * 39:12 4k physical page base address
699 * 11:7 fragment
700 * 6 write
701 * 5 read
702 * 4 exe
703 * 3 reserved
704 * 2 snooped
705 * 1 system
706 * 0 valid
707 *
708 * PDE format on VI:
709 * 63:59 block fragment size
710 * 58:40 reserved
711 * 39:1 physical base address of PTE
712 * bits 5:1 must be 0.
713 * 0 valid
714 */
715
gmc_v8_0_get_vm_pde(struct amdgpu_device * adev,int level,uint64_t * addr,uint64_t * flags)716 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
717 uint64_t *addr, uint64_t *flags)
718 {
719 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
720 }
721
gmc_v8_0_get_vm_pte(struct amdgpu_device * adev,struct amdgpu_bo_va_mapping * mapping,uint64_t * flags)722 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev,
723 struct amdgpu_bo_va_mapping *mapping,
724 uint64_t *flags)
725 {
726 *flags &= ~AMDGPU_PTE_EXECUTABLE;
727 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
728 *flags &= ~AMDGPU_PTE_PRT;
729 }
730
731 /**
732 * gmc_v8_0_set_fault_enable_default - update VM fault handling
733 *
734 * @adev: amdgpu_device pointer
735 * @value: true redirects VM faults to the default page
736 */
gmc_v8_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)737 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
738 bool value)
739 {
740 u32 tmp;
741
742 tmp = RREG32(mmVM_CONTEXT1_CNTL);
743 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
744 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
745 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
746 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
747 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
748 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
749 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
750 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
751 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
752 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
753 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
754 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
755 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
756 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
757 WREG32(mmVM_CONTEXT1_CNTL, tmp);
758 }
759
760 /**
761 * gmc_v8_0_set_prt - set PRT VM fault
762 *
763 * @adev: amdgpu_device pointer
764 * @enable: enable/disable VM fault handling for PRT
765 */
gmc_v8_0_set_prt(struct amdgpu_device * adev,bool enable)766 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
767 {
768 u32 tmp;
769
770 if (enable && !adev->gmc.prt_warning) {
771 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
772 adev->gmc.prt_warning = true;
773 }
774
775 tmp = RREG32(mmVM_PRT_CNTL);
776 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
777 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
778 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
779 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
780 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
781 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
782 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
783 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
784 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
785 L2_CACHE_STORE_INVALID_ENTRIES, enable);
786 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
787 L1_TLB_STORE_INVALID_ENTRIES, enable);
788 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
789 MASK_PDE0_FAULT, enable);
790 WREG32(mmVM_PRT_CNTL, tmp);
791
792 if (enable) {
793 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
794 uint32_t high = adev->vm_manager.max_pfn -
795 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
796
797 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
798 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
799 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
800 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
801 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
802 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
803 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
804 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
805 } else {
806 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
807 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
808 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
809 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
810 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
811 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
812 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
813 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
814 }
815 }
816
817 /**
818 * gmc_v8_0_gart_enable - gart enable
819 *
820 * @adev: amdgpu_device pointer
821 *
822 * This sets up the TLBs, programs the page tables for VMID0,
823 * sets up the hw for VMIDs 1-15 which are allocated on
824 * demand, and sets up the global locations for the LDS, GDS,
825 * and GPUVM for FSA64 clients (VI).
826 * Returns 0 for success, errors for failure.
827 */
gmc_v8_0_gart_enable(struct amdgpu_device * adev)828 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
829 {
830 uint64_t table_addr;
831 u32 tmp, field;
832 int i;
833
834 if (adev->gart.bo == NULL) {
835 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
836 return -EINVAL;
837 }
838 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
839 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
840
841 /* Setup TLB control */
842 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
843 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
844 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
845 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
846 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
847 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
848 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
849 /* Setup L2 cache */
850 tmp = RREG32(mmVM_L2_CNTL);
851 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
858 WREG32(mmVM_L2_CNTL, tmp);
859 tmp = RREG32(mmVM_L2_CNTL2);
860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
862 WREG32(mmVM_L2_CNTL2, tmp);
863
864 field = adev->vm_manager.fragment_size;
865 tmp = RREG32(mmVM_L2_CNTL3);
866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
868 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
869 WREG32(mmVM_L2_CNTL3, tmp);
870 /* XXX: set to enable PTE/PDE in system memory */
871 tmp = RREG32(mmVM_L2_CNTL4);
872 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
873 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
874 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
876 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
877 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
879 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
880 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
881 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
882 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
883 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
884 WREG32(mmVM_L2_CNTL4, tmp);
885 /* setup context0 */
886 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
887 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
888 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
889 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
890 (u32)(adev->dummy_page_addr >> 12));
891 WREG32(mmVM_CONTEXT0_CNTL2, 0);
892 tmp = RREG32(mmVM_CONTEXT0_CNTL);
893 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
894 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
895 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
896 WREG32(mmVM_CONTEXT0_CNTL, tmp);
897
898 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
899 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
900 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
901
902 /* empty context1-15 */
903 /* FIXME start with 4G, once using 2 level pt switch to full
904 * vm size space
905 */
906 /* set vm size, must be a multiple of 4 */
907 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
908 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
909 for (i = 1; i < AMDGPU_NUM_VMID; i++) {
910 if (i < 8)
911 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
912 table_addr >> 12);
913 else
914 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
915 table_addr >> 12);
916 }
917
918 /* enable context1-15 */
919 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
920 (u32)(adev->dummy_page_addr >> 12));
921 WREG32(mmVM_CONTEXT1_CNTL2, 4);
922 tmp = RREG32(mmVM_CONTEXT1_CNTL);
923 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
924 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
925 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
926 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
927 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
928 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
929 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
930 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
931 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
932 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
933 adev->vm_manager.block_size - 9);
934 WREG32(mmVM_CONTEXT1_CNTL, tmp);
935 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
936 gmc_v8_0_set_fault_enable_default(adev, false);
937 else
938 gmc_v8_0_set_fault_enable_default(adev, true);
939
940 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0);
941 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
942 (unsigned)(adev->gmc.gart_size >> 20),
943 (unsigned long long)table_addr);
944 return 0;
945 }
946
gmc_v8_0_gart_init(struct amdgpu_device * adev)947 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
948 {
949 int r;
950
951 if (adev->gart.bo) {
952 WARN(1, "R600 PCIE GART already initialized\n");
953 return 0;
954 }
955 /* Initialize common gart structure */
956 r = amdgpu_gart_init(adev);
957 if (r)
958 return r;
959 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
960 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
961 return amdgpu_gart_table_vram_alloc(adev);
962 }
963
964 /**
965 * gmc_v8_0_gart_disable - gart disable
966 *
967 * @adev: amdgpu_device pointer
968 *
969 * This disables all VM page table (VI).
970 */
gmc_v8_0_gart_disable(struct amdgpu_device * adev)971 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
972 {
973 u32 tmp;
974
975 /* Disable all tables */
976 WREG32(mmVM_CONTEXT0_CNTL, 0);
977 WREG32(mmVM_CONTEXT1_CNTL, 0);
978 /* Setup TLB control */
979 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
980 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
981 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
982 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
983 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
984 /* Setup L2 cache */
985 tmp = RREG32(mmVM_L2_CNTL);
986 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
987 WREG32(mmVM_L2_CNTL, tmp);
988 WREG32(mmVM_L2_CNTL2, 0);
989 }
990
991 /**
992 * gmc_v8_0_vm_decode_fault - print human readable fault info
993 *
994 * @adev: amdgpu_device pointer
995 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
996 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
997 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
998 * @pasid: debug logging only - no functional use
999 *
1000 * Print human readable fault information (VI).
1001 */
gmc_v8_0_vm_decode_fault(struct amdgpu_device * adev,u32 status,u32 addr,u32 mc_client,unsigned pasid)1002 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
1003 u32 addr, u32 mc_client, unsigned pasid)
1004 {
1005 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
1006 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1007 PROTECTIONS);
1008 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
1009 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
1010 u32 mc_id;
1011
1012 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1013 MEMORY_CLIENT_ID);
1014
1015 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1016 protections, vmid, pasid, addr,
1017 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1018 MEMORY_CLIENT_RW) ?
1019 "write" : "read", block, mc_client, mc_id);
1020 }
1021
gmc_v8_0_convert_vram_type(int mc_seq_vram_type)1022 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1023 {
1024 switch (mc_seq_vram_type) {
1025 case MC_SEQ_MISC0__MT__GDDR1:
1026 return AMDGPU_VRAM_TYPE_GDDR1;
1027 case MC_SEQ_MISC0__MT__DDR2:
1028 return AMDGPU_VRAM_TYPE_DDR2;
1029 case MC_SEQ_MISC0__MT__GDDR3:
1030 return AMDGPU_VRAM_TYPE_GDDR3;
1031 case MC_SEQ_MISC0__MT__GDDR4:
1032 return AMDGPU_VRAM_TYPE_GDDR4;
1033 case MC_SEQ_MISC0__MT__GDDR5:
1034 return AMDGPU_VRAM_TYPE_GDDR5;
1035 case MC_SEQ_MISC0__MT__HBM:
1036 return AMDGPU_VRAM_TYPE_HBM;
1037 case MC_SEQ_MISC0__MT__DDR3:
1038 return AMDGPU_VRAM_TYPE_DDR3;
1039 default:
1040 return AMDGPU_VRAM_TYPE_UNKNOWN;
1041 }
1042 }
1043
gmc_v8_0_early_init(void * handle)1044 static int gmc_v8_0_early_init(void *handle)
1045 {
1046 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1047
1048 gmc_v8_0_set_gmc_funcs(adev);
1049 gmc_v8_0_set_irq_funcs(adev);
1050
1051 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1052 adev->gmc.shared_aperture_end =
1053 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1054 adev->gmc.private_aperture_start =
1055 adev->gmc.shared_aperture_end + 1;
1056 adev->gmc.private_aperture_end =
1057 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1058
1059 return 0;
1060 }
1061
gmc_v8_0_late_init(void * handle)1062 static int gmc_v8_0_late_init(void *handle)
1063 {
1064 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1065
1066 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1067 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1068 else
1069 return 0;
1070 }
1071
gmc_v8_0_get_vbios_fb_size(struct amdgpu_device * adev)1072 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1073 {
1074 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1075 unsigned size;
1076
1077 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1078 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1079 } else {
1080 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1081 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1082 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1083 4);
1084 }
1085
1086 return size;
1087 }
1088
1089 #define mmMC_SEQ_MISC0_FIJI 0xA71
1090
gmc_v8_0_sw_init(void * handle)1091 static int gmc_v8_0_sw_init(void *handle)
1092 {
1093 int r;
1094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1095
1096 adev->num_vmhubs = 1;
1097
1098 if (adev->flags & AMD_IS_APU) {
1099 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1100 } else {
1101 u32 tmp;
1102
1103 if ((adev->asic_type == CHIP_FIJI) ||
1104 (adev->asic_type == CHIP_VEGAM))
1105 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1106 else
1107 tmp = RREG32(mmMC_SEQ_MISC0);
1108 tmp &= MC_SEQ_MISC0__MT__MASK;
1109 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1110 }
1111
1112 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1113 if (r)
1114 return r;
1115
1116 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1117 if (r)
1118 return r;
1119
1120 /* Adjust VM size here.
1121 * Currently set to 4GB ((1 << 20) 4k pages).
1122 * Max GPUVM size for cayman and SI is 40 bits.
1123 */
1124 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1125
1126 /* Set the internal MC address mask
1127 * This is the max address of the GPU's
1128 * internal address space.
1129 */
1130 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1131
1132 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1133 if (r) {
1134 pr_warn("No suitable DMA available\n");
1135 return r;
1136 }
1137 adev->need_swiotlb = drm_need_swiotlb(40);
1138
1139 r = gmc_v8_0_init_microcode(adev);
1140 if (r) {
1141 DRM_ERROR("Failed to load mc firmware!\n");
1142 return r;
1143 }
1144
1145 r = gmc_v8_0_mc_init(adev);
1146 if (r)
1147 return r;
1148
1149 amdgpu_gmc_get_vbios_allocations(adev);
1150
1151 /* Memory manager */
1152 r = amdgpu_bo_init(adev);
1153 if (r)
1154 return r;
1155
1156 r = gmc_v8_0_gart_init(adev);
1157 if (r)
1158 return r;
1159
1160 /*
1161 * number of VMs
1162 * VMID 0 is reserved for System
1163 * amdgpu graphics/compute will use VMIDs 1-7
1164 * amdkfd will use VMIDs 8-15
1165 */
1166 adev->vm_manager.first_kfd_vmid = 8;
1167 amdgpu_vm_manager_init(adev);
1168
1169 /* base offset of vram pages */
1170 if (adev->flags & AMD_IS_APU) {
1171 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1172
1173 tmp <<= 22;
1174 adev->vm_manager.vram_base_offset = tmp;
1175 } else {
1176 adev->vm_manager.vram_base_offset = 0;
1177 }
1178
1179 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1180 GFP_KERNEL);
1181 if (!adev->gmc.vm_fault_info)
1182 return -ENOMEM;
1183 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1184
1185 return 0;
1186 }
1187
gmc_v8_0_sw_fini(void * handle)1188 static int gmc_v8_0_sw_fini(void *handle)
1189 {
1190 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1191
1192 amdgpu_gem_force_release(adev);
1193 amdgpu_vm_manager_fini(adev);
1194 kfree(adev->gmc.vm_fault_info);
1195 amdgpu_gart_table_vram_free(adev);
1196 amdgpu_bo_fini(adev);
1197 amdgpu_ucode_release(&adev->gmc.fw);
1198
1199 return 0;
1200 }
1201
gmc_v8_0_hw_init(void * handle)1202 static int gmc_v8_0_hw_init(void *handle)
1203 {
1204 int r;
1205 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1206
1207 gmc_v8_0_init_golden_registers(adev);
1208
1209 gmc_v8_0_mc_program(adev);
1210
1211 if (adev->asic_type == CHIP_TONGA) {
1212 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1213 if (r) {
1214 DRM_ERROR("Failed to load MC firmware!\n");
1215 return r;
1216 }
1217 } else if (adev->asic_type == CHIP_POLARIS11 ||
1218 adev->asic_type == CHIP_POLARIS10 ||
1219 adev->asic_type == CHIP_POLARIS12) {
1220 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1221 if (r) {
1222 DRM_ERROR("Failed to load MC firmware!\n");
1223 return r;
1224 }
1225 }
1226
1227 r = gmc_v8_0_gart_enable(adev);
1228 if (r)
1229 return r;
1230
1231 if (amdgpu_emu_mode == 1)
1232 return amdgpu_gmc_vram_checking(adev);
1233 else
1234 return r;
1235 }
1236
gmc_v8_0_hw_fini(void * handle)1237 static int gmc_v8_0_hw_fini(void *handle)
1238 {
1239 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1240
1241 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1242 gmc_v8_0_gart_disable(adev);
1243
1244 return 0;
1245 }
1246
gmc_v8_0_suspend(void * handle)1247 static int gmc_v8_0_suspend(void *handle)
1248 {
1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250
1251 gmc_v8_0_hw_fini(adev);
1252
1253 return 0;
1254 }
1255
gmc_v8_0_resume(void * handle)1256 static int gmc_v8_0_resume(void *handle)
1257 {
1258 int r;
1259 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1260
1261 r = gmc_v8_0_hw_init(adev);
1262 if (r)
1263 return r;
1264
1265 amdgpu_vmid_reset_all(adev);
1266
1267 return 0;
1268 }
1269
gmc_v8_0_is_idle(void * handle)1270 static bool gmc_v8_0_is_idle(void *handle)
1271 {
1272 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1273 u32 tmp = RREG32(mmSRBM_STATUS);
1274
1275 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1276 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1277 return false;
1278
1279 return true;
1280 }
1281
gmc_v8_0_wait_for_idle(void * handle)1282 static int gmc_v8_0_wait_for_idle(void *handle)
1283 {
1284 unsigned i;
1285 u32 tmp;
1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1287
1288 for (i = 0; i < adev->usec_timeout; i++) {
1289 /* read MC_STATUS */
1290 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1291 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1292 SRBM_STATUS__MCC_BUSY_MASK |
1293 SRBM_STATUS__MCD_BUSY_MASK |
1294 SRBM_STATUS__VMC_BUSY_MASK |
1295 SRBM_STATUS__VMC1_BUSY_MASK);
1296 if (!tmp)
1297 return 0;
1298 udelay(1);
1299 }
1300 return -ETIMEDOUT;
1301
1302 }
1303
gmc_v8_0_check_soft_reset(void * handle)1304 static bool gmc_v8_0_check_soft_reset(void *handle)
1305 {
1306 u32 srbm_soft_reset = 0;
1307 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1308 u32 tmp = RREG32(mmSRBM_STATUS);
1309
1310 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1311 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1312 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1313
1314 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1315 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1316 if (!(adev->flags & AMD_IS_APU))
1317 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1318 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1319 }
1320 if (srbm_soft_reset) {
1321 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1322 return true;
1323 } else {
1324 adev->gmc.srbm_soft_reset = 0;
1325 return false;
1326 }
1327 }
1328
gmc_v8_0_pre_soft_reset(void * handle)1329 static int gmc_v8_0_pre_soft_reset(void *handle)
1330 {
1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1332
1333 if (!adev->gmc.srbm_soft_reset)
1334 return 0;
1335
1336 gmc_v8_0_mc_stop(adev);
1337 if (gmc_v8_0_wait_for_idle(adev)) {
1338 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1339 }
1340
1341 return 0;
1342 }
1343
gmc_v8_0_soft_reset(void * handle)1344 static int gmc_v8_0_soft_reset(void *handle)
1345 {
1346 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1347 u32 srbm_soft_reset;
1348
1349 if (!adev->gmc.srbm_soft_reset)
1350 return 0;
1351 srbm_soft_reset = adev->gmc.srbm_soft_reset;
1352
1353 if (srbm_soft_reset) {
1354 u32 tmp;
1355
1356 tmp = RREG32(mmSRBM_SOFT_RESET);
1357 tmp |= srbm_soft_reset;
1358 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1359 WREG32(mmSRBM_SOFT_RESET, tmp);
1360 tmp = RREG32(mmSRBM_SOFT_RESET);
1361
1362 udelay(50);
1363
1364 tmp &= ~srbm_soft_reset;
1365 WREG32(mmSRBM_SOFT_RESET, tmp);
1366 tmp = RREG32(mmSRBM_SOFT_RESET);
1367
1368 /* Wait a little for things to settle down */
1369 udelay(50);
1370 }
1371
1372 return 0;
1373 }
1374
gmc_v8_0_post_soft_reset(void * handle)1375 static int gmc_v8_0_post_soft_reset(void *handle)
1376 {
1377 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1378
1379 if (!adev->gmc.srbm_soft_reset)
1380 return 0;
1381
1382 gmc_v8_0_mc_resume(adev);
1383 return 0;
1384 }
1385
gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)1386 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1387 struct amdgpu_irq_src *src,
1388 unsigned type,
1389 enum amdgpu_interrupt_state state)
1390 {
1391 u32 tmp;
1392 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1393 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1394 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1395 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1396 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1397 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1398 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1399
1400 switch (state) {
1401 case AMDGPU_IRQ_STATE_DISABLE:
1402 /* system context */
1403 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1404 tmp &= ~bits;
1405 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1406 /* VMs */
1407 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1408 tmp &= ~bits;
1409 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1410 break;
1411 case AMDGPU_IRQ_STATE_ENABLE:
1412 /* system context */
1413 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1414 tmp |= bits;
1415 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1416 /* VMs */
1417 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1418 tmp |= bits;
1419 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1420 break;
1421 default:
1422 break;
1423 }
1424
1425 return 0;
1426 }
1427
gmc_v8_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1428 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1429 struct amdgpu_irq_src *source,
1430 struct amdgpu_iv_entry *entry)
1431 {
1432 u32 addr, status, mc_client, vmid;
1433
1434 if (amdgpu_sriov_vf(adev)) {
1435 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1436 entry->src_id, entry->src_data[0]);
1437 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1438 return 0;
1439 }
1440
1441 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1442 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1443 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1444 /* reset addr and status */
1445 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1446
1447 if (!addr && !status)
1448 return 0;
1449
1450 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1451 gmc_v8_0_set_fault_enable_default(adev, false);
1452
1453 if (printk_ratelimit()) {
1454 struct amdgpu_task_info task_info;
1455
1456 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
1457 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1458
1459 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
1460 entry->src_id, entry->src_data[0], task_info.process_name,
1461 task_info.tgid, task_info.task_name, task_info.pid);
1462 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1463 addr);
1464 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1465 status);
1466 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1467 entry->pasid);
1468 }
1469
1470 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1471 VMID);
1472 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1473 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1474 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1475 u32 protections = REG_GET_FIELD(status,
1476 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1477 PROTECTIONS);
1478
1479 info->vmid = vmid;
1480 info->mc_id = REG_GET_FIELD(status,
1481 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1482 MEMORY_CLIENT_ID);
1483 info->status = status;
1484 info->page_addr = addr;
1485 info->prot_valid = protections & 0x7 ? true : false;
1486 info->prot_read = protections & 0x8 ? true : false;
1487 info->prot_write = protections & 0x10 ? true : false;
1488 info->prot_exec = protections & 0x20 ? true : false;
1489 mb();
1490 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1491 }
1492
1493 return 0;
1494 }
1495
fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1496 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1497 bool enable)
1498 {
1499 uint32_t data;
1500
1501 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1502 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1503 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1504 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1505
1506 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1507 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1508 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1509
1510 data = RREG32(mmMC_HUB_MISC_VM_CG);
1511 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1512 WREG32(mmMC_HUB_MISC_VM_CG, data);
1513
1514 data = RREG32(mmMC_XPB_CLK_GAT);
1515 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1516 WREG32(mmMC_XPB_CLK_GAT, data);
1517
1518 data = RREG32(mmATC_MISC_CG);
1519 data |= ATC_MISC_CG__ENABLE_MASK;
1520 WREG32(mmATC_MISC_CG, data);
1521
1522 data = RREG32(mmMC_CITF_MISC_WR_CG);
1523 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1524 WREG32(mmMC_CITF_MISC_WR_CG, data);
1525
1526 data = RREG32(mmMC_CITF_MISC_RD_CG);
1527 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1528 WREG32(mmMC_CITF_MISC_RD_CG, data);
1529
1530 data = RREG32(mmMC_CITF_MISC_VM_CG);
1531 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1532 WREG32(mmMC_CITF_MISC_VM_CG, data);
1533
1534 data = RREG32(mmVM_L2_CG);
1535 data |= VM_L2_CG__ENABLE_MASK;
1536 WREG32(mmVM_L2_CG, data);
1537 } else {
1538 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1539 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1540 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1541
1542 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1543 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1544 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1545
1546 data = RREG32(mmMC_HUB_MISC_VM_CG);
1547 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1548 WREG32(mmMC_HUB_MISC_VM_CG, data);
1549
1550 data = RREG32(mmMC_XPB_CLK_GAT);
1551 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1552 WREG32(mmMC_XPB_CLK_GAT, data);
1553
1554 data = RREG32(mmATC_MISC_CG);
1555 data &= ~ATC_MISC_CG__ENABLE_MASK;
1556 WREG32(mmATC_MISC_CG, data);
1557
1558 data = RREG32(mmMC_CITF_MISC_WR_CG);
1559 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1560 WREG32(mmMC_CITF_MISC_WR_CG, data);
1561
1562 data = RREG32(mmMC_CITF_MISC_RD_CG);
1563 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1564 WREG32(mmMC_CITF_MISC_RD_CG, data);
1565
1566 data = RREG32(mmMC_CITF_MISC_VM_CG);
1567 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1568 WREG32(mmMC_CITF_MISC_VM_CG, data);
1569
1570 data = RREG32(mmVM_L2_CG);
1571 data &= ~VM_L2_CG__ENABLE_MASK;
1572 WREG32(mmVM_L2_CG, data);
1573 }
1574 }
1575
fiji_update_mc_light_sleep(struct amdgpu_device * adev,bool enable)1576 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1577 bool enable)
1578 {
1579 uint32_t data;
1580
1581 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1582 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1583 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1584 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1585
1586 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1587 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1588 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1589
1590 data = RREG32(mmMC_HUB_MISC_VM_CG);
1591 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1592 WREG32(mmMC_HUB_MISC_VM_CG, data);
1593
1594 data = RREG32(mmMC_XPB_CLK_GAT);
1595 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1596 WREG32(mmMC_XPB_CLK_GAT, data);
1597
1598 data = RREG32(mmATC_MISC_CG);
1599 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1600 WREG32(mmATC_MISC_CG, data);
1601
1602 data = RREG32(mmMC_CITF_MISC_WR_CG);
1603 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1604 WREG32(mmMC_CITF_MISC_WR_CG, data);
1605
1606 data = RREG32(mmMC_CITF_MISC_RD_CG);
1607 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1608 WREG32(mmMC_CITF_MISC_RD_CG, data);
1609
1610 data = RREG32(mmMC_CITF_MISC_VM_CG);
1611 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1612 WREG32(mmMC_CITF_MISC_VM_CG, data);
1613
1614 data = RREG32(mmVM_L2_CG);
1615 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1616 WREG32(mmVM_L2_CG, data);
1617 } else {
1618 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1619 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1620 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1621
1622 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1623 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1624 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1625
1626 data = RREG32(mmMC_HUB_MISC_VM_CG);
1627 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1628 WREG32(mmMC_HUB_MISC_VM_CG, data);
1629
1630 data = RREG32(mmMC_XPB_CLK_GAT);
1631 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1632 WREG32(mmMC_XPB_CLK_GAT, data);
1633
1634 data = RREG32(mmATC_MISC_CG);
1635 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1636 WREG32(mmATC_MISC_CG, data);
1637
1638 data = RREG32(mmMC_CITF_MISC_WR_CG);
1639 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1640 WREG32(mmMC_CITF_MISC_WR_CG, data);
1641
1642 data = RREG32(mmMC_CITF_MISC_RD_CG);
1643 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1644 WREG32(mmMC_CITF_MISC_RD_CG, data);
1645
1646 data = RREG32(mmMC_CITF_MISC_VM_CG);
1647 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1648 WREG32(mmMC_CITF_MISC_VM_CG, data);
1649
1650 data = RREG32(mmVM_L2_CG);
1651 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1652 WREG32(mmVM_L2_CG, data);
1653 }
1654 }
1655
gmc_v8_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1656 static int gmc_v8_0_set_clockgating_state(void *handle,
1657 enum amd_clockgating_state state)
1658 {
1659 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1660
1661 if (amdgpu_sriov_vf(adev))
1662 return 0;
1663
1664 switch (adev->asic_type) {
1665 case CHIP_FIJI:
1666 fiji_update_mc_medium_grain_clock_gating(adev,
1667 state == AMD_CG_STATE_GATE);
1668 fiji_update_mc_light_sleep(adev,
1669 state == AMD_CG_STATE_GATE);
1670 break;
1671 default:
1672 break;
1673 }
1674 return 0;
1675 }
1676
gmc_v8_0_set_powergating_state(void * handle,enum amd_powergating_state state)1677 static int gmc_v8_0_set_powergating_state(void *handle,
1678 enum amd_powergating_state state)
1679 {
1680 return 0;
1681 }
1682
gmc_v8_0_get_clockgating_state(void * handle,u64 * flags)1683 static void gmc_v8_0_get_clockgating_state(void *handle, u64 *flags)
1684 {
1685 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1686 int data;
1687
1688 if (amdgpu_sriov_vf(adev))
1689 *flags = 0;
1690
1691 /* AMD_CG_SUPPORT_MC_MGCG */
1692 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1693 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1694 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1695
1696 /* AMD_CG_SUPPORT_MC_LS */
1697 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1698 *flags |= AMD_CG_SUPPORT_MC_LS;
1699 }
1700
1701 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1702 .name = "gmc_v8_0",
1703 .early_init = gmc_v8_0_early_init,
1704 .late_init = gmc_v8_0_late_init,
1705 .sw_init = gmc_v8_0_sw_init,
1706 .sw_fini = gmc_v8_0_sw_fini,
1707 .hw_init = gmc_v8_0_hw_init,
1708 .hw_fini = gmc_v8_0_hw_fini,
1709 .suspend = gmc_v8_0_suspend,
1710 .resume = gmc_v8_0_resume,
1711 .is_idle = gmc_v8_0_is_idle,
1712 .wait_for_idle = gmc_v8_0_wait_for_idle,
1713 .check_soft_reset = gmc_v8_0_check_soft_reset,
1714 .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1715 .soft_reset = gmc_v8_0_soft_reset,
1716 .post_soft_reset = gmc_v8_0_post_soft_reset,
1717 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1718 .set_powergating_state = gmc_v8_0_set_powergating_state,
1719 .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1720 };
1721
1722 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1723 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1724 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
1725 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1726 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1727 .set_prt = gmc_v8_0_set_prt,
1728 .get_vm_pde = gmc_v8_0_get_vm_pde,
1729 .get_vm_pte = gmc_v8_0_get_vm_pte,
1730 .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size,
1731 };
1732
1733 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1734 .set = gmc_v8_0_vm_fault_interrupt_state,
1735 .process = gmc_v8_0_process_interrupt,
1736 };
1737
gmc_v8_0_set_gmc_funcs(struct amdgpu_device * adev)1738 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1739 {
1740 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1741 }
1742
gmc_v8_0_set_irq_funcs(struct amdgpu_device * adev)1743 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1744 {
1745 adev->gmc.vm_fault.num_types = 1;
1746 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1747 }
1748
1749 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1750 {
1751 .type = AMD_IP_BLOCK_TYPE_GMC,
1752 .major = 8,
1753 .minor = 0,
1754 .rev = 0,
1755 .funcs = &gmc_v8_0_ip_funcs,
1756 };
1757
1758 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1759 {
1760 .type = AMD_IP_BLOCK_TYPE_GMC,
1761 .major = 8,
1762 .minor = 1,
1763 .rev = 0,
1764 .funcs = &gmc_v8_0_ip_funcs,
1765 };
1766
1767 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1768 {
1769 .type = AMD_IP_BLOCK_TYPE_GMC,
1770 .major = 8,
1771 .minor = 5,
1772 .rev = 0,
1773 .funcs = &gmc_v8_0_ip_funcs,
1774 };
1775